Interface potential barrier height and leakage current behavior of Pt/(Ba,Sr)TiO3/Pt capacitors fabricated by sputtering process

Abstract

Variations of the leakage current behaviors and interface potential barrier height (φ _B ) of rf-sputter deposited (Ba, Sr)TiO₃ (BST) thin films, with thickness ranging from 20nm to 150 nm are investigated as a function of the thickness and bias voltages. The top and bottom electrodes are dc-sputter-deposited Pt films. φ _B critically depends on the BST film deposition temperature, postannealing atmosphere and time after the annealing. The postannealing under N₂ atmosphere results in a high interface potential barrier height and low leakage current. Maintaining the BST capacitor in air for a long time reduces the φ _B from about 2.4 eV to 1.6eV due to the oxidation. φ _B is not so dependent on the film thickness in this experimental range. The leakage conduction mechanism is very dependent on the BST film thickness; the 20nm thick film shows tunneling current, 30 and 40 nm thick films show Schottky emission current and the thicker films show a mixed characteristics and bulk and interface limited currents although the mechanism is not clearly understood at this moment.     

Statistical study of the effect of interface charge fluctuations in HEMTs using a 3D simulator

The intrinsic parameter fluctuations associated with the discreteness of charge and matter become an important factor when the semiconductor devices are scaled to nanometre dimensions. The interface charge in the recess regions of high electron mobility transistors (HEMTs) has a considerable effect on the overall device performance. We have employed a 3D parallel drift-diffusion device simulator to study the impact of interface charge fluctuations on the I-V characteristics of nanometre HEMTs. For this purpose, two devices have been analysed, a 120 nm gate length pseudomorphic HEMT with an In_0.2Ga_0.8As channel and a 50 nm gate length InP HEMT with an In_0.7Ga_0.3As channel.     

RF Performance of Strained SiGe pMOSFETs: Linearity and Gain

The RF performance of strained-SiGe pMOSFETs on SOI substrates has been investigated through the use of TCAD simulations. To optimize RF performance of strained-SiGe pMOSFETs, including intrinsic gain, linearity and g_m/I_d, we propose to vary the Ge concentration in the channel, shrink the SOI thickness and adopt an asymmetric doping profile along the channel. We find that neither strain nor the asymmetric doping approach is able to unlock the trade-off between intrinsic gain and linearity found in bulk and SOI relaxed Si MOSFETs. Instead, SOI layer thickness control provides an alternative approach to improving gain without sacrificing linearity. For optimized RF performance, the strained-SiGe pMOSFETs with high Ge concentrations (0.3 ≤ x ≤ 0.7) in the channel and thin SOI layers (< 20 nm) are preferred.     

Variations of interface potential barrier height and leakage current of (Ba,Sr)TiO3 thin films deposited by sputtering process

Abstract

Variations of the leakage current behaviors and interface potential barrier height (Φ_B) of rf-sputter deposited (Ba, Sr)TiO₃ (BST) thin films with thicknesses ranging from 20 nm to 150 nm are investigated as a function of the thickness and bias voltages. The top and bottom electrodes are dc-sputter-deposited Pt films. Φ_B critically depends on the BST film deposition temperature, postannealing atmosphere and time after the annealing. The postannealing under N₂ atmosphere results in a high interface potential barrier height and low leakage current. Maintaining the BST capacitor in air for a long time reduces the Φ_B from about 2.4 eV to 1.6 eV due to the oxidation. Φ_B is not so dependent on the film thickness in this experimental range. The leakage conduction mechanism is very dependent on the BST film thickness; the 20 nm thick film shows tunneling current, 30 and 40 nm thick films show Schottky emission current.     

Sensitivity of single- and double-gate MOS architectures to residual discrete dopant distribution in the channel

The effect of a single discrete impurity in the channel of Fully-Depleted Single- and Double-Gate MOSFETs is analyzed by means of 3D Monte Carlo simulation. The Double-Gate (DG) architecture appears to be less sensitive to the dopant perturbation than the Single-Gate (SG) counterpart. For an N-channel device the influence of a P-type impurity on the current-voltage characteristics is shown to be strongly dependent on the impurity position in the channel. The maximum current degradation is obtained for an impurity located about 5 nm from the source-end of the channel. The I _on reduction reaches 6% in DG and 10.5% in SG. A small current enhancement (less than 2%) is induced by an N-type impurity. These results are analyzed in terms of velocity profile between source and drain.     

Impact of high‐κ gate dielectric and other physical parameters on the electrostatics and threshold voltage of long channel gate‐all‐around nanowire transistor

High‐κ gate‐all‐around structure counters the Short Channel Effect (SCEs) mostly providing excellent off‐state performance, whereas high mobility III–V channel ensures better on‐state performance, rendering III–V nanowire GAAFET a potential candidate for replacing the current FinFETs in microchips. In this paper, a 2D simulator for the III–V GAAFET based on self‐consistent solution of Schrodinger–Poisson equation is proposed. Using this simulator, capacitance–voltage profile and threshold voltage are characterized, which reveal that gate dielectric constant (κ) and oxide thickness do not affect threshold voltage significantly at lower channel doping. Moreover, change in alloy composition of In_xGa_1‐xAs, channel doping, and cross‐sectional area has trivial effects on the inversion capacitance although threshold voltage can be shifted by the former two. Although, channel material also affects the threshold voltage, most sharp change in threshold voltage is observed with change in fin width of the channel (0.005 V/nm for above 10 nm fin width and 0.064 V/nm for sub‐10 nm fin width). Simulation suggests that for lower channel doping below 10²³ m⁻³, fin width variation affects the threshold voltage most. Whereas when the doping is higher than 10²³ m⁻³, both the thickness and dielectric constant of the oxide material have strong effects on threshold voltage (0.05 V/nm oxide thickness and 0.01 V/per unit change in κ). Copyright © 2014 John Wiley & Sons, Ltd.     

EnergyDispersion Relations for Holes in Silicon Quantum Wells and Quantum Wires

We calculate the energy dispersion relations in Si quantum wells (QW), E(k _2D), and quantum wires (QWR), E(k _1D), focusing on the regions with negative effective mass (NEM) in the valence band. The existence of such NEM regions is a necessary condition for the current oscillations in ballistic quasineutral plasma in semiconductor structures. The frequency range of such oscillations can be extended to the terahertz region by scaling down the length of structures. Our analysis shows that silicon is a promising material for prospective NEM-based terahertz wave generators. We also found that comparing to Si QWRs, Si QWs are preferable structures for NEM-based generation in the terahertz range.     

Analysis of work of liquid metal induction pump

Contents In the paper the finite element method is presented so as to determine electromagnetic field distribution in a cylindrical liquid metal induction pump. The effect of exciting current frequency, the channel width and the channel material conductivity on dynamic parameters of the pump has been analysed. — The obtained calculation results have been shown in the graphs.

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Analyse der Pumpe für ein flüssiges Metall

Übersicht Im Beitrag wurde die Methode der finiten Elemente zur Bestimmung der Verteilung des elektromagnetischen Feldes in einer zylindrischen Pumpe für ein flüssiges Metall verwendet. Man hat den Einfluß des Erregerstroms, der Kanalbreite und der Leitfähigkeit des zum Aufbau des Kanals benutzten Stoffes — auf die dynamischen Parameter dieser Pumpe untersucht. Die erhaltenen Ergebnisse hat man in Form von Diagrammen dargestellt.

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List of symbols A vector potential - A vector potential (complex r.m.s. value) - A z-component of vector potential (complex r.m.s. value) - A _i ,A _j ,A _k vector potential values in nodal pointsi, j, k (complex r.m.s. values) - B magnetic induction - B magnetic induction (complex r.m.s. value) - B _x ,B _y components of magnetic induction (complex r.m.s. values) - F _t electrodynamic force - F mean force - F _a alternating force - F _x ,F _y components of the mean force - conductivity of the liquid metal - J current density (complex r.m.s. value) - J _a current density - J _w exciting current linear density (complex r.m.s. value) - l length of the channel - magnetic permeability of the liquid metal - M torque acting upon the liquid metal - current pulsation - p pressure of transported metal - Q pump efficiency - v _x ,v _y components of the liquid metal's velocity in the 0X and 0Y direction - z ^* conjugate complex number ofz     

Monte Carlo analysis of dynamic characteristics and high‐frequency noise performances of nanoscale double‐gate MOSFETs

In this paper, a full‐band Monte Carlo simulator is employed to study the dynamic characteristics and high‐frequency noise performances of a double‐gate (DG) metal–oxide–semiconductor field‐effect transistor (MOSFET) with 30 nm gate length. Admittance parameters (Y parameters) are calculated to characterize the dynamic response of the device. The noise behaviors of the simulated structure are studied on the basis of the spectral densities of the instantaneous current fluctuations at the drain and gate terminals, together with their cross‐correlation. Then the normalized noise parameters (P, R, and C), minimum noise figure (NF_min), and so on are employed to evaluate the noise performances. To show the outstanding radio‐frequency performances of the DG MOSFET, a single‐gate silicon‐on‐insulator MOSFET with the same gate length is also studied for comparison. The results show that the DG structure provides better dynamic characteristics and superior high‐frequency noise performances, owing to its inherent short‐channel effect immunity, better gate control ability, and lower channel noise. Copyright © 2012 John Wiley & Sons, Ltd.     

Random Telegraph Noise in 30 nm FETs with Conventional and High-κ Dielectrics

The magnitude of fractional current variation in ultra-small (30 nm channel length) MOSFETs due to single charge trapping-detrapping events at any position within the gate dielectric is studied using numerical simulation. These random telegraph signals in the drain current indicate the amplitude of low frequency MOSFET noise. Simulations are performed for realistic devices with poly-silicon gates subject to poly-silicon depletion, and for both SiO₂ and HfO₂ as dielectric materials.     

An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano‐circuit simulation. The FinFET used in this work is designed using careful engineering of source–drain extension, which simultaneously improves maximum frequency of oscillation ƒ_max because of lower gate to drain capacitance, and intrinsic gain A_V0 = g_m/g_ds, due to lower output conductance g_ds. The framework for the ANN‐based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I_d on drain–source V_ds and gate–source V_gs is derived by a simple two‐layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low‐noise amplifier. At low power (J_ds∼10 µA/µm) improvement was observed in both third‐order‐intercept IIP₃ (∼10 dBm) and intrinsic gain A_V0 (∼20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first‐order to third‐order derivative of I_d with respect to gate voltage and lower g_ds in FinFET compared to bulk MOSFET. Copyright © 2009 John Wiley & Sons, Ltd.     

NEGF simulations of the effect of strain on scaled double gate nanoMOSFETs

The effect of biaxial strain on double gate (DG) nanoscaled Si MOSFET with channel lengths in the nanometre range is investigated using Non-Equilibrium Green’s Functions (NEGF) simulations. We have employed fully 2D NEGF simulations in order to answer the question at which body thickness the effects of strain is masked by the confinement impact. Following ITRS, we start with a 14 nm gate length DG MOSFET having a body thickness of 9 nm scaling the transistors to gate lengths of 10, 6 and 4 nm and body thicknesses of 6.1, 2.6 and 1.3 nm. The simulated I _D–V _G characteristics show a 6% improvement in the on-current for the 14 nm gate length transistor mainly due to the energy separation of the Δ valleys. The strain effect separates the 2 fold from the 4 fold valleys thus keeping mostly operational transverse electron effective mass in the transport direction. However, in the device with an extreme body thickness of 1.3 nm, the strain effect has no more impact on the DG performance because the strong confinement itself produces a large energy separation of valleys.     

Silicon-Germanium Structure in Surrounding-Gate Strained Silicon Nanowire Field Effect Transistors

In this paper we numerically examine the electrical characteristics of surrounding-gate strained silicon nanowire field effect transistors (FETs) by changing the radius (R_SiGe) of silicon-germanium (SiGe) wire. Due to the higher electron mobility, the n-type FETs with strained silicon channel films do enhance driving capability (∼8% increment on the drain current) in comparison with the pure Si one. The leakage current and transfer characteristics, the threshold-voltage (V_t), the drain induced barrier height lowering (DIBL), and the gate capacitance (C_G) are estimated with respect to different gate length (L_G), gate bias (V_G), and R_SiGe. For short channel effects, such as V_t roll-off and DIBL, the surrounding-gate strained silicon nanowire FET sustains similar characteristics with the pure Si one.     

Magnetic core properties and their thermal stability in a BCC Fe-Zr-B-Cu alloy with nanoscale grain size

A mostly single bcc phase with nanoscale grain size of 10 to 20 nm has been found to form by annealing amorphous Fe-Zr-B, Fe-Hf-B and Fe-M-B-Cu (M = Ti, Zr, Hf, Nb and Ta) alloys. It has further been clarified that the newly developed nanocrystalline bcc alloys exhibit high permeability (μ_e) combined with high saturation magnetization (B_s). Subsequently, the possible application potentials of the bcc alloys were investigated. The core loss is as small as 66 mW/kg at 1 T and 50 Hz for a nanocrystalline bcc Fe₈₆Zr₇B₆Cu₁ alloy obtained by annealing for 3.6 ks at 873 K. This value is 45 and 95 percent smaller than those for amorphous Fe₈₆Si₉B₁₃ alloy and Fe-3.5 percent Si alloy, respectively, which are presently in use as core materials in electric power transformers. The frequency dependence of the core loss for the bcc alloy at 0.2 T is almost the same as that for an amorphous Co_70.5Fe_4.5Si₁₀B₁₅ alloy with zero magnetostriction. In the frequency range of 10 to 300 kHz, the core loss for the bcc alloy is slightly smaller than the Co base amorphous which has been used as core material in high-frequency transformers. Furthermore, the core losses of the nanocrystalline Fe₈₆Zr₇B₆Cu₁ alloy also were found to have high stability against thermal aging. Thus, nanocrystalline bcc Fe-Zr-B-Cu alloys with the advantages of high B_s, high μ_e, and low core loss is expected to be used as a core material in various transformers.     

The role of the source and drain contacts on self-heating effect in nanowire transistors

We find that self-heating effects are not pronounced in silicon nanowire transistors with channel length 10 nm even in the presence of the wrap-around oxide. We observe a maximum current degradation of 6% for V _G =V _D =1.0 V in a structure in which the metal gates are far away from the channel. The overall small current degradation is attributed to the significant velocity overshoot effect in these structures. The lattice temperature profile shows moderate temperature rise and velocity of the carriers is slightly deteriorated due to self-heating effects when compared to isothermal simulations.     

Scaling MOSFETs to 10 nm: Coulomb effects, source starvation, and virtual source model

In our attempts to scale FETs to the 10 nm length, alternatives to conventional Si CMOS are sought on the grounds that: (1) Si seems to have reached its technological and performance limits and (2) the use of alternative high-mobility channel materials will provide the missing performance. With the help of numerical simulations here we establish the reasons why indeed Si seems to have hit an intrinsic performance barrier and whether or not high mobility semiconductors can indeed grant us our wishes. The role of long-and short-range electron-electron interactions are revisited together with a recent analysis of the historical performance trends. The density-of-states (DOS) bottleneck and source starvation issues are also reviewed to see what advantage alternative substrates may bring us. Finally, the well-known ‘virtual source model’ is analyzed to assess whether it can be used as a quantitative tool to guide us to the 10 nm gate length.     

Increase of breakdown voltage due to composite insulation in SF6 gas

The breakdown characteristics using a hemispherical tip rod (10 ～ 60 mm) molded with epoxy resin-to-plate gap in SF₆ gas up to 0.20 MPa was studied. The result shows that breakdown characteristics are classified into three regions (A, B and C region) depending on gap length. In the A-region breakdown voltage is lowered compared with bare hemispherical tip rod-to-plate gap. In the B-region breakdown voltage is raised sharply with gap length and in the C-region it saturates. The maximum increase ratio of breakdown voltage in the B and C region are 1.95 times (ac) and 1.68 times (impulse) compared with a bare hemispherical tip rod-to-plate gap characteristic. The ratios depend on the diameter of the spherical tip rod and the thickness of epoxy resin. It is concluded that the increase of breakdown voltage is attributed to the synergism effect of the decrease of maximum electric field strength by epoxy resin and the suppression of field emission. The use of composite insulation reduces the gap length drastically in the gas-insulated switchgear, for instance, C-GIS (Cubicle-type Gas-Insulated Switchgear).     

Enhancing the performances of recycling folded cascode OpAmp in nanoscale CMOS through voltage supply doubling and design for reliability

Current‐oriented operational amplifier (OpAmp) design has been common for its orderly current‐to‐speed tradeoff. However, for high‐precision or high‐linearity applications, increasing the current does not help much, as the supply voltage (V_DD) and intrinsic gain of the MOSFETs in ultra‐scaled CMOS technologies are very limited. This paper introduces voltage‐oriented circuit techniques to address such limitations. Specifically, a 2xV_DD‐enabled recycling folded cascade (RFC) OpAmp is proposed. It features: (1) current recycling to enhance the effective trans conductance by 4x with no extra power; (2) transistor stacking to boost the output resistance by one to two orders of magnitude; and (3) V_DD elevating to enlarge the linear output swing by 4x. Comparing with its 1xV_DD RFC and FC counterparts, the proposed solution achieves 20‐dB higher DC gain (i.e. 72.8 dB) in open loop and 20‐dB lower IM3 (i.e., –76.5 dB) in closed loop, under the same power budget of 0.6 mW in a 1‐V General Purpose 65‐nm CMOS process. In many applications, these joint improvements in a single stage are already adequate, being more power efficient (i.e. less current paths), stable (i.e. more phase margin), and compact (i.e. no frequency compensation) than multi‐stage OpAmps. Voltage‐conscious biasing and node‐voltage trajectory check ensure the device reliability in both transient and steady states. No specialized high‐voltage device is necessary. Copyright © 2012 John Wiley & Sons, Ltd.     

Impact of channel length,gate insulator thickness,gate insulator material,and temperature on the performance of nanoscale FETs

Aggressive technology scaling as per Moore’s law has led to elevated power dissipation levels owing to an exponential increase in subthreshold leakage power. Short channel effects (SCEs) due to channel length reduction, gate insulator thickness change, application of high-k gate insulator, and temperature change in a double-gate metal–oxide–semiconductor field-effect transistor (DG MOSFET) and carbon nanotube field-effect transistor (CNTFET) were investigated in this work. Computational simulations were performed to investigate SCEs, viz. the threshold voltage (V_th) roll-off, subthreshold swing (SS), and I_on/I_off ratio, in the DG MOSFET and CNTFET while reducing the channel length. The CNTFET showed better performance than the DG MOSFET, including near-zero SCEs due to its pure ballistic transport mechanism. We also examined the threshold voltage (V_th), subthreshold swing (SS), and I_on/I_off ratio of the DG MOSFET and CNTFET with varying gate insulator thickness, gate insulator material, and temperature. Finally, we handpicked almost similar parameters for both the CNTFET and DG MOSFET and carried out performance analysis based on the simulation results. Comparative analysis of the results showed that the CNTFET provides 47.8 times more I_on/I_off ratio than the DG MOSFET. Its better control over the threshold voltage, near-zero SCEs, high on-current, low leakage power consumption, and ability to operate at high temperature make the CNTFET a viable option for use in enhanced switching applications and low-voltage digital applications in nanoelectronics.     

Research on high-performance Nd?Fe?B magnets

The effects of the constituent phase of Nd-Fe-B magnets on sintering behavior are investigated. In the case of Nd-Fe-B magnets, a liquid phase forms by ternary eutectic reaction of Nd₂Fe₁₄B, Nd_1.1Fe₄B₄ and Nd-rich phase at 938 K. When the sintering temperature is raised above 1273 K, a remarkable shrinking occurs because of an increase in the amount of liquid phase which is supplied by the reaction between the Nd₂Fe₁₄B and the Nd_1.1Fe₄B₄ phase. The residual flux density (B_r) of Nd-Fe-B magnets increases in proportion to the increase in the among of the Nd₂Fe₁₄B phase. By contrast, the intrinsic coercivity (_iH_c) declined because of a decrease in the amount of the Nd_1.1Fe₄B₄ and the Nd-rich phase. As a result, new high-performance Nd-Fe-B magnets with the maximum energy product of above 366 kJ/m³ (46 mgOe) have been developed by means of controlling the component ratios of these phases in Nd-Fe-B magnets.