Moisture induced degradation of multilayer ceramic capacitors

When both precious metal electrode and base metal electrode (BME) capacitors were subjected to autoclave (121 °C/100% RH) testing for 500 h, it was found that the precious metal capacitors aged according to a well known aging mechanism (average capacitance degraded less than 3% from their starting values), but the BME capacitors degraded to below the −30% specification limit. One hypothesis for this new failure mechanism was that there could be oxidation or corrosion of the nickel plates. Another hypothesis was that the loss of capacitance was due to chemical changes in the barium titanate.This paper presents the evaluation of the two hypotheses and the physics of the degradation mechanism. It is concluded that there are chemical changes in the barium titanate resulting from the interaction of residual point defects from BME manufacturing and humidity in the field. The continuous reduction in capacitor size makes the newer base metal electrode capacitors more vulnerable to moisture degradation than the older generation precious metal capacitors. In addition, standard humidity life testing, such as JESD-22 THB and HAST, will likely not uncover this problem. Therefore, poor reliability due to degradation of base metal electrode multilayer ceramic capacitors may catch manufacturers and consumers by surprise.     

多层瓷介电容器绝缘特性RC的研究

采用N-沟道MOS场效应晶体管搭建电路,测得了多层瓷介电容器通过本身绝缘电阻放电的时间常数τ,对比了Ni和Pd/Ag内电极多层瓷介电容器的绝缘特性RC(绝缘电阻乘以电容量)指标,分析了Ni内电极绝缘特性较差的原因和潜在风险。结果表明:RC反映了介质材料的本身属性,代表电容器通过本身绝缘电阻放电的时间常数τ;Ni内电极的RC考核指标相对于Pd/Ag内电极从1 000 s降至100 s;Ni内电极多层瓷介电容器在高可靠长寿命电路使用时应提高其绝缘特性RC的考核指标。     

Detection of cracks in multilayer ceramic capacitors by X-ray imaging

A non-destructive method using X-ray imaging to find cracks in multilayer ceramic capacitors (MLCCs) mounted in different orientations with respect to the bending direction is presented. In total 300 MLCCs were investigated by 2D and 3D X-ray imaging after bending to varying levels of strain, and cross-section analysis was done to verify the findings. With X-ray imaging it was possible to not only detect the continuously cracked MLCCs, but also the cracked ones which were mounted 45° to the bending direction. These non-continuous cracks are difficult to identify even with cross-section analysis because the crack can be absent at the selected interface. None of the cracks could be identified by external optical inspection of the components using optical microscopy. The MLCCs mounted perpendicular to the bending direction were not cracked during the experiments, whereas the MLCCs mounted 45° or parallel to the bending direction were cracking at 3100 and 4300 μStr, respectively. Finding cracks with a non-invasive technique such as X-ray imaging is very advantageous because of its possible implementation as a screening test in a production environment.     

一种MLCC焊接失效分析

为找出某厂生产的多层陶瓷电容器端电极存在焊接失效的原因,运用体视显微镜、扫描电子显微镜和能谱仪对问题批次样品的端电极进行分析。从分析结果可知,在多层陶瓷电容器Cu端电极烧结过程中,Cu端表面有玻璃相溢出,这导致端电极部分区域的Ni层和Sn层电镀异常,最终造成电容器的焊接失效。经过对玻璃相溢出原理的分析,提出可以从铜浆料选择、烧结温度和封端工艺方面来解决该问题。     

Ni电极X8R多层陶瓷电容器的制备及性能

采用具有抗还原性的X8R瓷粉、镍内电极浆料和柔性导电端头浆料为原料,制备了Ni电极X8R多层陶瓷电容器(MLCC),研究了烧结升温速率以及柔性导电端头浆料对所制MLCC性能的影响。结果表明:最佳烧结升温速率为2℃/min,制备的Ni电极X8R-MLCC在-55～+150℃范围内,容量变化率≤±15%,电性能优良,可靠性高,适用于汽车电子等高温应用领域。     

多层陶瓷电容器端电极用低温烧结铜浆及烧结特性研究

多层陶瓷电容器(MLCC)端电极低温烧结技术仍是目前研究的重点与难点.为了改善MLCC低温烧结铜端电极的烧结形貌与质量,开发出适用于低温烧结的端电极铜浆的新型玻璃粉,探讨了玻璃粉的转变温度、含量、粒径以及玻璃粉与陶瓷基片的烧结润湿性与铜浆烧结特性之间的关系.此外,研究了铜粉形貌、粒径等对端电极烧结特性的影响.结果表明:...     

耐高温BNT-BT陶瓷电容器的制备及性能研究

采用氧化铋、碳酸钠、二氧化钛和钛酸钡为原料,制备了0.05Na0.5Bi0.5TiO3-0.95BaTiO3(BNT-BT)二元体系陶瓷。研究了BiNbO4和Nb2O5掺杂量对BNT-BT陶瓷的介电性能和容温变化率的影响。结果发现,对BNT-BT陶瓷掺杂摩尔分数为3.0%的BiNbO4和4.0%的Nb2O5时,获得了在–55~+200℃容温变化率都在±15%以内,且常温1 kHz下εr为1 297,tanδ为1.25×10–2的高稳定性、高性能MLCC。     

Rapid nondestructive testing of ceramic multilayer capacitors :

系统介绍了开路、短路和电参数漂移这三种主要的MLCC失效模式,以及介质层内空洞和电极结瘤、介质层分层、热应力和机械应力引起介质层裂纹、其他微观机理等五种主要的失效机理。针对MLCC的失效分析技术,从生产工艺和使用设计上提出了预防MLCC失效的措施。     

多层瓷介电容器失效模式和机理

系统介绍了开路、短路和电参数漂移这三种主要的MLCC失效模式,以及介质层内空洞和电极结瘤、介质层分层、热应力和机械应力引起介质层裂纹、其他微观机理等五种主要的失效机理。针对MLCC的失效分析技术,从生产工艺和使用设计上提出了预防MLCC失效的措施。     

Characteristics of a micromachined piezovalve combined with a multilayer ceramic actuator

This paper describes the design, fabrication and characteristics of a micromachined piezoelectric valve utilizing a multilayer ceramic actuator (MCA). The micromachined MCA valve, which uses a buckling effect, consists of three separate structures: the MCA, the valve actuator die and the seat die. The valve seat die with six trenches was made, and the actuator die, which is driven by the MCA under optimized conditions, was also fabricated. After Si wafer direct bonding between the seat die and the actuator die, the MCA was also anodically bonded to the seat/actuator die structure. A polydimethylsiloxane (PDMS) sealing pad was fabricated to minimize the leak rate. Finally, the PDMS sealing pad was also bonded to the seat die and the stainless steel package. The MCA valve shows a flow rate of 9.13 sccm at an applied DC voltage of 100 V with a 50% duty cycle and a maximum non-linearity of 2.24% FS. Therefore, the fabricated MCA valve is suitable for a variety of flow control equipment, as a medical bio-system and in the automobile industry.     

成型工艺对高介单层微波陶瓷电容器性能的影响

分别采用轧膜与流延两种成型工艺制备了SrTiO3高介单层微波陶瓷电容器材料,对比研究了两种成型工艺对其结构与性能的影响。研究表明:对于轧膜工艺而言,电容器陶瓷材料的εr和密度随着轧膜次数增加呈单峰效应,瓷料脱辊后轧膜70次左右可获得表面平整、结构致密、介电性能良好的电容器陶瓷材料。和流延工艺相比,轧膜工艺制备的电容器陶瓷材料εr较大,电容量温度变化率较小。     

电解电容器脉冲老练法及电源的研制

在氧化膜修补机制的基础上,分析了老练工序费时的根本原因,并据此研究了脉冲老练法,开发出脉冲老练电源。对比实验表明,可将高压老练时间从11.0h缩短到2.5h,能保证电容器具有同等的电性能与寿命,且对高温贮存寿命试验的漏电流回升有明显改善,可节约高压电容器的制造成本5%～10%。     

Testing the effects of reflow on tantalum capacitors

This study focuses on testing the effects of one and several reflow processes on surface mount tantalum capacitor characteristics, especially in a humid environment. Effects on maximum voltage, moisture absorption, and durability in the standard 85/85 test were examined. Research was done by using a 0–90 V voltage test, a 100% RH moisture absorption test, and the standard 85/85 test. Results show that a reflow process weakens the characteristics of tantalum capacitors and also affects their moisture absorption. Several reflow processes have a greater effect. Possible reasons are discussed in this paper.     

Isothermal aging of near-eutectic Sn-Ag-Cu solder alloys and its effect on electrical resistivity

Solder joints were prepared from seven eutectic and near-eutectic Sn-based compositions and characterized for electrical resistivity after 100 h and 1,000 h of isothermal aging at 423 K. The solder joint samples were prepared by hand soldering to copper substrates, and the post-heat treatment resistivity was measured at room temperature in a specially designed, four-point probe fixture. Compositions tested included Sn-3.5Ag, Sn-3.7Ag-0.9Cu, Sn-3.0Ag-0.5Cu, Sn-3.6Ag-1.0Cu, and Sn-3.9Ag-0.6Cu. In addition, the effect of a minor addition of a fourth element, designed to improve high-temperature shear strength, was also evaluated in the compositions Sn-3.7Ag-0.6Cu-0.3Co and Sn-3.7Ag-0.7Cu-0.2Fe. The observed changes in electrical resistivity are discussed in terms of microstructural coarsening, diffusional transport from the substrate, and nucleation of precipitate phases.     

Isothermal aging effects on the microstructure and solder bump shear strength of eutectic Sn37Pb and Sn3.5Ag solders

The reliability of the eutectic Sn37Pb (63%Sn37%Pb) and Sn3.5Ag (96.5%Sn3.5%Ag) solder bumps with an under bump metallization (UBM) consisting of an electroless Ni(P) plus a thin layer of Au was evaluated following isothermal aging at 150 °C. All the solder bumps remained intact after 1500 h aging at 150 °C. Solder bump microstructure evolution and interface structure change during isothermal aging were observed and correlated with the solder bump shear strength and failure modes. Cohesive solder failure was the only failure mode for the eutectic Sn37Pb solder bump, while partial cohesive solder failure and partial Ni(P) UBM/Al metallization interfacial delamination was the main failure mode for eutectic Sn3.5Ag solder bump.     

Temperature and voltage aging effects on electrical conduction mechanism in epoxy-BaTiO3 composite dielectric used in embedded capacitors

The electrical conduction mechanism in an embedded capacitor with epoxy-BaTiO₃ composite dielectric and Cu electrodes is investigated in this paper. Leakage current was measured across the dielectric by performing a voltage sweep from 0 to 100 V. The voltage sweep was performed at temperatures ranging from 25 °C to 125 °C. Various electrical conduction models such as Schottky, Poole-Frenkel, and ionic hopping were evaluated by comparing the functional dependence of leakage current on temperature and voltage for each mechanism which was considered. It was observed that the conduction mechanism was most consistent with Schottky emission. The contact potential barrier corresponding to Schottky emission was found to be 1.29 eV.The effect of combined temperature and voltage aging on the conduction mechanism was investigated by aging the embedded capacitor dielectric at 125 °C and 100 V for 1680 h. To investigate the difference between combined temperature and voltage aging and temperature aging alone, some capacitors were aged only by temperature at 125 °C for 1680 h. Measurements of leakage current as a function of temperature and voltage were performed at frequent intervals during the aging. It was observed that the value of leakage current did not increase during temperature and voltage aging unlike pure BaTiO₃ dielectrics.     

老练电压对铝电解电容器容量和漏电流的影响

老练电压对铝电解电容器的容量和漏电流有一定影响,对于低压（≤１６Ｖ）产品要确保老练电压的准确性;对高压（≤１００Ｖ）小容量产品,若容量偏差过大,可适当加高老练电压使其降低。老练后漏电流大的产品,加高老练电压也有良好效果。     

Testing the effects of temperature cycling on tantalum capacitors

This study focused on the reliability testing of tantalum capacitors. The objective was to develop efficient tests to examine the effects of temperature cycling on capacitor maximum voltage. A test according to the standard JESD22-A104D overlooks the fact that temperature changes often occur while the voltage is on. Capacitors were first tested according to the standard without voltage; the test was then repeated with added 15 V and 30 V. Second, short cycling tests were run at different temperatures to detect any changes in capacitor characteristics. After the cycling tests, capacitors were tested for voltage, which was slowly increased from 0 V to 90 V, provided no failure occurred. Results suggest that a temperature cycling effect can be achieved in a much shorter time than in standard tests. Temperature cycling can also be accelerated by adding voltage. Possible reasons are discussed in the paper.     

Numerical analysis of delamination and cracking phenomena in multi-layered flexible electronics

The first part of this paper deals with the analysis of layer buckling and delamination of thin film multi-layer structures that are used in flexible display applications. To this end, 250 nm thick indium tin oxide (ITO) layers have been deposited on a thick high temperature aromatic polyester substrate (Arylite™) with a silica–acrylate hybrid hard coat (HC). Typical buckle morphologies are determined from two-point bending experiments, in which buckle geometries are measured after straightening of the sample. Finite element simulations have been performed to estimate the corresponding interface properties and compressive strains in the layers, and to illustrate the effect of sample straightening on the buckle geometry. The second part considers the fracture sensitivity analysis of an active matrix Thin Film Transistor (TFT) display containing 512 × 256 pixels, with a typical pixel dimension of . Due to the large scale differences between the display and the TFT patterning a multi-scale modelling framework has been developed, which allows to include realistic material stacks and a detailed pixel geometry. The resulting patterning effect shows an anisotropic behaviour at both the pixel level and the global display level due to the multi-scale approach. Using the Area Release Energy (ARE) method an energy-based failure criterion has been utilised to analyse cohesive failure at several (critical) locations in the pixel geometry. Specifically, the sensitivity to tunnelling cracks in the dielectric layers is considered, which have been experimentally observed in comparable TFT samples that are subjected to tension. This local failure analysis allows for the identification of critical regions within the pixel geometry, which strongly depend on the location within a pixel.     

Acoustic noise and vibration analysis of solid state drive induced by multi-layer ceramic capacitors

Solid-state drives (SSDs), popular information storage devices, are typical printed circuit board assemblies (PCBA). As is true of other PCBAs, SSDs feature many multilayer ceramic capacitors (MLCCs). SSD vibration accompanied by high-pitched noise reflects the piezoelectric properties of MLCCs, and may cause great inconvenience to users. Here, we developed a finite element (FE) model predicting the vibration of the substrate associated with SSD acoustic noise. Because the SSD structure is complex and the model must be valid in the audible frequency range, we systematically constructed the model that is performed modal analysis. The excitation sources of the MLCCs were also modeled from a piezoelectric viewpoint, in which vibration analysis was performed in conjunction with the SSD model. Finally, the FE model was verified by comparing predicted and actual vibrations of an operational SSD.