Reliability of industrial packaging for microsystems

Packaging concepts for silicon-based micromachined sensors exposed to harsh environments are explored. By exposing the sensors directly to the media and applying protection at the wafer level the packaging and assembly will be simplified as compared to conventional methods of fabrication.Protective coatings of amorphous silicon carbide and tantalum oxide are suitable candidates with etch rates below 0.1 Å/h in aqueous solutions with pH 11 at temperatures up to 140°C. Si-Ta-N films exhibit etch rates around 1 Å/h. Parylene C coatings did not etch but peeled off after extended exposure times at elevated temperatures. The best diamond-like carbon films we tested did not etch, but delaminated due to local penetration of the etchants.Several glue types were investigated for chip mounting of the sensors. Hard epoxies, such as Epotek H77, on the one hand exhibit high bond strength and least degradation and leakage, but on the other hand introduce large sensor output drift with temperature changes. Softening of the Epo-tek H77 was observed at 70°C.An industrially attractive thin-film anodic silicon-to-silicon wafer bonding process was developed. Glass layers are deposited at 20 nm/s (1.2 μm/min) by electron-beam evaporation and bond strengths in excess of 25 N/mm² are obtained for bonding temperatures higher than 300°C.Through-hole electrical feedthroughs with a minimum line width of 20μm and a density of 250 wires per cm were obtained by applying electro-depositable photo-resist. Hermetically sealed feedthroughs were obtained using glass frits, which withstand pressures of 4000 bar.     

Monolithic packaging concepts for high isolation in circuits andantennas

High-frequency planar circuits experience large electromagnetic (EM) coupling in dense circuit environments. As a result, individual components exhibit performance degradation that ultimately limits overall circuit response. This paper addresses crosstalk in planar microstrip lines by evaluating micromachined packages as a means to reduce coupling. Microstrip lines with straight and meandering paths can exhibit crosstalk coupling as high as -20 dB (i.e., when placed in a side-by-side arrangement). From our study, inclusion of a monolithic package reduces this effect by as much as: -30 dB and, consequently, offers the requisite electrical and environmental protection in addition to shielding of individual elements from parasitic radiation. Presented herein is the development of the micromachined package for microstrip geometries. Included in the discussion are crosstalk effects between straight and bending geometries in open and packaged configurations and an evaluation of package noise characteristics. A packaged antenna element is also included as a demonstration of the potential use of micromachined packaging in array applications     

Reliability challenges in 3D IC packaging technology

At the moment, a major paradigm change, from 2D IC to 3D IC, is occurring in microelectronic industry. Joule heating is serious in 3D IC, and vertical interconnect is the critical element to be developed. Also reliability concerns will be extremely important. For example, in order to remove heat, a temperature gradient must exist in the packaging. If we assume just a difference of 1 °C across a micro-bump of 10 μm in diameter, the temperature gradient is 1000 °C/cm which cannot be ignored due to thermomigration. Equally challenging reliability issues are electromigration and stress-migration. Since the 3D IC structure is new, the details of reliability problems are mostly unknown. This paper presents a projection of the reliability challenges in 3D IC packaging technology on the basis of what we have known from flip chip technology.     

封装形式对电子元器件长期储存可靠性研究

长期储存是解决军用电子元器件停产断档问题的常用和重要方法之一。本文首先分析了长期储存中电子元器件的失效原因,包括静电、潮湿、温度、污染和震动,然后研究了对封装材料和环境的通用要求以及各封装形式对长期储存的特殊要求,最后比较了每种储存形式的实际寿命和优缺点。证实只要方法得当,每种储存形式均可实现大于15年以上的长期有效储存。     

Reliability assessment of delamination in chip-to-chip bonded MEMS packaging

The bond layer is often the weakest link in the reliability of chip packages in the integrated circuit (IC) industry. Micro-electrical-mechanical systems (MEMS) packages are no exception to this trend. This paper presents a nondestructive methodology for determining delamination in chip-to-chip bonded MEMS. Experimental methods are used to determine the adhesive layer strength in samples subjected to environmental testing, and the reliability of the bonding layer is investigated. A simulation is performed using inputs from scanning acoustic microscopy, and simulation model results are correlated with the experimental die shear measurements to establish the validity of the nondestructive methodology for determining adhesive layer strength.     

超薄无铅封装获得重大突破

近日,两种面向逻辑、RF应用及分立功率器件的封装在超薄无铅封装方面取得重大突破,这两种封装是由Philips Semiconductors公司推出的。其中,MicroPakII是世界上最小的无铅逻辑封装,仅1．0mm^2,焊垫间距为0．35mm。而面向分立功率器件和RF应用的Philips SOD882T封装则更小,仅为0．6mm^2,高仅0．4mm。     

Reliability analysis and design for the fine-pitch flip chip BGA packaging

The geometry of solder joints in the flip chip technologies is primarily determined by the associated solder volume and die/substrate-side pad size. In this study, the effect of these parameters on the solder joint reliability of a fine-pitched flip chip ball grid array (FCBGA) package is extensively investigated through finite element (FE) modeling and experimental testing. To facilitate thermal cycling (TC) testing, a simplified FCBGA test vehicle with a very high pin counts (i.e., 2499 FC solder joints) is designed and fabricated. By the vehicle, three different structural designs of flip chip solder joints, each of which consists of a different combination of these design parameters, are involved in the investigation. Furthermore, the associated FE models are constructed based on the predicted geometry of solder joints using a force-balanced analytical approach. By way of the predicted solder joint geometry, a simple design rule is created for readily and qualitatively assessing the reliability performance of solder joints during the initial design stage. The validity of the FE modeling is extensively demonstrated through typical accelerated thermal cycling (ATC) testing. To facilitate the testing, a daisy chain circuit is designed, and fabricated in the package for electrical resistance measurement. Finally, based on the validated FE modeling, parametric design of solder joint reliability is performed associated with a variety of die-side pad sizes. The results show that both the die/substrate-side pad size and underfill do play a significant role in solder joint reliability. The derived results demonstrate the applicability and validity of the proposed simple design rule. It is more surprising to find that the effect of the contact angle in flip chip solder joint reliability is less significant as compared to that of the standoff height when the underfill is included in the package.     

跨世纪的微电子封装

介绍了近几年国际微电子封装的特点和发展趋势 ,简述了我国微电子封装的现状和发展特点 ,并提出几点建议。     

Multichip packaging and the need for new materials

The sole determiner of speed, of cost, and of possible system size is the interconnection density of the circuits. The best way to increase the interconnection density is to reduce the dielectric constant, and there are new materials that offer almost a 2:1 reduction. Designing new modules with these low dielectric constant materials and with larger chips increases the wattage and increases the wattage density. Ceramic substrates must be used to dissipate the heat of the new large higher wattage chips without destroying them. This requires the use of new ceramic materials. A choice must be made between the leading contenders. A new multichip module technology is being defined, and will result in a major packaging change. The processes and the materials choices are presently overwhelming, but there are great advantages to those who identify the best solutions.     

一种新型给药微结构的封装技术研究

介绍了MEMS器件封装技术发展的历史、作用及现状;概要阐述了本课题组研究的可体内降解的高分子材料新型给药微结构;最后,针对这种高分子材料给药微器件自身的特点,提出了一种新型微器件的真空热融封装技术。     

VSAT networking concepts and new applications development

The authors present some innovative very small aperture terminal (VSAT) technology that can be used to support new applications. The first of these applications explores the possibility of realizing a VSAT-based satellite wide area network (SWAN) to provide flexible interconnection between local area networks (LANs) and metropolitan area networks (MANs) as well as gateway access to centralized information databases and computing services. A second application deals with the potential provision of ISDN-compatible services via VSATs in conjunction with existing satellites as well as future advanced satellites (ADSATs) having onboard switching and processing capabilities. The use of VSATs to solve backhaul interconnection/internetworking problems associated with evolving mobile satellite (MSAT) communication networks is discussed     

Reliability evaluation of BOAC and normal pad stacked-chip packaging using low-K wafers

This work evaluates the wire bondability and the reliability tests for the stacked-chip TFBGA wire bond packaging with the Sn–4.0Ag–0.5Cu lead-free solder ball. The bonding-over-active-circuit (BOAC) pad is the top test chip and the normal pad is the bottom test chip and is combined in the stacked-chip packaging. Both test chips are 90 nm low-K dielectric with five copper layers and one layer aluminum pad and a background ranging from 775 μm to 150 μm. According to the simulation results, the maximum normal stress of low-K layer for the BOAC pad is higher than that of the normal pad by 146.4%. However, the maximum shear stress of Cu metal layer for the BOAC pad is lower than that of the normal pad by 64.2%. To compare the bonding pad strength for the BOAC and normal pad low-K wafers, this work uses the simplified two-layer model to extract the effective mechanical properties of the two bonding pad structures. The effective average Young’s modulus of the normal pad and the BOAC pad are 86 GPa and 69 GPa, respectively. The test results indicate that the effective Young’s modulus of the normal pad exceeds that of the BOAC pad by 17 GPa. The wire bondability test of the ball shear and the wire pull test results are superior to the specification by 80% and 83.75%, respectively. All stacked-chip TFBGA packaging samples underwent reliability tests, including HAST, TCT, and HTST. All the wire bondability and reliability tests passed the specification for the BOAC pad and the normal pad low-K structures. Accordingly, this work shows that the proposed stacked-chip TFBGA packaging passes the wire bondability and the reliability tests. The proposed packaging improves the electrical performance, enhances the utility of the active chip area and saves chip area through the use of low-K and BOAC chips. Furthermore, the results show that the equivalent stiffness of the bonding pad structure can be used as the bondability and reliability test index for the chip.     

Quasi hermetic packaging for new generation of spaceborn microwave equipment

This paper presents the introduction of the quasi hermetic encapsulation of microwave hybrids for space application through different approaches evaluated at Thales Alenia Space – France. Thanks to the improvement for many years of microwave organic materials, it is now realistic to propose advanced packaging solutions like the chip on board approach with glob top encapsulation of active devices directly bonded on printed circuit boards for space applications. To validate this packaging approach, very significant reliability test-plans have been proposed and performed on the different technological processes and materials in agreement with standard space quality requirements. Results will be presented and a discussion on the nature of the stresses applied during the tests will be proposed.     

军用红外成像系统新概念新体制的发展

近年来,新的军事需求对军用红外成像系统提出了持久性监视、大范围覆盖、对目标区高分辨率成像、快速检测出目标事件等多项挑战,为了满足这些要求,军用红外成像系统的新概念、新体制研究成为热点.重点介绍了近年来在军用红外成像系统的新概念、新体制研究方面的新进展,并概述了压缩感知理论在新概念红外成像系统领域的应用情况,及用于新概念红外成像系统的微光机电系统和智能化红外焦平面阵列的发展.     

A new driver circuit for chip-to-chip signal transmission in Josephson packaging

A new driver circuit is developed for chip-to-chip logic signal transmission in Josephson computers. Multiple reflection noises between driver and connector impedance discontinuities may cause false logic operations in the driver and receiver circuits. Based on this factor, the driver is designed to match the impedance between the driver and transmission line in order to reduce multiple reflections. Since the noises due to the first reflections remain in this driver system, its use is limited to special cases. When used in these cases, however, the driver provides a shorter transmission path delay than Klein's driver. Experimentation shows that the driver has perfect impedance matching effects within a wide bias current margin (±26 percent).     

High density packaging technology ultra thin package & new tab package

As electronic devices become more highly integrated, the demand for small, high pin count packages has been increasing. We have developed two new types of IC packages in response to this demand. One is an ultra thin small outline package (TSOP) which has been reduced in size from the standard SOP and the other, which uses Tape Automated Bonding (TAB) technology, is a super thin, high pin count TAB in cap (T.I.C.) package. In this paper, we present these packages and their features along with the technologies used to improve package reliability and TAB. Thin packages are vulnerable to high humidity exposure, especially after heat shock.1 The following items were therefore investigated in order to improve humidity resistance: (1) The molding compound thermal stress, (2) Water absorption into the molding compound and its effect on package cracking during solder dipping, (3) Chip attach pad area and its affect on package cracking, (4) Adhesion between molding resin and chip attach pad and its affect on humidity resistance. With the improvements made as a result of these investigations, the reliability of the new thin packages is similar to that of the standard thicker plastic packages.     

Reliability of new semiconductor devices for long-distance opticalsubmarine-cable systems

Results from reliability tests conducted on three types of semiconductor devices used in optical repeaters are reported. The devices tested are: two types of 1.3-μm-band InGaAsP/InP laser diodes: a Ge avalanche photodiode; and monolithic integrated circuits. The devices have proved to be suitable for use in a long-distance optical submarine-cable system, such as the third transpacific cable system     

Chip-scale packaging

Uniting the advantages of bare die and mainstream packaging, these minimal IC supports are racing to the aid of portable yet powerful products. Rigorously defined, the perimeter of such a package is no more than 1.2 times the perimeter of the die it contains, so that few other IC packages are any smaller. This reduction in size is the key driver of the popularity of the approach. But because the term chip-scale has a marketing value, some manufacturers have extended it to cover other sizes, too. Chip-scale packaging technology is still taking its first steps into the marketplace, and issues of standards, design, and reliability remain to be solved. Even so, an infrastructure for the technology is beginning to develop, and its potential market seems to be guaranteed, not least by consumer thirst for portable electronic applications, for which the small, light package is a natural