Evolution of a unique flip-chip MCM-L package

Flip-chip (FC) packaging is gaining acceptance in the electronics packaging arena. More sources of bumped die and high density printed wiring boards (PWBs) laminates become available every day. Also, known good die (KGD) issues are being resolved by several companies, and design tools to perform FC packaging designs are becoming more available. This is the infrastructure FC packaging requires to become the packaging method of choice, particularly for >200 I/O applications. FC packages come in a variety of styles: FC plastic ball grid arrays (FC/PBGAs), FC plastic quad flat packs (PC/PQFPs), etc. Presently, the industry's drive is toward single chip packages on low cost laminates; i.e., organic substrates. Work is starting to occur in the area of multichip FC packages, due to the need to increase memory to microprocessor speed communication. In this article, a unique FC/MCM-L package is discussed. Part I will concentrate on the development and reliability testing of a one to four chip leadless FC/MCM-L package. Unlike traditional surface mount (SM) components that are attached to printed wiring boards (PWBs) with leads, the SM pads within the body of the package are used for attachment to a PWB. Collapsible eutectic solder domes are deposited on the SM pads by traditional screen printing. After reflow, these domes are used to connect the FC/MCM-L to the PWB. Challenges encountered during package design, PWB fabrication and first and second level assembly will be discussed. Part II of this article will focus on the extension of this FC/MCM-L package to a BGA second level interconnect. Change of FC attachment method, design enhancements, assembly, and reliability testing results will be presented     

Highly reliable non-conductive adhesives for flip chip CSP applications

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.     

An overview of solder bump shape prediction algorithms withvalidations

The trend to reduce the size of electronic packages and develop increasingly sophisticated electronic devices with more, higher density inputs/outputs (I/Os), leads to the use of area array packages using chip scale packaging (CSP), flip chip (FC), and wafer level packaging (WLP) technologies. Greater attention has been paid to the reliability of solder joints and the assembly yield of the surface mounting process as use of advanced electronic packaging technologies has increased. The solder joint reliability has been observed to be highly dependent on solder joint geometry as well as solder material properties, such that predicting solder reflow shape became a critical issue for the electronic research community. In general, the truncated sphere method, the analytical solution and the energy-based algorithm are the three major methods for solder reflow geometry prediction. This research develops solder joint reliability design guidelines to accurately predict both the solder bump geometry and the standoff height for reflow soldered joints in area array packages. Three simulation methods such as truncated-sphere theory force-balanced analytical solution and energy-based approach for prediction of the solder bump geometry are each examined in detail, and the thermal enhanced BGA (TBGA) and flip chip packages are selected as the benchmark models to compare the simulation and experimental results. The simulation results indicate that all three methods can accurately predict the solder reflow shape in an accurate range     

倒装片封装与芯片规模封装的综合比较及其发展前景

本文主要论述了现代微电子封装技术中倒装片封装技术和芯片规模封装技术的结构类型,应用产品,倒装片与晶片级规模封装,并阐述了倒装片封装与芯片规模封装的综合比较及其发展前景。     

Chip scale package issues

Availability of board solder joint reliability information is critical to the wider implementation of chip scale packages (CSPs). The JPL-led CSP consortia of enterprises representing government agencies and private companies have joined together to pool in-kind resources for developing the quality and reliability of CSPs for variety of projects. In the process of building the consortia test vehicles, many challenges were identified regarding various aspects of technology implementation. This paper will present our experience in the areas of technology implementation challenges, including design and building both standard and microvia boards, and assembly of two types of CSP test vehicles.     

Ultra CSPTM-a wafer level package

There has been a significant amount of work over the past five years on chip scale packaging. The majority of this work has been an extension of conventional integrated circuit (IC) packaging technology utilizing either wire bonders or tape automated bonding (TAB)-type packaging technology. Handling discrete devices during the IC packaging for these type of chip scale packages (CSPs) has resulted in a relatively high cost for these packages. This paper reports a true wafer level packaging (WLP) technology called the Ultra CSP^TM. One advantage of this WLP concept is that it uses standard IC processing technology for the majority of the package manufacturing. This makes the Ultra CSP ideal for both insertion at the end of the wafer fab as well as the facilitation of wafer level test and burn-in options. This is especially true for dynamic random access memory (DRAM) wafers. Wafer level burn-in and wafer level processing can be used for DRAM and other devices as a way to both reduce cost and improve cycle time. Thermal cycling results for Ultra CSPs with a variety of package sizes and input/output (I/O) counts are presented. These test vehicles, assembled to FR-4 boards without underfill, cover a range of footprints typical of flash memory, DRAM and other devices. The electrical and thermal performance characteristics of the Ultra CSP package technology are discussed     

Reliability evaluation of ultra-thin CSP using new flip-chip bonding technology––double-sided CSP and single-sided CSP

A high-density packaging technology has been developed that uses new flip-chip bonding technology with a thin IC and a thin substrate. Numerical analysis with the finite element method as well experiments clearly showed that deflection of the IC and reliability were affected by the IC thickness. Consequently, reliability could be improved by reducing IC thickness. The dependency of the life in single-sided chip-size packages (CSPs) could be expressed using a normal stress value in thickness, which is computed by the IC thickness and substrate type and thickness. The dependency of the life in double-sided CSPs could be expressed using a shear stress value in the vertical cross section, which is computed in IC thickness and substrate type and thickness, respectively.Moreover, a double-sided flip-chip approach solved the problem of warpage. A high-capacity memory card of 512 MB was put to practical use by applying these results. This increased the Si density by four times over that of a conventional CSP.     

PCB检查的声学工具及其应用

随着电子封装技术不断朝着微型化的发展,在检查倒装芯片封装和芯片规模封装中,声学微成像技术得到了极大的应用.利用扫描探测器把超声波用脉冲输入倒装芯片或别的封装,超声波在封装中向下穿透,直至遇到两种不同材料之间的界面为止.     

Recent advances in plastic packaging of flip-chip and multichipmodules (MCM) of microelectronics

The success in consumer electronics in the 1990's will be focused on low-cost and high performance electronics. Recent advances in polymeric materials (plastics) and integrated circuit (IC) encapsulants have made high-reliability very-large-scale integration (VLSI) plastic packaging a reality. High-performance polymeric materials possess excellent electrical and physical properties for IC protection. With their intrinsic low modulus and soft gel-like nature, silicone gels have become very effective encapsulants for larger, high input/output (I/O) (in excess of 10 000), wire-bonded and flip-chip VLSI chips. Furthermore, the recently developed silica-filled epoxies underfills, with the well controlled thermal coefficient of expansion (TCE), have enhanced the flip-chip and chip-on-board, direct chip attach (DCA) encapsulations. Recent studies indicate that adequate IC chip surface protection with high-performance silicone gels and epoxies plastic packages could replace conventional ceramic hermetic packages. This paper will review the IC technological trends, and IC encapsulation materials and processes. Special focus will be placed on the high-performance silicone and epoxy underfills, their chemistries and use as VLSI device encapsulants for single and multichip module applications     

Effect of the drop impact on BGA/CSP package reliability

In this study, ball grid arrays (BGAs) and chip size packages (CSPs) were evaluated with respect to their solder joint reliabilities under drop impacts. The correlation between solder joint stresses and motherboard strains was confirmed by numerical analysis, and the motherboard strains caused by the drop impacts were measured to evaluate the BGA/CSP reliability. The authors found that the stress at a solder joint differs depending on the package structure, even if the motherboard strain is the same, and that underfilling eases the motherboard strain and disperses the stress concentrated on a solder joint.     

Overdriving reliability of chip scale packaged LEDs: Quantitatively analyzing the impact of component

The objective of this study is to quantitatively evaluate the impacts of LED components on the overdriving reliability of high power white LED chip scale packages (CSPs). The reliability tests under room temperature are conducted over 1000 h in this study on CSP LEDs with overdriving currents. A novel method is proposed to investigate the impact of various components, including blue die, phosphor layer, and substrate, on the lumen depreciation of CSP LEDs after aging test. The electro-optical measurement results show that the overdriving current can lead to both massive light output degradation and significant color shift of CSP LEDs. The quantitative analysis results show that the phosphor layer is the major contributor to the failure in early period aging test. For the long-term reliability, the degradations of phosphor and reflectivity of substrate contribute significantly on lumen depreciation. The proposed reliability assessment method with overdriving loadings can be usefully implemented for LED manufacturers to make a cost- and effective-decision before mass production.     

Board level reliability assessment of chip scale packages

A large program had been initiated to study the board level reliability of various types of chip scale package (CSP). The results on six different packages are reported here, which cover flex interposer CSP, rigid interposer CSP, wafer level assembly CSP, and lead frame CSP. The packages were assembled on FR4 PCBs of two different thicknesses. Temperature cycling tests from −40°C to +125°C with 15 min dwell time at the extremes were conducted to failure for all the package types. The failure criteria were established based on the pattern of electrical resistance change. The cycles to failure were analyzed using Weibull distribution function for each type of package. Selected packages were tested in the temperature/humidity chamber under 85°C/85%RH for 1000 h. Some assembled packages were tested in vibration condition as well. In all these tests, the electrical resistance of each package under testing was monitored continuously. Test samples were also cross-sectioned and analyzed under a Scanning Electronic Microscope (SEM). Different failure mechanisms were identified for various packages. It was noted that some packages failed at the solder joints while others failed inside the package, which was packaging design and process related.     

Board-level reliability of Pb-free solder joints of TSOP and various CSPs

To evaluate various Pb-free solder systems for leaded package, thin small outline packages (TSOPs) and chip scale packages (CSPs) including leadframe CSP (LFCSP), fine pitch BGA (FBGA), and wafer level CSP (WLCSP) were characterized in terms of board level and mechanical solder joint reliability. For board level solder joint reliability test of TSOPs, daisy chain samples having pure-Sn were prepared and placed on daisy chain printed circuit board (PCB) with Pb-free solder pastes. For CSPs, the same composition of Pb-free solder balls and solder pastes were used for assembly of daisy chain PCB. The samples were subjected to temperature cycle (T/C) tests (-65/spl deg/C/spl sim/150/spl deg/C, -55/spl deg/C/spl sim/125/spl deg/C, 2 cycles/h). Solder joint lifetime was electrically monitored by resistance measurement and the metallurgical characteristics of solder joint were analyzed by microstructural observation on a cross-section sample. In addition, mechanical tests including shock test, variable frequency vibration test, and four point twisting test were carried out with daisy chain packages too. In order to compare the effect of Pb-free solders with those of Sn-Pb solder, Sn-Pb solder balls and solder paste were included. According to this paper, most Pb-free solder systems were compatible with the conventional Sn-Pb solder with respect to board level and mechanical solder joint reliability. For application of Pb-free solder to WLCSP, Cu diffusion barrier layer is required to block the excessive Cu diffusion, which induced Cu trace failure.     

Comprehensive treatment of moisture induced failure-recent advances

This paper describes a comprehensive treatment of moisture induced failure in integrated circuit (IC) packaging with emphasis on recent advances. This includes advanced technique for modeling moisture diffusion under dynamic boundary conditions such as experienced by packages during solder reflow, autoclave, and temperature-humidity cycling; advanced characterization technique for moisture sorption and diffusion properties of packaging materials including effect of edge diffusion on transverse diffusivity, anisotropic diffusivity in organic laminates, impact of non-Fickian sorption; advanced techniques for modeling vapor pressure during solder reflow; advanced techniques for modeling dynamic delamination propagation during solder reflow; interfacial fracture strength as a function of temperature and moisture; as well as plastic analysis of popcorn cracking.     

Novel reworkable fluxing underfill for board-level assembly

Underfills are traditionally applied for flip-chip applications. Recently, there has been increasing use of underfill for board-level assembly including ball grid arrays (BGAs) and chip scale packages (CSPs) to enhance reliability in harsh environments and impact resistance to mechanical shocks. The no-flow underfill process eliminates the need for capillary flow and combines fluxing and underfilling into one process step, which simplifies the assembly of underfilled BGAs and CSPs for SMT applications. However, the lack of reworkability decreases the final yield of assembled systems. In this paper, no-flow underfill formulations are developed to provide fluxing capability, reworkability, high impact resistance, and good reliability for the board-level components. The designed underfill materials are characterized with the differential scanning calorimeter (DSC), the thermal mechanical analyzer (TMA), and the dynamic mechanical analyzer (DMA). The potential reworkability of the underfills is evaluated using the die shear test at elevated temperatures. The 3-point bending test and the DMA frequency sweep indicate that the developed materials have high fracture toughness and good damping properties. CSP components are assembled on the board using developed underfill. High interconnect yield is achieved. Reworkability of the underfills is demonstrated. The reliability of the components is evaluated in air-to-air thermal shock (AATS). The developed formulations have potentially high reliability for board-level components.     

Drop impact reliability of edge-bonded lead-free chip scale packages

This paper presents the drop test reliability results for edge-bonded 0.5 mm pitch lead-free chip scale packages (CSPs) on a standard JEDEC drop reliability test board. The test boards were subjected to drop tests at several impact pulses, including a peak acceleration of 900 Gs with a pulse duration of 0.7 ms, a peak acceleration of 1500 Gs with a pulse duration of 0.5 ms, and a peak acceleration of 2900 Gs with a pulse duration of 0.3 ms. A high-speed dynamic resistance measurement system was used to monitor the failure of the solder joints. Two edge-bond materials used in this study were a UV-cured acrylic and a thermal-cured epoxy material. Tests were conducted on CSPs with edge-bond materials and CSPs without edge bonding. Statistics of the number of drops-to-failure for the 15 component locations on each test board are reported. The test results show that the drop test performance of edge-bonded CSPs is five to eight times better than the CSPs without edge bonding. Failure analysis was performed using dye-penetrant and scanning electron microscopy (SEM) methods. The most common failure mode observed is pad lift causing trace breakage. Solder crack and pad lift failure locations are characterized with the dye-penetrant method and optical microscopy.     

Wafer level packaging of a tape flip-chip chip scale packages

The advent of chip scale packages (CSPs) within the semiconductor community has led to the development of wafer scale assembly (WSA) or wafer level packaging (WLP) manufacturing in order to raise assembly efficiencies and lower operating costs. Texas Instruments (TI) has developed a unique WLP process for forming flip-chip, ball grid array packages. The die inputs and outputs of the TI CSP are connected through solder bumps to a polyimide film interposer. Solder balls on the other side of the interposer complete the electrical connection to a customer’s printed circuit board. A wafer-sized array of interposers designed to match the pattern of dies on a wafer is aligned and reflowed to a bumped wafer. The TI WLP process is completed by singulating the CSPs from the wafer using standard wafer saw equipment.Attachment of the interposer to the die as well as applying the die and board level solder bumps are carried out in wafer form using a new bumping technology called Tacky Dots™. Tacky Dots uses an array of sticky dots formed in a photosensitive coating laminated to a polyimide film for transferring and attaching solder spheres to semiconductor substrates. A populated film containing one solder sphere per Tacky Dot is positioned over the wafer or interposer and lowered until the spheres contact the pads. A reflow process transfers the spheres from the film to the wafer or interposer and the film is removed once the spheres have frozen.This paper illustrates the process steps and custom equipment developed for forming the TI CSP. The strategic use of finite element modeling for optimizing the design of the package is outlined. The paper concludes by summarizing the current package level reliability results.     

Escape routing design to reduce the number of layers in area array packaging

High density multilayer substrate technologies are indispensable to accommodate high input/outputs (I/Os) fine pitch area array integrated circuits (ICs), chip scale packages/ball grid arrays (CSP/BGAs) in the coming packaging generation. They must provide not only a high wiring density, but also an acceptable low cost, short turn around time (TAT) and reliability. Reduction of the number of layers is expected to be a reasonable solution for the conflicting demands. General approaches to reduce the layer count have been to decrease the size of the routing line width and spacing. However, they need changes in the manufacturing processes and materials, causing an increased cost. From escape routing design viewpoint, effects of routing manner on the layer count have been studied. A preferential routing creates specific pad geometry resulting in a high wiring efficiency. This effect can be estimated with an increase in the number of lines per layer routable as a contribution of "the hybrid channel," depending on capture pad pitch-pad diameter-line width-interline space relationship. It is one of the remarkable cases recognized that, within one line per channel rule, the preferential routing can be almost equivalent to that by two lines per channel with regard to the wireability. Its better effect on cost and TAT can also be expected compared with the two thinner sized lines per channel rule, since nothing changes in both manufacturing processes and materials is needed. This method is applicable immediately to packages and boards for assembly of the high I/O flip chips, CSPs, and BGAs.     

Reliability studies and design improvement of mirror image CSP assembly

In this paper, both simulation and testing techniques were used to address the reliability issue of mirror chip scale package (CSP) assembly. First, finite element modeling was employed to study the stress and strain of a mirror image CSP with comparison to a single-sided CSP. The study clearly illustrates that the strain distribution is not equally distributed across both sides of the CSP. The highest strain on one side of the mirror image CSP is often larger than the other one, which reduced the reliability of the package as a whole. In order to study the effects on the reliability of the mirror image CSP assembly, several parameters, such as PCB board materials selection, board thickness and warpage, PCB via design and routing, were investigated. Moreover, a design of experiment matrix was constructed to identify significant factors to minimize the highest strain in solder joints of mirror image. The test vehicle was then designed and assembled. Thermal cycling (0 to 100 °C) and thermal shock tests were thereafter performed to the mirror image CSPs and single-sided CSPs to compare with the simulation results.     

Reliability test and failure analysis of high power LED packages

A new type application specific light emitting diode(LED) package(ASLP) with freeform polycarbonate lens for street lighting is developed,whose manufacturing processes are compatible with a typical LED packaging process.The reliability test methods and failure criterions from different vendors are reviewed and compared.It is found that test methods and failure criterions are quite different.The rapid reliability assessment standards are urgently needed for the LED industry.85℃/85 RH with 700 mA is used to test our LED modules with three other vendors for 1000 h,showing no visible degradation in optical performance for our modules,with two other vendors showing significant degradation.Some failure analysis methods such as C-SAM,Nano X-ray CT and optical microscope are used for LED packages.Some failure mechanisms such as delaminations and cracks are detected in the LED packages after the accelerated reliability testing.The finite element simulation method is helpful for the failure analysis and design of the reliability of the LED packaging.One example is used to show one currently used module in industry is vulnerable and may not easily pass the harsh thermal cycle testing.