Electrooptic sampling of a packaged high-speed GaAs integratedcircuit

The authors describe the use of electrooptic sampling to characterize the performance of a packaged 1.7-GHz GaAs planar integrated decision circuit. To study the packaged device, it was necessary for the optical probe beam to impinge on the circuit from the front (active) side. This geometry enabled effective evaluation of the circuit, in spite of reduced spatial resolution and voltage sensitivity compared to a backside probing geometry. Using a gain-switched InGaAsP laser source, waveforms have been measured in the D flip-flop within the circuit and propagation delays of about 25 ps in the input buffers. Apparent crosstalk has been measured when the probe is positioned between adjacent active circuit lines and it is found that this crosstalk depends sensitively on the position of the probe beam     

Quantitative measurement with high time resolution of internal waveforms on MOS RAMs using a modified scanning electron microscope

The growing packing density of integrated circuits calls, to an increasing extent, for the testing of the functioning of the individual circuits of ICs. If a mechanical prober is used for this purpose, the resulting capacitive loading of the circuit is liable to alter its performance. It is shown in the present work that the electron beam represents an ideal nonloading and nondestructive probe which can be finely focused and positioned on measuring points within the circuit under test. A modified scanning electron microscope allows the recording of waveforms within a circuit with a voltage resolution of the order of 10-100 mV and a time resolution of less than 1 ns. The efficiency of the technique was demonstrated by measuring the internally derived clock pulses and the voltage distributions of a digit-line of a 4096-bit MOS RAM and comparing the results with computer simulations.     

A Packaging Solution for Optically Testing Wire-Bonded Chips

In this paper, we describe the design and the experimental characterization of a packaging technique for backside optical testing of chips requiring wirebonding. Optical testing methods, based either on the collection of spontaneous hot-carrier photoemission or on laser stimulation, require an optical access to the active area of the circuit through the backside of the chip, while still providing mechanical support to the thinned die (very fragile), heat sinking capability, power and electrical signals. The proposed package fulfils all these requirements and it can hence be used for picosecond imaging for circuit analysis/time resolved emission measurements, emission microscopy investigations, laser voltage probe, thermal laser stimulation, photoelectric laser stimulation, and other failure analysis methods that require optical access to the transistor level through the silicon backside. The advantages of the new package are its versatility (it can fit different chip sizes), easy handling, low cost, and the fact that it is designed for optical testing and not just for electrical testing. We successfully used the proposed package for optically test chips in advanced complementary metal–oxide–semiconductor technologies (65 nm): measurements at low voltage are possible thanks to the proposed package.      

Wafer level backside emission microscopy: sample preparation

Emission microscopy has been widely adopted as an important tool for analyzing integrated circuit failures from the front surface. More recently, the development of multi-level metallization, flip-chip and lead-on-chip package designs either eliminated or greatly restricted this inspection avenue. An obvious alternative is to inspect from the backside of semiconductors. However, as silicon itself is a light-blocking material, thinning the back surface becomes essential to successful backside emission microscopy (EM). This paper describes a thinning and polishing technique enabling a user to locally thin a defective die on a wafer. This local thinning and polishing allows the wafer to retain its overall mechanical strength to survive the subsequent microprobing while providing a viewing window for EM analysis through the backside.     

Imaging the Electric Potential within Organic Solar Cells

The charge transport in organic solar cells is investigated by surface potential measurements via scanning Kelvin probe microscopy. Access to the solar cell's cross‐section is gained by milling holes with a focused ion beam which enables the direct scan along the charge transport path. In a study of poly(3‐hexylthiophene):1‐(3‐methoxycarbonyl)propyl‐1‐phenyl[6,6]C61 (P3HT:PCBM) bulk heterojunction solar cells, the open circuit voltage is built up at the top contact. A comparison of the potential distribution within normal and inverted solar cells under operation exhibits strongly different behaviors, which can be assigned to a difference in interface properties.     

A review of ULSI failure analysis techniques for DRAMs. Part II: Defect isolation and visualization

In this paper the basic techniques for defect isolation and visualization used in physical failure analysis of trench technique dynamic random access memories (DRAMs) are reviewed. The methods described are state-of-the-art for DRAM failure analysis down to 0.14 μm feature size and beyond. In addition to defect isolation and defect visualization from the front side of a die, the backside preparation approach is reviewed. Beginning with basic sample preparation techniques including mechanical polishing, wet and dry etching and focused ion beam (FIB) applications advantages and disadvantages of various techniques are discussed. In the second section of the paper different types of optical microscopes are covered as well as scanning and transmission electron microscopes. The imaging capabilities of the FIB systems are included in this section. Finally, some applications of scanning probe techniques especially for dopant measurements and thin oxide characterization are described.     

Sampling electrostatic force probing using pulse positionmodulation technique

A sampling electrostatic force microscopy method utilising a pulse position modulation technique is demonstrated. High frequency arbitrary waveforms within integrated circuits are measured by down converting the high frequency spectrum of the circuit waveform to within the active frequency band of the mechanical frequency response of the probe     

Local thermal probing to detect open and shorted IC interconnections

A new failure analysis technique has been developed for backside and frontside localization of open and shorted interconnections on ICs. This scanning optical microscopy technique takes advantage of the interactions between IC defects and localized heating using a focused infrared laser (λ=1340 nm). Images are produced by monitoring the voltage changes across a constant current supply used to power the IC as the laser beam is scanned across the sample. The method utilizes the Seebeck Effect to localize open interconnections and Thermally-Induced Voltage Alteration to detect shorts. The interaction physics describing the signal generation process and several examples demonstrating the localization of opens and shorts are described. Operational guidelines and limitations are also discussed.     

Global fault localization using induced voltage alteration

Advances in integrated circuit technology have made failure site localization extremely challenging. Charge-induced voltage alteration (CIVA), low energy CIVA (LECIVA), light-induced voltage alteration (LIVA), Seebeck effect imaging (SEI) and thermally-induced voltage alteration (TIVA) are five recently developed failure analysis techniques which meet the challenge by rapidly and non-destructively localizing interconnection defects on ICs. The techniques take advantage of voltage fluctuations in a constant current power supply as an electron or photon beam is scanned across an IC. CIVA and LECIVA are scanning electron microscopy techniques that yield rapid localization of open interconnections. LIVA is a scanning optical microscopy (SOM) method that yields quick identification of damaged semiconductor junctions and determines transistor logic states. SEI and TIVA are SOM techniques that rapidly localize open interconnections and shorts respectively. LIVA, SEI, and TIVA can be performed from the backside of ICs by using the proper photon wavelength. This paper describes the CIVA, LECIVA, LIVA, TIVA, and SEI techniques in terms of the physics of signal generation, general data acquisition system required, and imaging results displaying the utility of each technique for localizing interconnection defects.     

Preparation of defined structures on very thin foils for characterization of AFM probes

In atomic force microscopy (AFM), knowledge of the probe (tip) geometry is a critical factor for obtaining reproducible images. This is particularly important for measurements in the contact mode, in which a certain amount of wear of the probe always occurs affecting the image quality of small, flat and/or larger surface structures. In addition to probe geometry, the slope of the probe with respect to the sample is of importance. In this work, probe geometry is determined by the use of structured foils obtained using focused ion beam (FIB). In this manner, we demonstrate the possibility of determining the AFM probe geometry and the slope on the basis of differently-sized structures. An established algorithm was implemented for the reconstruction of the probes. The shape of FIB structured foils was determined separately by scanning electron microscopy (SEM).     

Observation of the internal waveforms in high-speed high-density LSIs using an EOS prober

Electron beam (EB) probing has been used to observe the internal waveforms in ULSLs. However, as the speed of LSIs increases and their power consumption decreases, the temporal and voltage resolution of EB probing is going to be inadequate for measuring these waveforms. Electro-optic sampling (EOS) probing is expected to overcome this limitation, provided its spatial resolution can be improved. In this paper, forming a via on the interconnection under test is proposed for practically improving spatial resolution. The effectiveness of this method and the dependence of the detected signal level on testing pad area are clarified by simulation. To verify these results, vias are formed in ECL SRAMs by focused ion beam trimming, and waveforms with frequency as high as 100 MHz and swing as small as 30 mV are successfully observed. Using this technique, the dependence of the detected signal level on testing pad area is verified, and it is confirmed that the amplitude change below 10 mV and the delay time below 100 ps can be measured. With the improved spatial resolution, EOS probing enables us to observe high-frequency and small-swing waveforms even in high-density fine interconnections. In future, this technology will be crucial for observing internal waveforms in LSIs.     

Time-resolved optical characterization of electrical activity in integrated circuits

If the rate of improvement in the performance of advanced silicon integrated circuits is to be sustained, new techniques for the measurement of electrical waveforms in operating circuits are needed. Critical factors dictating this requirement include the increased speed and complexity of circuits, the growing importance of faults that appear only during high-speed operation, and the use of flip-chip packaging technologies. Two recently developed all-optical methods for measuring the switching activity from the backside of a chip are described and compared. One is a passive approach based on the measurement of hot carrier luminescence emitted from the channel of a CMOS field-effect transistor (FET) during switching. The second uses a laser probe to sense the switching induced modulation of the silicon optical constants near an FET's source and drain.     

Flip-Chip Bonding of MEMS Scanner for Laser Display Using Electroplated AuSn Solder Bump

A MEMS scanner has been flip-chip bonded by using electroplated AuSn solder bumps. The microelectromechanical systems (MEMS) scanner is mainly composed of two structures having vertical comb fingers. To optimize the bonding condition, the MEMS scanner was flip-chip bonded with various bonding temperatures. Scanning electron microscopy (SEM) with an energy dispersive X-ray (EDX) spectroscopic system was used to observe the microstructures of the joints and analyze the element compositions of them. The die shear strength increased as the bonding temperature increased. During the thermal aging test, the delamination occurred at the interconnection of the MEMS scanner bonded at 340 degC. It is inferred that the Au layer serving as pad metallization has been dissolved in the molten AuSn solder totally, and subsequently the Cr layer was directly exposed to the AuSn solder. Judging by the results of both die shear test and thermal aging test, the optimal bonding temperature was found to be approximately 320 degC. Finally, using this MEMS scanner, we obtained an optical scanning angle of 32deg when driven by the ac control voltage of the resonant frequency in the range of 22.1-24.5 kHz with the 100-V dc bias voltages     

SiC晶圆背面激光退火工艺研究

降低芯片背面金属-半导体欧姆接触电阻是有效提高器件性能的方式之一。采用650 V SiC肖特基势垒二极管(SBD)工艺,使用波长355 nm不同能量的脉冲激光进行退火实验,利用X射线衍射(XRD)和探针台对晶圆背面镍硅合金进行测量分析,得出最佳能量为3.6 J/cm²。退火后采用扫描电子显微镜(SEM)观察晶圆背面碳团簇,针对背面的碳团簇问题,在Ar;气氛下对晶圆进行了表面处理,使用SEM和探针台分别对两组样品的表面形貌和电压-电流特性进行了对比分析。实验结果表明,通过表面处理可以有效降低表面的碳含量,并且使器件正向压降均值降低了6%,利用圆形传输线模型(CTLM)测得芯片的比导通电阻为9.7×10^-6Ω·cm²。器件性能和均匀性都得到提高。     

聚焦离子束在光纤探针制备技术中的应用

本文概述了利用聚焦离子束制备用于近场光学显微镜光纤探针的方法,讨论了探针的锥型刻蚀、孔径控制和特殊结构加工等;论述了聚焦离子束的工作原理和在光纤探针高精度加工方面的优势。利用此技术制备的光纤探针的锥型和针尖孔径精确可控,并具有高光洁度,高通光效率等特点。     

200-mm wafer-scale transfer of 0.18-/spl mu/m dual-damascene Cu/SiO/sub 2/ interconnection system to plastic substrates

We report a low-temperature (<200/spl deg/C) 200-mm wafer-scale transfer of a 0.18-/spl mu/m dual-damascene Cu/SiO/sub 2/ interconnection system to FR-4 plastic substrates using adhesive bonding. We demonstrate removal of the silicon bulk layer to leave behind a flexible 3-/spl mu/m-thick Si back-end-of-line (BEOL) circuit on a 0.1-mm-thick FR-4 wafer. The mechanical and electrical integrity of the thin Si BEOL circuit on FR-4 are confirmed by focused ion beam scanning electron microscope microscopy and current-voltage characterization on a variety of test structures, which include serpentine, via chain and Kelvin test structures on different locations on the wafer. This process will pave the path to allow integration of high-performance submicrometer Si electronics on plastic substrates.     

邻近导体布局对电光测量的影响

采用静态有限差分法，求解了电光探测时探头内部的电场分布；发现了电光信号随布线的变化，设计了一系列不同布线的电极；采用ITO导电膜进行电光信号幅度校准并减少串扰。理论分析与实验结果符合得很好。最后，分析了ITO导电膜对CMOS反相器高频特性的影响。     

Evaluation of die edge cracking in flip-chip PBGA packages

Increasing die size and large coefficient of thermal expansion (CTE) mismatch in flip-chip plastic ball grid array (FC-PBGA) packages have made die fracture a major failure mode during reliability testing. Most die fracture observed before was die backside vertical cracking, which was caused by excessive package bending and backside defects. However, due to die edge defects induced by the singulation process and the choice of underfill material, an increasing number of die cracks were found to initiate from die edge and propagate horizontally across the die. In order to improve package reliability and performance, die edge cracking has to be eliminated. An extensive finite element analysis was completed to investigate die edge cracking and find its solutions. A fracture mechanics approach was used to evaluate the effect of various package parameters on die edge initiated fracture. Strain energy release rate was found to be an effective technique for evaluating die edge initiated fracture from singulation-induced flaws. The impact of initial flaw size and a variety of package parameters was investigated. Unlike in die backside cracking, the dominant parameters causing die edge horizontal fracture are more closely related to local effects.     

Characterization of fritting phenomena on Al electrode for low contact force probe card

We have investigated the characteristics of fritting of thin oxide film on an aluminum electrode for application to a probe card with low contact force. The fritting is a kind of electric breakdown of oxide film on metal electrode. It can be utilized for making electric contacts between the test probe and the electrode on LSI chips without a large force. The voltage and the contact force needed to cause fritting on a sputtered Al film was measured using W, BeCu and Pd needle probes. The contact resistance was also measured. A fritting was occurred by applying a contact load of 1 mN and voltage of 5 V. The contact resistance decreases with increasing the maximum current that passes through the contact. A current of 500 mA is enough to obtain the contact resistance of 1 /spl Omega/, which is low enough in practical test of signal lines. No damages were found on the Al film by optical microscope and scanning electron microscope observation.     

由版图引起的CMOS ESD保护电路失效的分析

ESD保护电路已经成为CMOS集成电路不可或缺的组成部分,在当前CMOS IC特征尺寸进入深亚微米时代后,如何避免由ESD应力导致的保护电路的击穿已经成为CMOS IC设计过程中一个棘手的问题.光发射显微镜利用了IC芯片失效点所产生的显微红外发光现象可以对失效部位进行定位,结合版图分析以及微分析技术,如扫描电子显微镜SEM、聚焦离子束FIB等的应用可以揭示ESD保护电路的失效原因及其机理.通过对两个击穿失效的CMOS功率ICESD保护电路实际案例的分析和研究,提出了改进ESD保护电路版图设计的途径.