A centroid-based PWM switching technique for full-bridge inverterapplications

A novel centroid-based pulse-width-modulation (PWM) switching strategy is proposed which is suitable for full-bridge inverter applications. This method is evaluated, and its performance is compared with existing PWM switching strategies. The performance evaluation and comparison are based on the total harmonic distortion (THD) and number of pulses per cycle of the inverter output waveform. The objective of the new switching strategy is to minimize both the THD and low-order harmonics. Simulation results show that this technique yields a significant improvement in performance. In addition, a hybrid switching sequence is developed for the proposed scheme, which can lead to further reduction in switching losses     

A higher levels multilevel inverter with reduced number of switches

This paper presents a high-levels multilevel inverter (MLI) with a reduced number of the required switches. Forty-nine levels can be obtained in the output voltage from this circuit by using only 12 semiconductor switches, while in conventional topologies of MLI, a higher number of switches is required producing a lower number of levels in the output voltage. Reduction in the number of semiconductor switches, gate drivers, DC voltage sources and increasing the number of voltage levels are advantages of the proposed MLI compared with other topologies. These advantages result in smaller size, lower loss and low installation cost. Total harmonic distortion (THD) in the output waveform of the inverter is very low, thus, using a filter to improve the output waveform is not needed. A switching pulse system has been presented to produce nearly sinusoidal waveforms. Mathematical relations and switching states of the proposed topology have been discussed. Simulation results have been obtained and studied. The prototype of the modified MLI has been built and tested in the laboratory using a dSPACE (DS1104) evaluation board in order to verify the simulation results. Several of the experimental results of the proposed topology have been included and discussed.     

A low frequency AC to high frequency AC inverter with build-in power factor correction and soft-switching

This paper presents a full bridge AC-AC inverter for high frequency power distribution system with power factor correction stage controlled by a unified controller. The proposed inverter has the following features: 1) load independent output voltage with constant frequency and very low total harmonic distortion (THD); 2) soft switching of the full bridge switches for a wide range of input voltage and load conditions; 3) low DC bus voltage; 4) simple control and cost effectiveness for the power factor correction stage. Operating principles and performance characteristics are presented, and guidance to design the converter is given. Experimental results of a 90-265V/sub ac/ input, 30 V/sub ac/ output at 100 kHz, 250 W laboratory prototype are given to verify the theoretical and simulation results. The proposed ac-ac inverter is attractive for low power (up to 250 W) high frequency applications.     

Suppression of line voltage related distortion in current controlled grid connected inverters

The influence of selected control strategies on the level of low-order current harmonic distortion generated by an inverter connected to a distorted grid is investigated through a combination of theoretical and experimental studies. A detailed theoretical analysis, based on the concept of harmonic impedance, establishes the suitability of inductor current feedback versus output current feedback with respect to inverter power quality. Experimental results, obtained from a purpose-built 500-W, three-level, half-bridge inverter with an L-C-L output filter, verify the efficacy of inductor current as the feedback variable, yielding an output current total harmonic distortion (THD) some 29% lower than that achieved using output current feedback. A feed-forward grid voltage disturbance rejection scheme is proposed as a means to further reduce the level of low-order current harmonic distortion. Results obtained from an inverter with inductor current feedback and optimized feed-forward disturbance rejection show a THD of just 3% at full-load, representing an improvement of some 53% on the same inverter with output current feedback and no feed-forward compensation. Significant improvements in THD were also achieved across the entire load range. It is concluded that the use of inductor current feedback and feed-forward voltage disturbance rejection represent cost-effect mechanisms for achieving improved output current quality.     

Four-wire dynamic voltage restorer based on a three-dimensional voltage space vector PWM algorithm

A modified voltage space vector pulse-width modulated (PWM) algorithm for a four-wire dynamic voltage restorer (DVR) is described. The switching strategy based on a three-dimensional (3-D) /spl alpha//spl beta/O voltage space is applicable to the control of three-phase four-wire inverter systems such as the split-capacitor PWM inverter and the four-leg PWM inverter. In contrast to the conventional voltage space vector PWM method, it controls positive, negative and zero sequence components of the terminal voltages instantaneously. Three 3-D modulation schemes are analyzed with respect to total harmonic distortion (THD), weighted total harmonic distortion (WTHD), neutral line ripple and switching loss over the whole range of the modulation index when the DVR experiences both balanced and unbalanced sags with phase angle jumps. Experimental results from a 9 kW DVR system using a split-capacitor PWM inverter are presented to validate the simulation results.     

基于极点配置的400Hz逆变电源系统设计

针对单相400Hz逆变电源系统的控制特点,引入输出电压瞬时值外环和电感电流内环的双环反馈控制,采用极点配置与PI控制相结合的方法对系统进行了设计,并根据状态空间理论建立了系统数学模型。仿真结果表明,该方案动态响应快、稳态精度高、THD小、带负载能力强。     

Active harmonic elimination for multilevel converters

This paper presents an active harmonic elimination method to eliminate any number of specific higher order harmonics of multilevel converters with equal or unequal dc voltages. First, resultant theory is applied to transcendental equations characterizing the harmonic content to eliminate low order harmonics and to determine switching angles for the fundamental frequency switching scheme and a unipolar switching scheme. Next, the residual higher order harmonics are computed and subtracted from the original voltage waveform to eliminate them. The simulation results show that the method can effectively eliminate the specific harmonics, and a low total harmonic distortion (THD) near sine wave is produced. An experimental 11-level H-bridge multilevel converter with a field programmable gate array controller is employed to implement the method. The experimental results show that the method does effectively eliminate any number of specific harmonics, and the output voltage waveform has low THD.     

Zero-voltage switching for three-level capacitor clamping inverter

A zero-voltage switching (ZVS) scheme for a three-level capacitor clamping inverter based on the true pulsewidth modulation (PWM) pole is proposed in this paper. With this scheme, the main switches work with ZVS through the assistance of a small rating zero current switching (ZCS) lossless auxiliary circuitry without imposing any voltage/current spikes on the main devices or any extra control complexities. Consequently, a three-level capacitor clamping inverter system can operate at a promoted switching frequency and becomes more eligible to be considered for high-power advanced applications, for example, in high-speed drives or power active filter areas. In this paper, the main circuit operation issues as regards the clamping voltage stability, damping capacitor stress, and output voltage spectrum are shortly reviewed first, after which the commutation principle, auxiliary circuitry stress analysis, and auxiliary circuitry designing methodology are presented in detail. Experimental results from a 700 V supply 3 kW half-bridge three-level capacitor clamping inverter are demonstrated which conform well to the proposal     

Design and analysis of power-CMOS-gate-based switched-capacitor boost DC-AC inverter

A multistage power CMOS-transmission-gate-based (CMOS-TG) quasi-switched-capacitor (QSC) boost DC-AC inverter is proposed and integrated with a boost DC-DC converter for a step-up application with AC or DC load. In this paper, using CMOS-TG as a bidirectional switch, the various topologies can be integrated in the same configuration for achieving two functions: boosting and alternating; boosting for getting a sinusoidal output in which the peak is the result of a many times step-up of the input; alternating to realize the positive/negative half sinusoidal of the output. The inverter does not require any inductive elements as inductor and transformer, so integrated circuit (IC) fabrication will be promising for realization. By using the state-space averaging technique, the large-signal state-space model of the inverter is proposed, and then both the static analysis and dynamic small-signal analysis are derived to form a unified formulation for inverter/converter. Based on this formulation, there are presented for theoretical analysis/control design, including steady-state power, conversion efficiency, voltage conversion ratio, output ripple percentage, capacitance selection, closed-loop control and stability, and total harmonic distortion (THD), etc. Finally, a six-stage QSC boost DC-AC inverter is simulated by PSPICE, and the simulations are discussed for some cases, including: 1) steady-state AC output, ripple percentage, and power efficiency; 2) transient response of the regulated inverter for load variation; 3) a practical capacitive load: electromagnetic luminescent (EL) lamp, and 4) efficiency, ripple percentage, and THD for different loads. The results are illustrated to show the efficacy of the proposed inverter.     

Application of sliding-mode control to the design of a buck-basedsinusoidal generator

This paper is devoted to the design of a sliding-mode control scheme for a buck-based inverter, with programmable amplitude, frequency, and DC offset, with no external sinusoidal reference required. A general procedure for obtaining an autonomous (time independent) switching surface from a time-dependent one is presented. For this surface, the system exhibits a zeroth-order dynamics in sliding motion. On the other hand, from the sliding-domain analysis, a set of design restrictions is established in terms of the inverter output filter Bode diagram and the output signal parameters (amplitude, frequency and DC offset), facilitating the subsequent design procedure. The control scheme is robust with respect to both power-stage parameter variations and external disturbances and can be implemented by means of conventional electronic circuitry. Simulations and experimental results for both reactive and nonlinear loads are presented     

基于脉冲阶梯调制的级联型逆变器研究

脉冲阶梯调制(PSM)是将脉宽调制(PWM)与阶梯调制(SM)相结合,起初应用在高压直流电源系统中。将脉冲阶梯调制技术应用到逆变器领域,提出了基于脉冲阶梯调制的级联型逆变器。介绍了级联逆变器的基本拓扑,分析了PSM级联型逆变器的工作原理,研究了PSM的调制算法。该级联型逆变器具有电路结构简单、控制方法简便、开关损耗小、效率高等优点,适合高压大功率场合。建立了6模块的PSM级联型高压逆变器(可获得有效值为4 kV的输出电压)的Matlab仿真模型进行分析,给出仿真结果。仿真结果表明,PSM级联型高压逆变器的输出波形特性好,谐波含量和THD均很小。     

Some system design considerations for a high switching frequency PWM inverter

A sinusoidal PWM inverter is required to faithfully reproduce the control waveforms at the output with minimum distortion. This paper presents some design considerations for such an inverter. The choice of switching frequency is the main criterion which affects the output voltage harmonic distortion at high switching frequencies. This paper shows that there exists an optimum switching frequency above which the output harmonic distortion becomes more visible. The dead time generator circuit for a low cost inverter and effect of driver circuits on the output waveform are discussed. Experimental results from laboratory models are presented.     

Topological and Modulation Design of Three-Level Z-Source Inverters

This paper presents the development of two three- level cascaded Z-source inverters, whose output voltage can be stepped down or up unlike a traditional buck three-level inverter. The proposed inverters are designed using two three-phase voltage-source inverter bridges, supplied by two uniquely designed Z-source impedance networks. These three-phase bridges can either be cascaded at their dc sides to form a dc-link-cascaded Z-source inverter or at their ac outputs using single-phase transformers to form a dual Z-source inverter. The dc-link-cascaded inverter has the advantages of not using any clamping diodes and transformers, but does not have redundant switching states within a phase leg for equalizing switching losses among the power devices. This constraint limits the modulation options for the dc-link-cascaded inverter, and indeed, it can only be controlled using the modified carrier disposition technique with appropriate “Z-source shoot-through” states inserted for achieving balanced voltage boosting and optimal “nearest-three-vectors” switching. On the other hand, the dual Z-source inverter with transformer isolation can be controlled using different modulation approaches due to the presence of redundant switching states within a phase leg. Particularly, using a modified phase-shifted-carrier (PSC) scheme with shoot-through states inserted, it is shown that the dual inverter can be implemented using only a single Z-source network, while still achieving the correct volt-sec average and switching loss equalization. This represents a significant reduction in cost, and can more than compensate for the slightly degraded spectral characteristics of the PSC scheme. To verify the theoretical concepts discussed, experimental testing has been performed with the captured results presented in a later section of the paper.      

Optimal Variable Switching Frequency Scheme for Reducing Switching Loss in Single-Phase Inverters Based on Time-Domain Ripple Analysis

The choice of switching frequency for pulsewidth modulation single-phase inverters, such as those used in grid-connected photovoltaic application, is usually a tradeoff between reducing the total harmonic distortion (THD) and reducing the switching loss. This paper discusses an approach to minimize the switching loss while meeting a given THD requirement using variable switching frequency schemes (switching schemes with the switching frequency varying within a fundamental period). An optimal switching scheme is proposed based on time-domain current ripple analysis and the calculus of variations. The analysis shows that, to meet the same THD requirement, the optimal scheme has a significant saving on switching loss, compared to the fixed switching frequency scheme and the hysteresis control scheme, in addition to other benefits such as reduced peak switching loss and a spread spectrum of the current harmonics. The optimal scheme has been implemented in a prototype and the experimental results have verified the theoretical analysis. Also, a straightforward design method for designing filter inductors for single-phase converters is provided based on the time-domain current ripple analysis.     

Class-E DC/DC converters with a capacitive impedance inverter

Analysis and design rules are presented for three class-E switching-mode DC/DC power converters, each with a capacitive impedance inverter. Experimental results are given for one of the converters. A zero-voltage switching technique is achieved for both class-E inverters and rectifiers. Therefore, the efficiency of the converters is very high at switching frequencies in the megahertz range. By applying a capacitive impedance inverter, lossless operation of the class-E inverter can be obtained for a wide range of converter load resistance, from full load to infinity. Experimental results are in excellent agreement with the theoretical calculations. Only a 12% relative bandwidth of the switching frequency is required to maintain a constant DC output voltage for the load resistance from full load to infinity at about 1 MHz with 15-W output     

Fundamental Frequency Switching Strategies of a Seven-Level Hybrid Cascaded H-Bridge Multilevel Inverter

This paper presents a cascaded H-bridge multilevel inverter that can be implemented using only a single dc power source and capacitors. Standard cascaded multilevel inverters require $n$ dc sources for 2$n + hbox{1}$ levels. Without requiring transformers, the scheme proposed here allows the use of a single dc power source (e.g., a battery or a fuel cell stack) with the remaining $n-1$ dc sources being capacitors, which is referred to as hybrid cascaded H-bridge multilevel inverter (HCMLI) in this paper. It is shown that the inverter can simultaneously maintain the dc voltage level of the capacitors and choose a fundamental frequency switching pattern to produce a nearly sinusoidal output. HCMLI using only a single dc source for each phase is promising for high-power motor drive applications as it significantly decreases the number of required dc power supplies, provides high-quality output power due to its high number of output levels, and results in high conversion efficiency and low thermal stress as it uses a fundamental frequency switching scheme. This paper mainly discusses control of seven-level HCMLI with fundamental frequency switching control and how its modulation index range can be extended using triplen harmonic compensation.      

Improvement of light-load efficiency using width-switching scheme for CMOS transistors

This paper presents a derivation of the optimum width of transistors to minimize losses in monolithic CMOS buck converters. The high optimal width requires a tapered inverter chain gate driver. A technique called "width switching" is presented. It can be integrated with the inverter chain to maintain maximum converter efficiency over a wide power range, particularly at light load. Experimental results are presented from a chip containing CMOS transistors optimized for power levels between 50 mW and 200 mW. Challenges in implementing the width-switching scheme and other applications are also discussed.     

Output voltage distortion characterization in multilevel PWM converters

One of the main features to consider in the development of new pulsewidth modulations (PWM) for multilevel converters is the high-frequency output-voltage distortion. In this letter, a novel per-switching-cycle figure, the harmonic distortion of order n for switching cycle k(HD/sub n,k/), is introduced to quantitatively characterize the output three-phase voltage harmonic distortion of multilevel converters around all the integer multiples of the switching frequency. This figure allows for the decomposing of the modulation design problem within an output voltage fundamental cycle into an independent set of smaller problems for every switching cycle. The expression of HD/sub n,k/ as a function of the switching states' duty-ratio is presented for the three-level three-phase neutral-point-clamped voltage source inverter and it can be easily obtained for any other multilevel converter. From the evaluation of HD/sub n,k/ over 1/6th of the output-voltage fundamental-period the value of HD/sub n/ is obtained, providing a measure of the output voltage distortion in a fundamental period. This information is obtained at a lower computational cost than conventional fast Fourier transform (FFT) analysis. The accuracy of the HD/sub n/ distortion predictions is verified by comparing it to FFT-based results obtained from simulation and experiments. The expression to compute the total harmonic distortion (THD) as a function of HD/sub n/ is also derived.     

A novel space-vector current regulation scheme for afield-oriented-controlled induction motor drive

The system performance of an AC variable-speed drive directly depends on the current regulation. In this paper, a novel space-vector current regulation scheme for a field-oriented controller (FOC) is developed. Motor currents are regulated by generating appropriate inverter output voltage vectors via software-implemented comparators and a switching table. A switching table based on the angular coordinate enables the inverter to generate optimal voltage vectors. By introducing an additional triangular carrier signal to the output of original hysteresis comparators, a user-selectable high and fixed switching frequency can be obtained, further improving the driver performance. Experiments are made to verify the effectiveness and correctness of this proposed method. According to the experimental results, both simple hardware design and good current response can be attained     

Three-Level Inverter Scheme With Common Mode Voltage Elimination and DC Link Capacitor Voltage Balancing for an Open-End Winding Induction Motor Drive

A dc link capacitor voltage balancing scheme along with common mode voltage elimination is proposed for an induction motor drive, with open-end winding structure. The motor is fed from both the ends with three-level inverters generating a five level output voltage space phasor structure. If switching combinations, with zero common mode voltage in the pole voltage, are used, then the resultant voltage space vector combinations are equivalent to that of a three-level inverter. The proposed inverter vector locations exhibit greater multiplicity in the inverter switching combinations which is suitably exploited to arrive at a capacitor voltage balancing scheme. This allows the use of a single dc link power supply for the combined inverter structure. The simultaneous task of common mode voltage elimination with dc link capacitor voltage balancing, using only the switching state redundancies, is experimentally verified on a 1.5-kW induction motor drive