Direct gravure printing (DGP) method for printing fine-line electrical circuits on ceramics

The tendency toward higher packing densities and higher frequencies for telecommunication devices based on ceramic technology requires smaller dimensions for electrical wiring. Electrical thick-film circuits for ceramic and LTCC-substrates have, up to now, been printed with screen printing, where the printing lines width limit is about 125 /spl mu/m in mass production. A silicone polymer direct gravure printing (Si-DGP) process has been developed to perform smaller dimensions, down to 20 /spl mu/m lines width, for electrical circuitry. In the DGP process, the conductor paste is doctored to the grooves of the gravure and then it is pressed against the substrate. The paste is, thus, printed directly onto the substrate from the patterned gravure. The results showed that, using the DGP process, it was possible to print conductor lines down to 20 /spl mu/m in width. It was also noted that a 100% transfer of paste from the grooves of the gravure could be obtained with commercial pastes using the silicone polymer gravure. A dried thickness of up to 28 /spl mu/m was measured for the narrowest lines. Also conductor lines printed by the Si-DGP method were embedded inside LTCC-module.     

Fabrication of microvias for multilayer LTCC substrates

Advances in screen printing and photoimageable paste technologies have allowed low-temperature cofired ceramic (LTCC) circuit densities to continue to increase; however, the size of vias for Z-axis interconnections in multilayer LTCC substrates have been a limiting process constraint. In order to effectively exploit the 50-100-/spl mu/m line/spacing capabilities of advanced screen printing and photoimageable techniques, microvia technologies need to achieve 100 /spl mu/m and under in diameter. Three main steps in fabrication of microvias include via formation, via metallization or via fill, and layer-to-layer alignment. The challenges associated with the processing and equipment for the fabrication of microvias are addressed in this paper. Microvias down to 50 /spl mu/m in diameter with spacings as small as 50 /spl mu/m are achieved in 50-254-/spl mu/m-thick LTCC tape layers through the use of a mechanical punching system, whereas the minimum size of 75-/spl mu/m via/spacing is obtained using a pulse laser-drilling system in the LTCC tape layers with the same thicknesses as those for the punching test. The quality of punched microvias and laser-drilled microvias will be presented as well. Layer-to-layer alignment is crucial to the connection of vias in adjacent LTCC tape layers. Through a stack and tack machine with a three-camera vision system and an adjustable precision stage, less than 25-/spl mu/m layer-to-layer misalignment is achieved across a 114.3/spl times/114.3 mm (4.5/spl times/4.5 in) design area. In a six-layer LTCC test substrate (152/spl times/152/spl times/0.762 mm), microvias of 50, 75, and 100 /spl mu/m in diameter are successfully fabricated without the use of via catch pads. The cross section of fired microvias filled with silver conductor pastes at various locations of this substrate demonstrates a minor layer-to-layer misalignment in both X and Y directions across the substrate.     

A 1-mil/SUP 2/ single-transistor memory cell in n silicon-gate technology

For a comparison of different single-transistor cell designs and sense/refresh amplifier designs figures of merit are derived from the quasi-static behavior of the memory circuit during sensing. The principles of the different cell designs are discussed. A cell with the most favorable design has been realized with a standard n silicon-gate process sequence and contact photolithography. It uses aluminum word lines of 5 /spl mu/m width and separation, a contact hole with a size of 4 /spl mu/m to 6 /spl mu/m, and diffused bit lines with a width of 4 /spl mu/m. For the 1-mil/SUP 2/ memory cell a sense/refresh amplifier based on the gated flip-flop principle has been realized. The sensitivity of this amplifier, which is determined by the integrated circuit element tolerances is estimated and measured.     

Oxide-isolated integrated Schottky logic

Integrated Schottky logic has been fabricated in an oxide-isolated technology using 5 /spl mu/m lines and spaces. The novel device uses a merged substrate p-n-p (base width /spl sime/1.0 /spl mu/m) to clamp the collector-base junction of the oxide-walled base, down-operated n-p-n transistor. Ion-implanted low-barrier PtSi-nSi Schottky diodes are used for n-p-n collector decoupling. The average propagation delay measured on a 25-stage ring oscillator (fan-in=fan-out=1) was 2.3 ns at 65 /spl mu/A/stage and 25/spl deg/C. This 150 fJ/V power-delay product is a 3.6/spl times/ improvement compared with 540 fJ/V for junction-isolated ISL (2.7 ns at 200 /spl mu/A/stage).     

A compact efficient Schottky collector transistor switch

A vertical Schottky collector transistor switch with merged vertical n-p-n load is described which is useful in both memory and logic applications. The device has been fabricated in an infant oxide isolated bipolar technology with Schottky collector area of 3.8 /spl mu/m/spl times/5.0 /spl mu/m (0.15 mil/spl times/0.2 mil). The intrinsic n-p-n load transistor directly below the Schottky collector requires no additional surface area. Contact location to extrinsic device regions is not restricted, providing wiring flexibility. Current gains of 3 and 4 have been obtained for prototype Schottky collector and n-p-n transistors, respectively. A power-delay product of 60 fJ/V has been observed on a 25-state (fan-out=1) closed-loop inverter chain using 5 /spl mu/m metal lines and spaces. A 5.0 ns delay at 15 /spl mu/A/stage (power-delay product=75 fJ/V) reveals potential for fast, low power VLSI application. The intrinsic speed limit of 2.76 ms is attained at 60 /spl mu/A/stage.     

Coulomb blockade memory using integrated single-electron transistor/metal-oxide-semiconductor transistor gain cells

A 3/spl times/3-bit Coulomb blockade memory cell array has been fabricated in silicon-on-insulator (SOI) material. In each cell, the Coulomb blockade effect in a single-electron transistor is used to define two charge states. The charge is stored on a memory node of area 1 /spl mu/m/spl times/1 /spl mu/m or 1 /spl mu/m/spl times/70 nm and is sensed with gain by a metal-oxide-semiconductor transistor. The write/read operation for a selected cell within the array is demonstrated. The measured states are separated by /spl sim/1000 electrons for the 1 /spl mu/m/spl times/1 /spl mu/m memory node cell and by 60 electrons for the 1 /spl mu/m/spl times/70 nm memory node cell. Single-electron transistor controlled operation persists up to a temperature of 65 K.     

Self-heating and trapping effects on the RF performance of GaN MESFETs

RF power performances of GaN MESFETs incorporating self-heating and trapping effects are reported. A physics-based large-signal model is used, which includes temperature dependences of transport and trapping parameters. Current collapse and dc-to-RF dispersion of output resistance and transconductance due to traps have been accounted for in the formulation. Calculated dc and pulsed I-V characteristics are in excellent agreement with the measured data. At 2 GHz, calculated maximum output power of a 0.3 /spl mu/m/spl times/100 /spl mu/m GaN MESFET is 22.8 dBm at the power gain of 6.1 dB and power-added efficiency of 28.5% are in excellent agreement with the corresponding measured values of 23 dBm, 5.8 dB, and 27.5%, respectively. Better thermal stability is observed for longer gate-length devices due to lower dissipation power density. At 2 GHz, gain compressions due to self-heating are 2.2, 1.9, and 0.75 dB for 0.30 /spl mu/m/spl times/100 /spl mu/m, 0.50 /spl mu/m/spl times/100 /spl mu/m, and 0.75 /spl mu/m/spl times/100 /spl mu/m GaN MESFETs, respectively. Significant increase in gain compression due to thermal effects is reported at elevated frequencies. At 2-GHz and 10-dBm output power, calculated third-order intermodulations (IM3s) of 0.30 /spl mu/m/spl times/100 /spl mu/m, 0.50 /spl mu/m/spl times/100 /spl mu/m, and 0.75 /spl mu/m/spl times/100 /spl mu/m GaN MESFETs are -61, -54, and - 45 dBc, respectively. For the same devices, the IM3 increases by 9, 6, and 3 dBc due to self-heating effects, respectively. Due to self-heating effects, the output referred third-order intercept point decreases by 4 dBm in a 0.30 /spl mu/m/spl times/100 /spl mu/m device.     

A memory-cell array with normally off-type Schottky-Barrier FET's

The potential of the metal-semiconductor field-effect transistor (MESFET) as a device for a dc-stable fixed-address memory-cell array is described. The implementation of dc-coupled circuits with `normally off' MESFET's having 1-/spl mu/m gate lengths yields several inherent advantages: high packing density, low power dissipation, low-power-delay time product, and low number of masking steps for transistors, diodes, and resistors. To demonstrate these advantages a fixed-address memory array with dc-stable cells has been chosen. The integrated cell area is 2.6 mil. For a supply voltage V/SUB s/=0.6 V, a standby power dissipation per cell of 5 /spl mu/W has been achieved. The cell switches within 4 ns. The differential sense current in the digit lines is /spl Delta/I/SUB s/=6 /spl mu/A.     

Surface-emitting unstable-resonator lasers with integrated diffractive beam-forming elements

Grating-coupled surface-emitting semiconductor lasers have been integrated with focusing and spot array generating diffractive beam-forming elements. The lasers have an unstable resonator producing a 160-/spl mu/m-wide single spatial mode. The area of the outcoupler element is 160 /spl mu/m/spl times/240 /spl mu/m. For an outcoupler focusing at 500 /spl mu/m above the surface the spot size is 9 /spl mu/m/spl times/17 /spl mu/m The spot size is primarily limited by aberrations in the wavefront of the guided mode.     

A new method for pHEMT noise-parameter determination based on 50-/spl Omega/ noise measurement system

A new method for determining the four noise parameters of pseudomorphic high electron-mobility transistors (pHEMTs) based on a 50-/spl Omega/ noise measurement system without a microwave tuner is presented. The noise parameters are determined based on the noise correlation matrix technique by fitting the measured noise figure of the active device. On-wafer experimental verification up to 26 GHz is presented and a comparison with a tuner-based method is given. The scaling rules for noise parameters have also been determined. Good agreement is obtained between simulated and measured results for 2/spl times/20 /spl mu/m, 2/spl times/40 /spl mu/m, and 2/spl times/60 /spl mu/m gatewidth (number of gate fingers /spl times/ unit gatewidth) 0.25-/spl mu/m double-heterojunction /spl delta/-doped pHEMTs.     

A 60-ns 4-Mbit CMOS DRAM with built-in selftest function

A 4-Mb CMOS DRAM measuring 6.9/spl times/16.11 mm/SUP 2/ has been fabricated using a 0.9-/spl mu/m twin-tub CMOS, triple-poly, single-metal process technology. N-channel depletion-type trench cells, 2.5/spl times/5.5 /spl mu/m/SUP 2/ each, are incorporated in a p-well. A novel built-in selftest (BIST) function which enables a simultaneous and automatic test of all the memory devices on a board is introduced to reduce the RAM testing time in a system. This function is effective for system maintenance and a daily start-up test even in a relatively small system. A high-speed low-power 4-Mb CMOS DRAM with 60-ns access time, 50-mA active current, and 200-/spl mu/A standby current is realized by widening the DQ line bus which connects the sense amplifiers with DQ buffers, thereby reducing the parasitic capacitance of the DQ lines.     

A 16 DIP, 64 kbit, static MOS-RAM

A 64K/spl times/1 bit fully static MOS-RAM has been fabricated. For the purpose of replacement of 64 kbit dynamic RAM, this static RAM has been designed to be assembled in a standard 300 mil 16 pin DIP. It is the first time address multiplexing has been in static RAMs. The device with multiple addressing and improved row decoder employs a double poly Si layer and a 1.5 /spl mu/m design rule which is achieved by advanced process technology. As a result, the RAM has a 11.0 /spl mu/m/spl times/26.5 /spl mu/m (291.5 /spl mu/m/SUP 2/) cell size and a 3.84 mm/spl times/7.40 mm (28.40 mm/SUP 2/) chip size. The address access time is less than 150 ns with an active power dissipation of 400 mW.     

Variable numerical-aperture temporal-coherence measurement of resonant-cavity LEDs

The first interferometric measurements of temporal-coherence length variation with numerical aperture (NA) are described for 650 nm, resonant-cavity light-emitting diodes (LEDs) agreeing with spectrally derived results. The interferometrically measured coherence length (22 /spl mu/m to 32 /spl mu/m) reduced by 37% for a 0.42 increase in NA. For a larger range of NA (0-1), this would give coherence lengths (10 /spl mu/m-40 /spl mu/m) lying in the gap between that of conventional LEDs (/spl sim/5 /spl mu/m) and superluminescent diodes (/spl sim/60 /spl mu/m).     

STL versus ISL: an experimental comparison

Schottky-transistor logic (STL) and integrated Schottky logic (ISL) have been fabricated in both 4-/spl mu/m and 2-/spl mu/m oxide isolated processes and characterized over the military temperature range (-55 to +125/spl deg/C ambient). The temperature coefficient of the average propagation delay (t/spl tilde//SUB pd/) is positive for STL over the entire operating current range. For ISL, the temperature coefficient of t/SUB pd/ is negative at low currents and positive at high currents. Both the 4-/spl mu/m and 2-/spl mu/m ring oscillator designs studied showed this behavior. At 25/spl deg/C, t/SUB pd/ data indicate no difference between STL and ISL for practical purposes. At -55/spl deg/C, the STL has a slight (~0.1 ns) speed advantage over ISL. At 150/spl deg/C (junction), the 2-/spl mu/m STL gates with a 200 /spl Omega///spl square/ base sheet resistance have the lowest minimum t/SUB pd/ of the gates studied (0.9 ns at a total current of 190 /spl mu/A) compared to the best for ISL at 1.0 ns and 150 /spl mu/A. The ISL operates at a lower logic swing than the STL at 105/spl deg/C, and has a speed advantage in the current range useful for VLSI. Additional data are presented which demonstrate the effect of the base resistance, epitaxial resistivity and substrate resistivity on delay.     

Wafer-level packaging technology for high-Q on-chip inductors and transmission lines

In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-art high-Q on-chip inductors on top of a five-levels-of-metal Cu damascene back-end of line (BEOL) silicon process using 20-/spl Omega//spl middot/cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric benzocyclobutene (BCB) and Cu layers. For a BCB-Cu thickness of 16 /spl mu/m/10 /spl mu/m, a peak single-ended Q factor of 38 at 4.7 GHz has been measured for a 1-nH inductor with a resonance frequency of 28 GHz. Removing substrate contacts slightly increases the performance, though a more significant improvement has been obtained by combining post-processed passives with patterned ground shields: for a 2.3-nH above integrated-circuit (above-IC) inductor, a 115% increase in Q/sub BW//sup max/ (37.5 versus 17.5) and a 192% increase in resonance frequency (F/sub res/: 12 GHz versus 5 GHz) have been obtained as compared to the equivalent BEOL realization with a patterned ground shield. Next to inductors, high-quality on-chip transmission lines may be realized in the WLP layers. Losses below -0.2 dB/mm at 25 GHz have been measured for 50-/spl Omega/ post-processed coplanar-waveguide lines, above-IC thin-film microstrip lines have measured losses below -0.12 dB/mm at 25 GHz.     

On-chip test circuit for measuring substrate and line-to-line coupling noise

An on-chip test circuit has been developed to directly measure substrate and line-to-line coupling noise. This test circuit has been manufactured in a 0.35 /spl mu/m double-well double polysilicon CMOS process and consists of noise generators and switched-capacitor signal processing circuitry. On-chip analog-to-digital conversion and calibration are used to eliminate off-chip noise and to extend the measurement accuracy by removing system noise. A scan circuit is described that enables the noise waveform to be reconstructed. On-chip generators ranging in area from 0.25 /spl mu/m/sup 2/ to 1.5 /spl mu/m/sup 2/ produce noise at the receiver decreasing from 3.14 mV//spl mu/m to 0.73 mV//spl mu/m. Open and closed guard rings reduce the noise by 20% and 85%, respectively. Measurement of test circuits manufactured with an epitaxial process-5.5-/spl mu/m-thick epitaxy with 20 /spl Omega//spl middot/cm resistivity on top of a 120 /spl mu/m bulk with 0.03 /spl Omega//spl middot/cm-exhibits a frequency limit of 50MHz below which coupling is insensitive to substrate noise. The difference between experimental results and an analytic model of the line-to-line coupling capacitance ranges from 8.5% to 17.7% for different metal layers.     

SODEL FET: novel channel and source/drain profile engineering schemes by selective Si epitaxial growth technology

In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the silicon-on-depletion layer FET (SODEL FET), has the depletion layer beneath the channel region, which works as an insulator like a buried oxide in a silicon-on-insulator MOSFET. Thanks to this channel structure, junction capacitance (C/sub j/) has been reduced in SODEL FET, i.e., C/sub j/ (area) was /spl sim/0.73 fF//spl mu/m/sup 2/ both in SODEL nFET and pFET at Vbias =0.0 V. The body effect coefficient /spl gamma/ is also reduced to less than 0.02 V/sup 1/2/. Nevertheless, current drives of 886 /spl mu/A//spl mu/m (I/sub off/=15 nA//spl mu/m) in nFET and -320 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) in pFET have been achieved in 70-nm gate length SODEL CMOS with |V/sub dd/|=1.2 V. New circuit design schemes are also proposed for high-performance and low-power CMOS applications using the combination of SODEL FETs and bulk FETs on the same chip for 90-nm-node generation and beyond.     

A 4 /spl mu/m NMOS NAND structure PLA

A PLA of NAND structure, using a NMOS Si gate process, has been developed to minimize chip area and maintain medium fast speed. The smallest memory cell size of 7/spl times/9 /spl mu/m is achieved by using ion implantation for PLA bit programming with 4 /spl mu/m design rules. Dynamic clocking scheme and self-timing circuits which are used in this PLA are described. With PLA size at 20/spl times/20/spl times/20, transistor size of 8 /spl mu/m/4 /spl mu/m, and cell size of 7/spl times/12 /spl mu/m, an internal access time of 150 ns is achieved with an external 4 MHz clock. Measured circuit power dissipation is 20 mW under normal conditions.     

A 32-bit NMOS microprocessor with a large register file

Two scaled versions of a 32-bit NMOS reduced-instruction-set computer CPU, called RISC II, have been implemented on two different processing lines using the simple layout rules of C.A. Mead and L.A. Conway (1980). The lambda values are 2 and 1.5 /spl mu/m, corresponding to drawn gate lengths of 4 and 3 /spl mu/m, respectively. The design utilizes a small set of simple instructions in conjunction with a large register file in order to provide high performance. This approach has resulted in two surprisingly powerful single-chip processors.     

A surface micromachined optical scanner array using photoresist lenses fabricated by a thermal reflow process

This paper presents the design, fabrication, and operation of a newly developed micromechanical optical scanner array using a translating microlens. We have used photoresist reflow technique to form a microlens on a surface micromachined XY-stage of the scratch-drive actuation mechanism. The lens scanner is placed at the focal length from an incident optical fiber to collimate the transmitting light. The collimated beam is steered two-dimensionally by the XY-motion of the microlens with respect to the incident fiber. We also have developed a theoretical model to predict appropriate initial resist thickness and diameter for the scanning lens. An optical scanning angle of /spl plusmn/7/spl deg/ has been demonstrated by sliding a microlens of 670-/spl mu/m focal length at a physical stroke of /spl plusmn/67 /spl mu/m. Typical angular positioning resolution has been estimated to be 0.018/spl deg/.