Double-diffused graded SiGe-base bipolar transistors

Self-aligned SiGe/Si bipolar transistors have been fabricated using a single-polysilicon, double-diffused process with the base in a graded SiGe layer to improve base transit time. To remain compatible with homojunction bipolar technology, undoped SiGe base and Si emitter layers were deposited by selective epitaxy at temperatures of 700-750°C in a commercial epitaxial reactor. Maximum cutoff frequencies of 40 and 50 GHz were observed for devices with collector-emitter breakdown voltages (BV_CEO) of 4.2 and 3.0 V, respectively. Preliminary results indicate that the addition of Ge to the base of these transistors did not degrade the long-term device reliability     

Self-aligned SiGe-base heterojunction bipolar transistor byselective epitaxy emitter window (SEEW) technology

In the device a SiGe epitaxial base is integrated in a structure which uses in situ doped epitaxial lateral overgrowth for the formation of the emitter window and the extrinsic base contact. Nearly ideal I -V characteristics have been achieved for a base width of 60 nm with an intrinsic base resistance of 4.6 kΩ/□ and for emitter widths down to 0.4 μm. A DC collector current enhancement factor of 3.1 was obtained relative to a Si homojunction transistor with a 1.25 times higher intrinsic base resistance. The breakdown voltage BV_CBO is identical for both Si and SiGe devices, even though the collector-base depletion region is partly overlapped with the reduced-bandgap SiGe strained layer. The lower BV_CEO, measured for the SiGe-base transistor, is due to the higher current gain. Based on these results the fabrication of high-speed bipolar circuits that take advantage of SiGe-base bandgap engineering seems possible using selective epitaxy emitter window (SEEW) technology     

Ultra-low-power and high-speed SiGe base bipolar transistors forwireless telecommunication systems

Ultra-low-power and high-speed SiGe base bipolar transistors that can be used in RF sections of multi-GHz telecommunication systems have been developed. The SiGe base and a poly-Si/SiGe base-contact were formed by selective growth in a self-aligned manner. The transistors have a very small base-collector capacitance (below 1 fF for an emitter area of 0.2×0.7 μm) and exhibit a high maximum oscillation frequency (30-70 GHz) at low current (5-100 μA). The power-delay product of an ECL ring oscillator is only 5.1 fJ/gate for a 250-mV voltage swing. The maximum toggle frequency of a one-eighth static divider is 4.7 GHz at a switching current of 68 μA/FF     

Low-frequency noise characteristics of UHV/CVD epitaxial Si- andSiGe-base bipolar transistors

We report the first measurements of low-frequency noise in high-performance, UHV/CVD epitaxial Si- and SiGe-base bipolar transistors. The magnitude of the noise power spectral density at fixed frequency for both Si and SiGe devices is comparable for similar bias, geometry, and doping conditions, indicating that the use of strained SiGe alloys does not degrade transistor noise performance. The best recorded values of noise corner frequency were 480 Hz and 373 Hz for the Si and SiGe transistors, respectively, for multi-stripe devices with an emitter area of 0.5×10.0×3 μm². A functional dependence of the noise power spectral density on base current for both device types of I_B^1.90 was observed, and noise measurements as a function of device geometry suggest that the contributing noise sources are uniformly distributed across the emitter of the transistors, not at the emitter periphery     

Ultrahigh-performance 8-GHz SiGe power HBT

This letter has demonstrated the state-of-the-art SiGe power heterojunction bipolar transistors (HBTs) operating at 8 GHz. In a common-base configuration, a continuous wave output power of 27.72 dBm with a concurrent power gain of 12.19 dB was measured at a peak power-added efficiency of 60.6% from a single SiGe HBT with a 3-/spl mu/m emitter finger stripe width and a 1340 /spl mu/m/sup 2/ total emitter area. The highest power-performance figure of merit (FOM) of 3.8/spl times/10/sup 5/ mW/spl middot/GHz/sup 2/ achieved from the device was resulted from using an optimized SiGe heterostructure and a compact device layout, which is made possible with a heavily doped base region.     

Visualizing the doping profile of a silicon germanium HBT with polysilicon emitter using electron holography

Modern bipolar transistors use polysilicon emitters and an epitaxial grown silicon germanium (SiGe) base. For device optimization, both the SiGe base and the region of the diffused emitter is of special interest. In this paper, electron holography is applied to visualize and directly measure the two-dimensional distribution of the local potential in a high-performance SiGe heterojunction bipolar transistor. Special emphasis is put on investigating the region of the emitter diffused into the epitaxially grown base layer. In addition, we investigate the self-aligned base-link construction. We compare electron holographic measurements of the whole transistor to secondary ion mass spectrometric (SIMS) data and discuss the results.     

一种基于MBE差分外延技术的SiGe低噪声放大器

采用MBE差分外延生长SiGe HBT基区,等平面隔离,多晶硅注入、快速退火形成发射区等工艺,实现了SiGe器件的平面集成。基于上述工艺技术研制的SiGe低噪声放大器(LNA),获得了1.7 GHz的带宽,23 dB的增益和3.5 dB的噪声系数。     

High-speed scaled-down self-aligned SEG SiGe HBTs

A scaled-down self-aligned selective-epitaxial-growth (SEG) SiGe HBT, structurally optimized for an emitter scaled down toward 100 nm, was developed. This SiGe HBT features a funnel-shaped emitter electrode and a narrow separation between the emitter and base electrodes. The first feature is effective for suppressing the increase of the emitter resistance, while the second one reduces the base resistance of the scaled-down emitter. The good current-voltage performance - a current gain of 500 for the SiGe HBT with an emitter area of 0.11 /spl times/ 0.34 /spl mu/m and V/sub BE/ standard deviation of less than 0.8 mV for emitter width down to about 0.13 /spl mu/m - demonstrates the applicability of this SiGe HBT with a narrow emitter. This SiGe HBT demonstrated high-speed operation: an emitter-coupled logic (ECL) gate delay of 4.8 ps and a maximum operating frequency of 81 GHz for a static frequency divider.     

Sub-20 ps ECL circuits with high-performance super self-alignedselectively grown SiGe base (SSSB) bipolar transistors

This paper describes a high maximum frequency of oscillation f_max self-aligned SiGe-base bipolar transistor technology, based on a self-aligned selective epitaxial growth (SEG) technology including graded Ge profile in an intrinsic base and link-base engineering using a borosilicate glass (BSG) sidewall structure. The transistor is a new self-aligned transistor, which we call a Super Self-aligned Selectively grown SiGe Base (SSSB) bipolar transistor. The 1st step of the annealing (800°C, 10 min) was performed for the diffusion of boron from the BSG film, before the deposition of an emitter polysilicon film. The 2nd step of the annealing (950°C, 10 sec) of emitter drive-in was carried out, which enabled us to obtain sufficient current gain using in-situ phosphorus doped polysilicon as an emitter electrode. Sheet resistance for a link-region more than one order lower than that of the epitaxial intrinsic base was obtained after heat treatment. Base profile (boron and Ge) design, and the 2-step annealing technique have realized cut-off frequency f_T of 51 GHz and f_max of 50 GHz. ECL circuits of 19-psec gate delay have been achieved     

Lateral base design rules for optimized low-frequency noise of differentially grown SiGe heterojunction bipolar transistors

The low-frequency noise dependence on lateral design parameters was investigated for SiGe heterojunction bipolar transistors fabricated by differential epitaxy. The low-frequency noise was found to vary substantially as a function of the extrinsic base design. The dominant noise sources were located either at the interface between the polycrystalline and epitaxial Si/SiGe base, in the epitaxial Si/SiGe base link region, in the base–emitter depletion region, or at the thin SiO₂ interface layer between the polysilicon and monosilicon emitter. Boron was found to passivate interfacial traps, acting as low-frequency noise sources. Generation–recombination noise with a strong dependence on the lateral electrical field was observed for some of the designs.     

The influence of emitter-base junction design on collectorsaturation current, ideality factor, Early voltage, and device switchingspeed of Si/SiGe HBT's

In advanced Si/SiGe HBT's the base is doped much higher than emitter and collector. Base outdiffusion becomes a problem because of the formation of parasitic barriers that degrade device performance. The simulations and experiments of this paper show that a strong correlation exists between (a) the drop of the collector saturation current, (b) an increase of its ideality factor and (c) a rise of the switching time due to an additional emitter delay which can no longer be neglected. Curves of these three parameters as a function of Si/SiGe heterointerface position and outdiffusion at the base-emitter interface have been calculated and indicate that only a few nm shift may cause severe device degradation. An important result is that the collector current ideality factor or the inverse Early voltage is a very sensitive indicator for the quality of the emitter-base interface. Application of these results have yielded experimental SiGe HBT's with transit frequencies above 60 GHz     

Transistor and circuit design for 100-200-GHz ICs

Compared to SiGe, InP HBTs offer superior electron transport properties but inferior scaling and parasitic reduction. Figures of merit for mixed-signal ICs are developed and HBT scaling laws introduced. Device and circuit results are summarized, including a simultaneous 450 GHz f/sub /spl tau// and 490 GHz f/sub max/ DHBT, 172-GHz amplifiers with 8.3-dBm output power and 4.5-dB associated power gain, and 150-GHz static frequency dividers (a digital circuit figure-of-merit for a device technology). To compete with advanced 100-nm SiGe processes, InP HBTs must be similarly scaled and high process yields are imperative. Described are several process modules in development: these include an emitter-base dielectric sidewall spacer for increased yield, a collector pedestal implant for reduced extrinsic C/sub cb/, and emitter junction regrowth for reduced base and emitter resistances.     

超高压SiGe HBT器件结构及制作工艺研究

介绍了一种超高压锗硅异质结双极晶体管(SiGe HBT)的器件结构及制作工艺。该器件增大了N型赝埋层到有源区的距离,采用厚帽层锗硅基区及低浓度发射区的制作工艺,以提高SiGe HBT的击穿电压;在基区和发射区之间利用快速热处理提高工艺稳定性,并使HBT的电流增益(β)恢复到原来水平,以弥补厚帽层锗硅基区及低发射区浓度造成的电流增益降低。基区断开时,发射区到集电区的击穿电压(BVCEO)提高至10V,晶体管特征频率达到20GHz。     

Self-aligned complementary bipolar transistors fabricated with a selective-oxidation mask

This paper deals with a self-aligned complementary transistor (vertical n-p-n and vertical p-n-p) structure that is ideal for high-speed and high-accuracy analog bipolar LSI circuits. The device structure consists of a 2-µm epitaxial layer, a non-LOCOS trench isolation buried with polysilicon, and complementary transistors, which are characterized by self-aligned active base and emitter. The key feature lies in the fabrication process, which forms an active base and emitter by ion implantations through a silicon nitride film by the use of an oxidation film that covers an extrinsic base as a mask [1]. The leakage current at the emitter-base junction can be minimized, because the ion-implantation-induced residual defects are confined in the emitter and the extrinsic base regions. The current gains of both transistors (n-p-n and p-n-p) remain constant down to a collector current of Ic= 10^-9A. The typical distribution of the base-emitter offsets (ΔVBE) of transistor pairs was 0.2 mV as expressed in the standard deviation = 3σ. The maximum values of fTfor n-p-n and p-n-p transistors are 6 and 1.5 GHz, respectively.     

RTS noise in submicron SiGe epitaxial base bipolar transistors

In this paper, we report a comprehensive study of Random Telegraph Signal (RTS) noise in SiGe epitaxial base bipolar transistors. We analyse the multilevel fluctuations of base and emitter forward currents before and after reverse stress on the emitter-base junction. We show the influence of the chemical treatment preceeding polysilicon emitter deposition on noise properties. We identified that RTS noise arises from different regions in the device : the silicon/polysilicon interface if an oxidizing surface preparation is used, and the emitter periphery after stress-induced degradation. Temperature and bias dependent measurements allowed us to characterize these defects (activation energy, defect type), to analyse their impact to the low frequency noise properties of these transistors and to discuss the role of hot carrier stressing.     

A 4.2-ps ECL ring-oscillator in a 285-GHz fMAX SiGetechnology

This letter reports on the room temperature operation of a conventional SiGe bipolar ECL ring oscillator with a minimum stage delay of 4.2 ps for ~250 mV single ended voltage swing. To our knowledge, this is the lowest reported delay for a gate fabricated using transistor devices. The circuit uses 0.12 × 2 μm² emitter size SiGe n-p-n transistors with a room temperature f_T of 207 GHz and f_MAX (unilateral gain extrapolation) of 285 GHz. The ring oscillator was studied as a function of various device and circuit parameters and it was found that minimum delay is more dependent on the parasitic resistance and capacitance in the n-p-n device than on pure transit time across the device     

一种低噪声SiGe微波单片放大电路

介绍了一种利用SiGe技术制作的低噪声SiGe微波单片放大电路(MMIC)。该电路以达林顿结构的形式级联,由两个异质结双极型晶体管(HBT)和4个电阻组成;HBT采用准自对准结构,其SiGe基区为非选择性外延。在1 GHz频率下,电路噪声为1.59 dB,功率增益为14.3 dB,输入驻波比为1.6,输出驻波比为2.0。     

Application of selective epitaxial silicon and chemo-mechanicalpolishing to bipolar transistors

Successful demonstration of single-polysilicon bipolar transistors fabricated using selective epitaxial growth (SEG) and chemo-mechanical polishing (CMP) is reported. The pedestal structure made possible by the SEG/CMP process combination results in significantly reduced extrinsic-base collector capacitance. Cut-off frequency (f_T) of devices with emitter stripe width of 1 μm, a base width of 110 nm, and a peak base doping of 3×10¹⁸ cm^-3 have been observed to improve from 16 GHz to 22 GHz when the extrinsic-base collector overlap is decreased from 1 μm to 0.2 μm. Leakage current, often a problem for SEG structures, has been reduced to 27 nA/cm² for the area component, and 10 nA/cm for the edge component, by (1) appropriate post-polish processing, including a high-temperature anneal and sacrificial oxidation, (2) aligning the device sidewalls along the 〈100〉 direction, and (3) the presence of the pedestal structure. Base-emitter junction nonideality in these transistors has also been investigated     

p-n-p heterojunction bipolar transistors with buried subcollectorlayers

The buried-layer technology was applied to the fabrication of high-speed p-n-p AlGaAs/GaAs heterojunction bipolar transistors (HBTs). The subcollector layer was selectively implanted prior to the epitaxial growth of the rest of the device structure thereby eliminating the need for deep mesa isolation. Devices with 2×10-μm² emitter fingers and 100-nm base thickness had common-emitter current gains of 15 and cutoff frequencies of 17 GHz     

Simulation analysis of the DC current gain in an n-p-n a-Si:H/SiGe/Si heterojunction bipolar transistor

This paper presents the results of a simulation study focused on the evaluation of the DC characteristics of an n-p-n SiGe-based heterojunction bipolar transistor (HBT) performing an extremely thin n⁺ hydrogenated amorphous silicon (a-Si:H) emitter. The a-Si:H(n)/SiGe(p) structure exhibits an energy gap difference of approximately 0.8 eV mostly located at the valence band side and this results in an optimal configuration for the emitter/base junction to improve the emitter injection efficiency and thus the device performance.Considering a 20% Ge uniform concentration profile in the base region, simulations indicate that the DC characteristics of an a-Si:H/SiGe HBT are strictly dependent on two essential geometrical parameters, namely the emitter width and the base width. In particular, the emitter thickness degrades device characteristics in terms of current handling capabilities whereas higher current gains are obtained for progressively thinner base regions. A DC current gain exceeding 9000 can be predicted for an optimized device with a thin emitter and a 10 nm-thick, doped base.