IP虚拟交换机资源抽象及接口描述

通过可编程机制动态适应网络环境和应用的变化是未来网络交换机／路由器发展的趋势,该文根据多服务虚拟交换路由器结构（PVSMR）的技术思路,对IP交换机硬件资源进行了抽象,并在此基础上描述了IP硬交换一软交换接口,它包括两个方面：基本资源或功能的可编程控制与扩展新的功能算法。     

多服务交换资源虚拟分割算法的研究

为用户或应用提供多样性服务是网络发展的趋势，不同的服务需要相应的网络转发或交换机制支持，实现多服务交换或转发的关键是资源分配和管理，该文提出一种支持面向应用的多服务交换路由器的资源虚拟分割算法，它结合可编程路由器，根据不同应用的转发需求，为不同转发服务分配一定范围的虚拟资源区间，该虚拟分割区间能够隔离和保护不同应用网络流，为其提供一定的服务质量保障，并使服务间能够可控，动态地共享多余的资源。     

可编程路由器原型系统的设计与实现

基于网络的应用服务现在正飞速地发展,但传统的网络体系结构已经越来越难以满足当前灵活快速的、种类多样的、高服务质量的应用特点。根据多服务虚拟交换路由器结构(ProgrammableVirtualSwitchMultiserviceRouter,PVSMR)的技术思想,设计出一个可编程路由器原型系统,并就该系统平台的构建及其实现过程中有关要点进行了深入的讨论。     

策略路由的工作原理与具体网络应用

传统的路由策略都是使用从路由协议派生出来的路由表,根据目的地址进行报文的转发。在这种机制下,路由器只能根据报文的目的地址为用户提供比较单一的路由方式,它更多的是解决网络数据的转发问题,而不能提供有差别的服务。基于策略的路由为网络管理者提供了比传统路由协议对报文的转发和存储更强的控制能力。基于策略的路由比传统路由控制能力更强,使用更灵     

高速网络路由器IP报文转发技术的研究与实现

随着Internet的迅猛发展,高性能网络路由器在新一代高速IP网络中发挥着巨大的作用。而制约高性能网络路由器性能的瓶颈之一是IP报文的转发速度。针对当前先进的路由器体系结构,介绍了一种快速IP报文转发部件的设计方法及实现。     

基于MPLS网络中的分组转发研究

分析了IP报文在MPLS域中的路由选择和转发过程,与传统路由器分组选路和转发有很大不同,采用MPLS技术组建的网络有效地解决了路由器网络瓶颈问题。MPLS技术在高带宽、流量工程、VPN应用上具有独特的优势,为IP主干网提供一种新的应用方法。     

一种支持高速IPv6转发的路由器体系结构FIS

本文提出了一种在交换网络中执行转发操作的路由器体系结构,采用多个低速且具有独立转发和交换功能的转发交换结点FSN,组成多级流水线结构,以流水的方式执行报文转发和交换。本文对FIS中实现IPv6转发的关键技术—IPv6转发表的分解、转发表到FSN结点的映射、IPv6转发引擎的设计及报文调度算法进行了深入的研究,并基于FIS体系结构提出了易于硬件实现的IPv6查找机制和基于Hash老化的报文调度算法,为下一步FIS原型系统的实现提供了切实可行的方案。     

IP路由查找和报文分类模型研究

IP路由查找和报文分类作为路由器转发能力和提供高性能区分服务能力的关键因素,是当前路由器转发性能乃至整个网络性能的主要瓶颈。文章以IP路由查找和报文分类问题为研究对象,从空间几何的角度探究其本质,建立了相应数学模型MDCM,并以此为基础,讨论了各类搜索算法在IP路由查找和报文分类问题求解的优缺点,为研究和设计高性能的IP路由查找和报文分类算法提供重要指导。     

绿色路由器的低功耗FIS转发机制及其能耗分析

随着互联网的发展,现有路由器体系结构在性能、复杂性和节能等方面存在许多难以克服的问题,如何实现高效节能的转发机制是绿色高性能路由器设计面临的重大挑战.基于边交换边转发思想提出一种边转发边交换(forwarding in switching,FIS)机制,通过模糊转发流水交换减少了路由器转发和交换阶段的存储需求和访存次数.该机制复用多个低速节点构成多级流水线结构,通过低成本执行部件的规模化运行提高交换性能和IP查找速率,可降低报文查表交换的硬件实现复杂度.建立了先转发后交换(forwarding before switching,FBS)机制和FIS机制的能耗模型,使用不同模型模拟内部缓存、输入输出端口等具有不同结构的节点,仿真实验证明FIS机制比现有的FBS机制减少约12.5%的能耗.提出的分析模型适用于可扩展和绿色节能路由器的设计.     

高速网络PPP协议的实现及其安全机制的研究

研究了PPP协议在高速SDH／SONET光纤网络上的实现技术,并将其应用到高速路由器的工程实践中,实现的PPP协议软件向下和底层硬件驱动程序接口处理收到的PPP报文;向上和网络层协议IP,IPX接口将IP／IPX报文送交IP／IPX协议处理,形成发送网络层报文的控制机制。还研究了PPP协议的安全问题,包括协议的加密和认证机制,确保报文转发过程中的高速和安全性。     

MPFS: A truly scalable router architecture for next generation Internet

A new generation architecture of IP routers called massive parallel forwarding and switching （MPFS） is proposed, which is totally different from modern routers. The basic idea of MPFS is mapping complicated forwarding process into multilevel scalable switch fabric so as to implement packet forwarding in a pipelining and distributed way. This processing mechanism is named forwarding in switching （FIS）. By interconnecting multi-stage, lower speed components, called forwarding and switching nodes （FSN）, MPFS achieves better scalability in forwarding and switching performance just like MPP. We put emphasis upon IPv6 lookup problem in MPFS and propose a method for partitioning IPv6 FIB and mapping them to switch fabric. Simulation and computation results suggest that MPFS routers can support line-speed forwarding with a million of IPv6 prefixes at 40 Gbps. We also propose an implementation of 160 Tbps core router based on MPFS architecture at last.     

高性能IPv6转发引擎的FPGA实现

高速转发引擎是高性能IPv6路由器的关键技术,文章设计了一种IPv6高速转发引擎的硬件结构,编写了硬件结构的VerilogHDL模型,进行了仿真和逻辑综合,并成功用XILINX的FGPA对转发引擎进行了验证。测试结果表明,该文设计的转发引擎的结构正确,可以达到2.5G端口线速转发,满足了设计要求。     

Refined assured forwarding framework for differentiated services architecture

This paper presents a new refined assured forwarding (RAF) framework for improving the performance of DiffServ architecture where heterogeneous traffic flows share the same aggregate class. The new framework requires minimal modification to existing DiffServ routers by adding a second layer of classification of flows based on their average packet sizes and using Weighted Fair Queueing for flow scheduling. The efficiency of the new architecture in enhancing the performance of DiffServ is demonstrated by simulation results for delay, packet delivery, throughput, and packet loss, under different traffic scenarios.     

Improved parallelism and scheduling in multi-core software routers

Recent technological advances in commodity server architectures, with multiple multi-core CPUs, integrated memory controllers, high-speed interconnects, and enhanced network interface cards, provide substantial computational capacity, and thus an attractive platform for packet forwarding. However, to exploit this available capacity, we need a suitable software platform that allows effective parallel packet processing and resource management. In this paper, we at first introduce an improved forwarding architecture for software routers that enhances parallelism by exploiting hardware classification and multi-queue support, already available in recent commodity network interface cards. After evaluating the original scheduling algorithm of the widely-used Click modular router, we propose solutions for extending this scheduler for improved fairness, throughput, and more precise resource management. To illustrate the potential benefits of our proposal, we implement and evaluate a few key elements of our overall design. Finally, we discuss how our improved forwarding architecture and resource management might be applied in virtualized software routers.     

Prefix segregation scheme for a TCAM-based IP forwarding engine

A novel design for IP packet forwarding based on a new ternary content-addressable-memory configuration offers an efficient hardware solution for the longest-prefix matching problem in Internet routers. The architecture has lower update complexity, lower cost, and shorter search latency compared to the conventional TCAM structure.     

HSRP协议分析与应用

HSRP(Hot Standby R outing P rotoco l,热备份路由选择协议)主要是提供一种在IP传输失败情况下不中断服务的机制。此协议将多台路由器都映射成为一个虚拟的路由器,保证同时有且只有一个路由器代表虚拟路由器实行数据包的发送,而访问主机则把数据包发向虚拟路由器。当转发包的路由器由于某种原因而无法工作的话,则另外的路由器将被选择去代替原来的路由器,从而不会对访问主机的连通性上产生大的中断。     

主动层次多目通信路由模型

许多应用需要IP多目通信.在Internet大规模应用IP Multicast时,有效的路由是关键.这样的多目路由协议必须是有效的、可伸缩的和增量可配置的.但是传统的Internet路由对性能是不敏感的,不能平衡负载和处理拥塞.现有的大多数多目通信路由协议不仅负责数据转发,还负责路由树的构造,这给路由器带来了极大的复杂性,而且协议的配置是手动的、费时费钱的工作.该文提出一个主动层次式Multicast路由的体系结构,采用主动网络技术将多目通信路由协议的数据转发和控制机制分开,根据链路的状态信息用主动报文控     

A core stateless bandwidth broker architecture for scalable support of guaranteed services

We present a novel bandwidth broker architecture for scalable support of guaranteed services that decouples the QoS control plane from the packet forwarding plane. More specifically, under this architecture, core routers do not maintain any QoS reservation states, whether per-flow or aggregate. Instead, the QoS reservation states are stored at and managed by a bandwidth broker. There are several advantages of such a bandwidth broker architecture. Among others, it avoids the problem of inconsistent QoS states faced by the conventional hop-by-hop, distributed admission control approach. Furthermore, it allows us to design efficient admission control algorithms without incurring any overhead at core routers. The proposed bandwidth broker architecture is designed based on a core stateless virtual time reference system developed recently. This virtual time reference system provides a unifying framework to characterize, in terms of their abilities to support delay guarantees, both the per-hop behaviors of core routers and the end-to-end properties of their concatenation. We focus on the design of efficient admission control algorithms under the proposed bandwidth broker architecture. We consider both per-flow end-to-end guaranteed delay services and class-based guaranteed delay services with flow aggregation. Using our bandwidth broker architecture, we demonstrate how admission control can be done on a per domain basis instead of on a "hop-by-hop" basis. Such an approach may significantly reduce the complexity of the admission control algorithms. In designing class-based admission control algorithms, we investigate the problem of dynamic flow aggregation in providing guaranteed delay services and devise a new apparatus to effectively circumvent this problem. We conduct detailed analyses to provide theoretical underpinning for our schemes as well as to establish their correctness. Simulations are also performed to demonstrate the efficacy of our schemes.     

TCAM architecture for IP lookup using prefix properties

In modern IP routers, Internet protocol (IP) lookup forms a bottleneck in packet forwarding because the lookup speed cannot catch up with the increase in link bandwidth. Ternary content-addressable memories (TCAMs) have emerged as viable devices for designing high-throughput forwarding engines on routers. Called ternary because they store don't-care states in addition to 0s and 1s, TCAMs search the data (IP address) in a single clock cycle. Because of this property, TCAMs are particularly attractive for packet forwarding and classifications. Despite these advantages, large TCAM arrays have high power consumption and lack scalable design schemes, which limit their use. We propose a two-level pipelined architecture that reduces power consumption through memory compaction and the selective enablement of only a portion of the TCAM array. We also introduce the idea of prefix aggregation and prefix expansion to reduce the number of routing-table entries in TCAMs for IP lookup. We also discuss an efficient incremental update scheme for the routing of prefixes and provide empirical equations for estimating memory requirements and proportional power consumption for the proposed architecture.