A Novel Log-Domain Differentiator

A log-domain differentiator circuit, constructed using an appropriate input stage and a multiplier block, is proposed in this Letter. The input stage compresses the voltage at the capacitor's nodes and simultaneously produces a replica of the current that flows through the capacitor. The multiplier block realizes the desired output current. The analysis of the proposed circuit has been verified through simulation results.     

A Methodology for Long Time Constant Log-Domain Filters in CMOS

A simple methodology for implementation of low-order, current-mode, log-domain filters in CMOS technology is presented. The key transistors in the circuit are operated in weak inversion and in contrast with previous approaches may pass into the triode regime. The concept is particularly suited to implementation in silicon-on-insulator technology, because dielectric isolation of the transistors eliminates leakage currents, and because influence of the body effect on circuit function is limited. Very long time constants, on the order of 1 s or more, are obtainable. A simple elaboration of the basic unit circuit allows the time constant to be controlled by a bias current.Patrick Shoemaker received the B.A., M.S., and Ph.D. degrees in Bioengineering from the University of California, San Diego. From 1984 to 1998 he was an engineer with the Space and Naval Warfare Systems Center in San Diego, where he worked on modeling and implementation of artificial neural networks, and analog and mixed-signal circuit design. Since 1998 he has been with Tanner Research in Pasadena, California, where his work has focused on biological information processing (in particular, insect vision) and on biomimetic analog integrated circuits. Dr. Shoemaker is a member of the IEEE and the International Neural Network Society.     

Analysis and Compensation of Log-Domain Biquadratic Filter Response Deviations due to Transistor Nonidealities

A translinear log-domain integrator, the powerhouse of log-domain filtering techniques, is analyzed to determine its deviations due to major time-invariant bipolar transistor imperfections, such as parasitic emitter and base resistances, finite beta, Early effect, and area mismatches. The results are used to predict the transfer function deviations of biquad filters, for both lowpass and bandpass filter responses. It will be shown that the errors can be understood and categorized into integrator scalar and negative feedback errors, and how they can be electronically compensated. SPICE simulations, both large and small-signal analysis, are performed to verify the results.     

Synthesis of Log-Domain Filters from First-Order Building Blocks

Log-domain filters are an important class of current-mode circuits having large-signal linearity and increased tuning range over voltage-mode filter circuits of similar complexity. In this paper we describe synthesis of a single-ended, first-order filter circuit from static and dynamic translinear circuit principles, and show how higher-order filters can be easily constructed from the first-order building block. We address additional issues related to low-frequency (audio-frequency) filter design and present results measured from test circuits and a complete 15-channel filterbank system fabricated in 2 m and 1.2 m BiCMOS processes.     

Improved Biquad Structures Using Double-Output Transconductance Blocks for Tunable Continuous-Time Filters

A family of g_m-C biquad structures is derived. These biquads require only a pair of grounded capacitors and three transconductors. It is shown that a pair of complex zeros can be realized simply by replicating the output stage of the transconductance block, thereby constructing a second output current that is proportional to the original output current. Although these biquad structures are very compact, they allow independent programming of the filter's center frequency andQ . IC simulations and measurements are presented using a fifth-order tunable filter as an example.     

A Study of Different Class AB Log Domain First Order Filters

Several different class AB log-domain/translinear filters are compared in terms of their noise and distortion behavior using both analytical and simulation results. A few of the circuit topologies shown have not been considered before and are derived using a new theory for class AB dynamical circuits recently proposed. The study, although approximate, suggests ways in which both noise and distortion performance may be optimized by appropriate choice of circuit topology. Other practical aspects of the designs are also discussed.     

对数域积分电路的噪声特性研究

介绍了瞬时缩展积分器的基本原理，对数域积分器是其中重要的一种，由于对数域电路是基于晶体管的对数－指数缩展特性，且晶体管本身存在噪声源，使得安的噪声呈现出信号与噪声相互调制的特性，这与线性非缩展积分电路噪声为常数是有所不同，文中采用积分器框图形式，将噪声集中考虑为一固定噪声源进行分析，最后得出了甲类和甲乙类工作状态的对数域积分器信噪比SNR的计算公式，研究表明，只有甲乙类工作的积分电路可饱和到SNRmax，使其动态范围能比甲类状态电路的动态范围扩展很多。     

A Low-Voltage Fully Differential MOSFET-C Bandpass-Based Voltage-Controlled Oscillator for Frequency Tuning

A low-voltage fully differential MOSEFT-C bandpass-based voltage-controlled oscillator for the purpose of frequency-tuning of filters is proposed. This oscillator is guaranteed to start oscillating and provide well-controlled amplitude. Experimental filters and the filter tuning circuit are designed to demonstrate its use. The performance of this circuit is shown by experimental results.     

Realization of current-mirror filters with large time-constants

A novel scheme for realizing large time-constants in analog filters, using current-mirrors as active elements, is introduced in this paper. Instead of employing conventional capacitor multipliers, the proposed concept is based on the realization of very low values of transconductance. This has been achieved through a linear compression of the input signal in order to achieve operation of the core in a reduced bias current. The expansion performed by the output stage preserves the gain of the whole system. The validity of the proposed scheme as well as the offered benefit have been verified through simulation results using the Analog Design Environment of the Cadence software.     

A CMOS Hearing Aid Device

In this paper a CMOS Hearing Aid Device is described. The system is composed of a low-distortion low-noise preamplifier, an automatic gain control (AGC), a fully programmable switched-capacitor filter (equalizer), and a control system. The device has been fabricated in a 1.2 m CMOS analog process. The dynamic range of the device is 55 dB while the harmonic distortion components are below –50 dB. Experimental results show the feasibility of the proposed architecture.     

Design of Fully Balanced Analog Systems Based on Ordinary and/or Modified Single-Ended Opamps

The system architectures, which allow a high performance fully balanced (FB) system based on ordinary/modified single-ended opamps to be implemented, are investigated and the basic and general requirements are formulated. Two new methods of an FB analog system design, which contribute towards achieving both a high performance IC system implementation and a great reduction of the design time are presented. It is shown that a single-ended system based on any type of opamp (rail-to-rail, constant g _m , etc.), realized in any technology (CMOS, bipolar, BiCMOS, GaAs), can be easily and effectively converted to its FB counterpart in a very practical way. Using the proposed rules, any FB system implementation with opamps (data converter, modulator, filter, etc.) requires only a single-ended system version design and the drawbacks related to a conventional FB system design are avoided. The principles of the design are pointed out and they are verified by experimental results.     

Design of Monolithic Tunable CMOS Band-Pass Filter Using Current Feedback Operational Amplifiers

We propose in this paper a tunable second order band-pass filter based on two CMOS current feedback operational amplifiers (CFOAs). The CFOA includes a novel offset compensation technique. A digital building block is implemented in the proposed band-pass filter to tune its central frequency. An important feature of the adopted tuning procedure is the ability to tune the filter without affecting other characteristics such as gain, phase and quality factor. The band-pass filter topology is validated with a configuration where the central frequency is tuned from 60 MHz to 95 MHz with frequency steps of 5 MHz. Measurements of the offset-compensated CFOA are promising, and simulation results of the CFOA-based band-pass filter using the 0.18 μ m CMOS process confirm our theoretical analysis.     

Switched-capacitor decimation filter design using time-multiplexing and polyphase decomposition of transfer functions with low denominator orders

A new switched-capacitor decimation filter design technique is presented. Based on a combination of the polyphase decomposition of IIR low-pass transfer functions having small denominator order and time-multiplexed operational transconductance amplifiers, the filter presents very low sensitivity to transfer function coefficients. It suits analog front-end systems by providing signal conditioning and relaxing the filtering requirements in converting between continuous-time and discrete-time signals. A prototype decimation filter has been designed and fabricated in a standard CMOS process to verify the proposed approach. In fully differential design, the filter has a die area of 2.8 mm², dissipates 67.2 mW out of a 5 V power supply and achieves a dynamic range of 58 dB at 1% THD. Experimental measurements are found in close agreement with theory.     

A 65 mW, 0.4–2.3 GHz Bandpass Filter for Satellite Receivers

A monolithic tunable bandpass filter for satellite receiver front-ends is presented. The center frequency of the bandpass filter can be tuned from 0.4 GHz to 2.3 GHz. The filter is constructed using four transconductor-C poly-phase filter sections and has a 50 dB variable gain range. At 20 dB attenuation and at 30 dB gain the measured 1 dB compression point is –21 dBm and –56 dBm, respectively. Measured input IP3 is –12 dBm. The noise figure is 15 dB at maximum gain. An on-chip I/Q oscillator tracks the center frequency and enables automatic tuning. The bandpass filter dissipates 65 mW with 5 Volt supply voltage and occupies 0.16 mm² chip area. The filter is realized in a standard 11 GHz f _t bipolar technology.     

“模拟集成电路”课程教学内容的探讨

本文将"模拟集成电路"课程定位为后端专业课程,提出了从最新科研文献中提取课程内容的方法。本文以代表当今研究前沿的2010年"模拟集成电路"最重要学术会议的论文集为素材,通过分析和总结素材中涉及的概念,得出"模拟集成电路"教学应该覆盖的内容,并将所获得的课程与模拟集成电路界知名大学的现有模拟集成电路教学体系进行了比较。     

具有高频补偿的CMOS MOCCII

为了使MOCCII(多端输出的第二代电流传输器)能工作于高频段,本文提出了一种具有高频补偿的CMOS MOCCII电路.对于电流传输函数I_Z/I_X及,I_(Z-)/I_X采用在电流镜中加一个可调电阻方法,使得电流镜的传输函数由一阶系统变成可调极点的二阶系统,调节电阻大小,使得极点远离S平面原点,从而提高电流镜频带宽度.对于电压传递函数V_X/V_Y,在X与Y之间加并行差分对,以增加等效跨导,提高V_X/V_Y的频带宽度,同时,在X与Y之间的负载电流镜中加入一个电阻,以进一步提高VX/VY的频带宽度.仿真表明,V_X/V_Y的-3dB截止频率由补偿前的544MHz提高到补偿后的1.053GHz;I_Z/I_X及I_(Z-)/I_X的-3dB截止频率分别由补偿前的510MHz、400MHz提高到补偿后的1GHz.最后,作为应用,给出了由补偿前后MOCCII所构成的电流模式滤波器.     

用Tow-Thomas电路设计含有限非零传输零点有源滤波器的方法

Tow-Thomas电路是一种实现全极点滤波器的典型电路。本文给出了用Tow-Thoms电路设计含有限非零传输零点有源滤波器的方法，从而使Tow-Thomas电路可用于单片集成滤波器电路。而文中给出的公式可用于计算外接元件。设计实例表明了文中给出的计算公式的正确性。     

Predicting current-mode transfers in a particular group of circuits

A new theorem is introduced. From the voltage transfer functions existing in an initial network, this allows to predict the current-mode transfers available in the transformed circuit. This theorem is demonstrated and the results are discussed. An illustrative example is then analysed, the begining circuit being a 2nd ordrer Sallen-Key bandpass filter operating in voltage-mode. All the transfer functions of the associated filter operating in current-mode are deduced from this theorem.     

低压低功耗阶跃增益对数域电流模滤波器的状态空间设计方法

本文提出了一种基于状态空间方程理论的阶跃增益对数域CMOS电流模滤波器设计新方法,并构建了构成阶跃增益对数域高阶滤波器的基本状态方程及其对应的基本电路单元.可简化电路设计,易于实现电路优化;MOS管工作在亚域值区,低电压低功耗;电路中间变量可观测,可实现阶跃增益及可调带宽.采用该方法,实现了一款基于0.35μm工艺的二阶CMOS对数域电路,工作电压1.4V,功耗15μW,电路面积150×160μm2.     

Fully integrated signal conditioning of an accelerometer for implantable pacemakers

This paper shows the development of a fully integrated G _m -C 0.5–7 Hz bandpass amplifier (gain G = 400), for a piezoelectric accelerometer to be employed in rate adaptive pacemakers. The circuit, fabricated in a standard 0.8 micron CMOS technology, operates with a power supply as low as 2 V, consumes 230 nA of current, and has only a 2.1 μV_rms input referred noise. Detailed circuit specifications, measurements, and a system performance comparative analysis are presented. The physical activity system includes a fully integrated G _m -C rectifier and 3-second time average. Fully integrated very low frequency circuits were implemented with the aid of series-parallel current division in symmetrical OTAs. OTAs as low as 33 pS (equivalent to a 30 GΩ resistor) were designed, fabricated, and tested.