Comparison of ATM switching architectures

Clear examination of work currently done within CCITT indicates the importance of a broadband telecommunication network. As this network should be capable of integrating all services in an efficient way—in order to reduce cost—the asynchronous transfer mode (ATM) was selected by CCITT as the target transfer mode for implementing the broadband integrated services digital network (BISDN). This selection implies that the switching nodes in the BISDN network are capable of supporting this high-speed packet and connection-orientated technique. Within the literature different switching node architectures based upon ATM have been proposed. All of these architectures should meet the high-speed and high-throughput requirements so as to cope with the delay and jitter performance objectives. In a first step this paper describes alternative switching techniques for the basic building block (switching element) of a switching node. A common model architecture of the switching element is drafted. A classification of switching elements described in the literature is derived and the influence on the complexity and performance is weighted. In a second step the switching node architecture is further elaborated according to the control and flexibility requirements. Core (switching) and edge (switching related) functions are listed, and possible functional partitionings are discussed. Finally, these ATM switching architectures are compared according to a background frame consisting of several straightforward comparison points such as the buffering strategy, the internal routeing method, the switching overhead, the connection-orientated or connectionless operation, etc.     

Nonblocking architectures for ATM switching

General models for a class of nonblocking architectures of asynchronous transfer mode (ATM) switches are described. Hardware aspects are discussed to show the implementation feasibility of the proposed switch architectures by means of the current technology. Performance issues are studied to point out the traffic bottlenecks of the different structures. It is shown that the classification of queueing is the main concept that enables the classification of nonblocking ATM switches. Three main packet queueing strategies can be adopted in the switching fabric: input queueing, shared queueing, and output queueing. Switch architectures adopting only one of these strategies are described. The ways in which two strategies can be jointly adopted in a switching fabric to result in the mixed queueing strategies input-output queueing, input-shared queueing, and shared-output queueing are also discussed     

ATM switching architectures for wafer-scale integration

This paper proposes the use of wafer-scale integration (WSI) technology for ATM switching systems and presents two different switching architectures specifically designed for WSI. WSI is particularly useful for switching networks since the interconnection lengths are minimized when the entire network is laid out on a single semiconductor wafer. We propose a defect-tolerant multipath buffered crossbar (MBC) with an expandable structure which can easily be scaled up or down according to the choice of wafer size. We also design an ATM-based Manhattan-street network (MSN) as an alternative architecture, suitable for wafer-scale implementation. We compare the two architectures from different standpoints such as performance, defect-tolerance, delay, practicality, testability, complexity, yield, and area     

Wireless ATM network architectures

Emulated LAN technology supports mobile hosts in wireless ATM networks. This paper introduces virtual LAN (VLAN) services using ATM LAN emulation technology which operates on a client/server model. One of the attractive features of the VLAN is the capability to group users into a broadcast domain. The focus of this paper is the issue of supporting quality of service to mobiles in a wireless ATM network. Copyright © 2001 John Wiley & Sons, Ltd.     

Service-specific control architectures for ATM

The concept of a service-specific control architecture (SSCA) in an ATM environment is presented. Here, a control architecture denotes the out-of-band control and management mechanisms operational in a network or virtual network (or part thereof). An SSCA can use knowledge about the applications it serves to make better use of network resources, and thus provide a more efficient service. Such a control architecture can be designed to provide only the subset of control functions required by the applications it serves, thereby greatly reducing its complexity. The switchlet mechanism, which allows more than one control architecture to be operational simultaneously within the same network, enables the use of service-specific control architectures. Implementation work is presented to illustrate the use of switchlets and SSCAs. This includes both an environment which uses switchlets to dynamically create virtual networks, and an SSCA used to provide video- and audioconferencing facilities in an ATM environment     

Design of a non-blocking shared-memory copy network for ATM

The design of a copy network is presented for use in an ATM (asynchronous transfer mode) switch supporting BISDN (broadband integrated services digital network) traffic. Inherent traffic characteristics of BISDN services require ATM switches to handle bursty traffic with multicast connections. In typical ATM switch designs a copy network is used to replicate multicast cells before being forwarded to a point-to-point routeing network. In such designs, a single multicast cell enters the switch and is replicated once for each multicast connection. Each copy is forwarded to the routeing network with a unique destination address and is routed to the appropriate output port. Non-blocking copy networks permit multiple cells to be multicasted at once, up to the number of outputs of the copy network. Another critical feature of ATM switch design is the location of buffers for the temporary storage of transmitted cells. Buffering is required when multiple cells require a common switch resource for transmission. Typically, one cell is granted the resource and is transmitted while the remaining cells are buffered. Current switch designs associate discrete buffers with individual switch resources. Discrete buffering is not efficient for bursty traffic as traffic bursts can overflow individual switch buffers and result in dropped cells, while other buffers are under-used. A new non-blocking copy network is presented in this paper with a shared-memory input buffer. Blocked cells from any switch input are stored in a single shared input buffer. The copy network consists of three banyan networks and shared-memory queues. The design is scalable for large numbers of inputs due to low hardware complexity, O (N log₂ N), and distributed operation and control. It is shown in a simulation study that a switch incorporating the shared-memory copy network has increased throughput and lower buffer requirements to maintain low packet loss probability when compared to a switch with a discrete buffer copy network.     

A shared-memory virtual channel queue for ATM broadband terminal adaptors

In order to take advantage of the low entry cost of the future public ATM (asynchronous transfer mode) network with shared facilities, it is highly desirable to interconnect different hosts and local area networks (LANs) to the ATM network. The interface between the computer hosts or LANs and the ATM network, commonly called a broadband terminal adaptor (BTA), provides the necessary format conversion for the data packets and the ATM cells. It is conceivable that multiple packets from different virtual channels are interleaved as they arrive at the receive-end BTA. The BTA must have a sufficiently large buffer, called a virtual channel queue (VCQ), to temporarily store the partially received packets. Once a complete packet has been received, it is forwarded to the host or LAN. Whenever the buffer fills with all incomplete packets, a packet must be discarded to make room for others. In this paper, we first study, through computer simulations, the buffer size requirement of a shared-memory VCQ for different numbers of virtual channels at various packet loss probabilities. We then present two different implementation architectures for the shared-memory VCQ, and compare their hardware complexity. The second architecture with linked-queue approach, adopted in our work, requires less buffer and has better scalability to accommodate a large number of virtual channels. Various possible error conditions, such as cell losses in the ATM network and the VCQ buffer overflow, are considered. Corresponding solutions are proposed and included in the VCQ designs.     

ATM switching on demand

The different applications for which ATM broadband networks can be used are discussed. With regard to the ATM layer, the CCITT has standardized two kinds of virtual connections: virtual channel connections (VCCs) and virtual path connections (VPCs), where a VPC can be considered as an aggregate of VCCs. It is shown that two large groups of applications can be supported using either the VPC or VCC concept. In the first range of applications, only semipermanent VPC connections are supported. In the second, fully on demand VCC connections are offered to the subscribers. A flexible broadband signaling capable of handling all sorts of manipulations in a multimedia environment is described. The signaling is shown to be applicable to distributive digital TV     

Protocol architectures for satellite ATM broadband networks

The latest developments and experimentation in asynchronous transfer mode (ATM) technology show that ATM will be a candidate transport mechanism in many private and public multimedia networks. Furthermore, the interest in satellite ATM systems has grown considerably because they can rapidly and economically extend the boundaries of any terrestrial network. Currently, there is a huge increase in the demand for satellite communications operating at the Ka-frequency bands; several different systems have been proposed and are under development worldwide. Two main scenarios for satellite access network protocols are presented in this article. The first one uses ATM cell encapsulation and satellite-specific protocols for establishing and managing a connection, whereas the second one provides a highly integrated solution with the ATM protocol stack and defines a new satellite ATM (S-ATM) protocol layer     

ATM signaling transport network architectures and analysis

As public carriers plan to offer new broadband services and consolidate different types of services into a single ATM network platform, the identification of an appropriate target broadband signaling transport network architecture is necessary to ensure smooth and cost-effective signaling network evolution. A number of suggestions have been made for possible broadband signaling transport architectures, ranging from the retention of signal transfer points (STPs) to the adoption of a fully distributed signaling transport architecture supporting the associated signaling mode only. The purpose of this article is to describe these architecture alternatives and discuss their qualitative and quantitative tradeoffs. The authors focus on public networks only     

Satellite ATM network architectures: an overview

A satellite ATM network has been envisioned as the next information super-skyway. There has been a migration from traditional bent pipe satellites to onboard processing ATM satellites. The current congestion in the Internet has motivated the use of alternate paths-using satellites to support global Internet transport and access. This article presents the various system and protocol layer architectures of SATM networks     

Architectures for ATM switching systems

Eight specific architectures for asynchronous transfer mode (ATM) switching systems are compared: the Knockout, Sunshine, Lee's, Tandem Banyan, Shuffleout, and three variations on buffered Benes networks. The differences between switching systems, based on architectural choices rather than details of implementation are discussed. Several broad categories of systems based on high-level architecture choices are considered. Within each category one or more alternatives are reviewed, and an equation for the chip count for each alternative is developed. The equations are used to make plots of chip count for each network over a range of parametric values     

New architectures for optical TDM switching

A systematic theoretical study of architectures for optical TDM switching, using lithium niobate optical switches and optical fiber delay lines for storage, is undertaken. The architectures allow the bit rate and wavelength transparency of these devices to be exploited. A technique involving recursive definition and proof is used to define the networks, which are mathematically related to Benes and Waksman networks. This produces architectures that are very different from existing optical TDM networks. They exhibit economical use of components, which reaches the theoretical minimum in some cases. The use of feed-forward rather than feed-back delays give these networks superior crosstalk performance and more uniform attenuation than existing designs.<>     

Onboard switching for ATM via satellite

This article presents an architecture for onboard ATM switching. The constraints of the space environment and the associated delays (especially with geostationary satellites) create often conflicting requirements for the implementation of ATM via satellite. These requirements must be considered when designing onboard equipment. The article suggests that the use of MF-TDMA framing and of physical-layer scheduling as a preswitching stage allows for the use of standard switch fabrics onboard with additional fault tolerance and buffer mechanisms. The details of the scheduler and of the RF front end, including demodulation and demultiplexing, are presented as well as suitable switch fabrics and their performance/implementation impact. ATM is now widely considered the delivery medium for the broadband services of the future. This fact has also attracted the attention of the satellite community. Current satellite ATM trials have concentrated on trunking applications using available broadcast satellites. However, the US FCC filings for Ka band satellites, as well as Canadian W and European initiatives, have focused on a new generation of digital regenerative multibeam onboard processing satellites     

Polyhedral switching structures for ATM networks

The authors propose switching structures based on regular and non-regular polyhedra which ensure better QoS than the ATM switching networks known to date. The key idea of this solution is based on placing elementary switches on a sphere-shaped surface. Any set of adjacent switches forms a polygon, and the polygons in turn form a polyhedron     

A scalable ATM switching system architecture

The architecture of an asynchronous transfer mode (ATM) switching system for prototype applications is presented. The general concept to upgrade the existing ISDN switch with an ATM module is introduced, and the building blocks of this ATM module are described in detail. Switching of ATM cells is performed in a single application-specific integrated circuit (ASIC). ASICs can be cascaded to form large switching modules. Peripheral modules interface the ATM switch to external transmission systems and perform all ATM-related functions, including means for redundancy of the switching network. The redundancy scheme tolerates single failures without affecting the user information. A switching network architecture is shown to be capable of fulfilling varying demands in terms of the number of ports for ATM switches and cross connects, concentrators, and multiplexers     

A taxonomy of broadband integrated switching architectures

A nomenclature describing a set of essential dimensions or characteristics germane to integrated broadband switching architectures is presented. Using this vocabulary, a classification of switching architectures is proposed. The classification is intended to afford the switch designer an ordered and reasoned approach to deciding among the numerous choices in the design of broadband switches     

Stochastic models for ATM switching networks

Models that take into account the fact that the switching speed may be appreciably greater than the speed at which some sources generate their respective cells are considered. The case is investigated where the cells making up individual bursts are spaced according to some prescribed probability distribution. It is shown that the switch performance is strongly dependent on the input parameters and it is demonstrated that analytical approaches provide useful alternatives to the lengthy simulation runs needed to evaluate probabilities of rare events, such as cell losses     

Priority management in ATM switching nodes

Various space priority mechanisms and their detailed performance evaluation are described. A comparative performance study is given, indicating the excellent performance characteristics of a simple buffer management scheme called partial buffer sharing. The introduction of a second bearer capability provides a 10^-6 cell loss rate instead of 10^-10