Low-temperature electrical characterization of fully depleted eXtra-strained SOI n-MOSFETs with TiN/HfO2 gate stack for the 32-nm technology node

In this paper, experimental results for low-temperature operation on advanced eXtra-strained FD-SOI NMOS transistors with thin film, high-k dielectric, mid-gap metal gate, and with very aggressive dimensions are presented for the 32-nm technology node. The temperature dependence of some key parameters are used to analyze the impact of strain amount on the stress-induced mobility gain, to identify the major physical mechanisms responsible of this enhanced performance, as well as the short channel effect and the narrow channel effect, down to 25 nm gate length and width.     

Amorphous InGaZnO thin film transistors with SiO2/HfO2 double-layer gate dielectric fabricated at low temperature

Amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) with double-layer gate dielectric were fabricated at low temperature and characterized. A stacked 150 nm-thick SiO₂/50 nm-thick HfO₂ dielectric layer was employed to improve the capacitance and leakage characteristics of the gate oxide. The SiO₂/HfO₂ showed a higher capacitance of 35 nF/cm² and a lower leakage current density of 4.6 nA/cm² than 200 nm-thick SiO₂. The obtained saturation mobility (μ_sat), threshold voltage (V_th), and subthreshold swing (S) of the fabricated TFTs were 18.8 cm² V^?1 s^?1, 0.88 V, and 0.48 V/decade, respectively. Furthermore, it was found that oxygen pressure during the IGZO channel layer deposition had a great influence on the performance of the TFTs.     

Enhanced leakage current properties of HfO2/GaN gate dielectric stack by introducing an ultrathin buffer layer

The band alignments of HfO₂/GaN, HfO₂/SiO₂/GaN and HfO₂/Al₂O₃/GaN gate dielectric stacks were comparatively investigated by using X-ray photoelectron spectroscopy. It was observed that the introduction of an ultrathin buffer layer film (SiO₂ or Al₂O₃) in HfO₂/GaN stack can make the band alignments more symmetrical with larger barrier height as identified by the valence band offsets and electron energy loss spectrum measurements. At room temperature, the leakage current density as function of temperature is 4.1 × 10^?6, 3 × 10^?7 and 9.8 × 10^?8 A cm^?2 at the bias of 1 V for the HfO₂/GaN, HfO₂/Al₂O₃/GaN and HfO₂/SiO₂/GaN gate dielectric stacks, correspondingly. With temperature increase from room temperature to 300 °C, the HfO₂/SiO₂/GaN gate dielectric stack exhibits lowest lower leakage current density than that of others. The HfO₂/GaN high-k gate dielectric stack with an ultrathin SiO₂ buffer layer appears to be a promising candidate for future GaN based high temperature metal-oxide-semiconductor (MOS) devices applications.     

Reducing dielectric losses in MnZn ferrites by adding TiO/sub 2/ and MoO/sub 3/

We investigated the complementary effects of TiO/sub 2/ and MoO/sub 3/ additives on the magnetic properties, the core loss, and the dielectric properties of MnZn ferrites. We analyzed the composition factors influencing the permeability of MnZn ferrites. A high initial permeability base ZnO-MnO-Fe/sub 2/O/sub 3/ composition ratio was selected. Electrical and dielectric analyses indicated that the introduction of TiO/sub 2/ can improve the high-frequency loss properties of MnZn ferrite cores, but such introduction will also have a negative effect on the magnetic properties of the sintered samples. Introduction of MoO/sub 3/ can alleviate the negative influence of TiO/sub 2/ and also reduce the internal polarization intensity. As a result, the dielectric constant and corresponding dielectric loss may be reduced. We give experimental results in the paper.     

Tunneling currents through ultra thin HfO2/Al2O3/HfO2 triple layer gate dielectrics for advanced MIS devices

The dramatic scaling down of silicon integrated circuits has led to an intensive study of high dielectric constant materials as an alternative to the conventional insulators currently employed in microelectronics, i.e., silicon dioxide, silicon nitride, or oxynitride, which seem to have reached their physical limit in terms of reduction of thickness due to large leakage gate current. Introducing a physically thicker high-K material can reduce the leakage current to the acceptable limit. There are many potential candidates for high-K gate dielectrics with the K-valves ranging from 9 to 80. These are Al₂O₃, Y₂O₃, La₂O₃, Ta₂O₅, TiO₂, ZrO₂ and HfO₂. It is important to study the various leakage mechanisms in these films with the aim of improving their leakage current characteristics for use in advanced microelectronics devices. A procedure for calculating the tunneling current for stacked dielectrics is developed and subsequently applied to ultra thin films with equivalent oxide thickness (EOT) of 3.0 nm. Tunneling currents have been calculated as a function of gate voltage for different structures. Direct and Fowler-Nordheim tunneling currents through triple layer dielectrics are investigated for substrate injection. Using exact tunneling transmission calculations, current density–gate voltage (J _g?V _g) characteristics for ultra thin single layer gate dielectrics with different thicknesses have been shown to agree well with recently reported experiments. Extensions of this approach demonstrate that tunneling currents in HfO₂/Al₂O₃/HfO₂ structure with equivalent oxide thickness of 3.0 nm can be significantly lower than that through single layer oxides of the same thickness.     

Growth and characterization of HfO2 high-k gate dielectric films by laser molecular beam epitaxy (LMBE)

The HfO₂ gate dielectric films were fabricated by the laser molecular beam epitaxy (LMBE) technique. High-resolution transmission electron microscopy (HRTEM) observation showed that under optimized condition, there is no detectable SiO₂ interfacial layer in the as-deposited film and a SiO₂ interfacial layer of about 0.4 nm was formed at the Si interface due to the post deposition annealing. Capacitance–voltage (C–V) measurement of the film revealed that the equivalent oxide thickness was about 1.3 nm. Such a film showed very low leakage current density of 1.5 × 10⁻² A cm⁻² at 1 V gate bias from the current–voltage (I–V) analysis. The conduction mechanisms as a function of temperature T and electric field E were also systematically studied.     

Characterization of poly(vinylidene fluoride-trifluoroethylene) 50/50 copolymer films as a gate dielectric

Thin films of poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) 50/50 copolymer were prepared by spin coating on p-Si substrate. Thermal behavior of the film was observed by measuring the film thickness with ellipsometry as a function of the temperature and abrupt volume expansion was observed at 130–150 °C. Capacitance-voltage (C-V) and current-voltage (I-V) behavior of the aluminum/P(VDF-TrFE)/p-Si MIS (metal-insulator-semiconductor) structures were studied and dielectric constant of the P(VDF-TrFE) film was measured to be about 15.3 at optimum condition. No hysteresis was observed in the C-V curve for films as deposited and annealed (70–200 °C). Films annealed at temperatures higher than the volume expansion temperature showed substantial surface roughness due to the crystallization. Flat band voltage (V_FB) of the MIS structure with as deposited films was about −0.3 V and increased up to −2.0 V with annealing. This suggested that positive charges were generated in the film. Electronic properties of the annealed P(VDF-TrFE) film at above melting temperature were degraded substantially with larger shift in flat band voltage, low dielectric constant and low breakdown voltage. Organic thin film transistor with pentacene active layer and P(VDF-TrFE) as a gate dielectric layer showed a mobility of 0.31 cm²/V·s and threshold voltage of −0.45 V.     

十二位SOI/CMOS数模转换器的研制

介绍一种SOI／CMOS数模转换器的设计和工艺。电路采用了SOI（Silicon On Insulator)材料代替常规的体硅，使电路具有高速、抗辐照的特点；同时，电路采用独特分段结构和3－7温度编码电路，降低了对R－2R电阻网络的精度要求，提高了转换精度。     

Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

Due to the limitations in conventional complementary metal-oxide-semiconductor (CMOS) scaling technology in recent years, innovation in transistor structures and integration of novel materials has been a key to enhancing the performance of CMOS field-effect transistors (FETs) of past technology generations. Tremendous progress of high dielectric constant (high-k) gate stacks has been made in recent years and some of them have come into application in CMOS devices. However, many challenges remain, such as: (a) suitable permittivity, band gap and band alignment for dielectrics, on Si, (b) thermodynamic stability and interface engineering at both high-k/Si interface and metal/metal interface, (c) depletion effect, high gate resistance and its incompatibility with high-k for metal gate, and (d) low performance attributed to threshold voltage instability. Based on current progress and fundamental considerations, we review the current status and challenges in novel high-k dielectrics and metal gates research for planar CMOS devices and alternative device technologies to provide insights for future research. Finally, this review concludes with perspectives towards the future gate stack technology and challenges in advanced CMOS devices.     

Interfacial reaction and electrical properties of HfO2 film gate dielectric prepared by pulsed laser deposition in nitrogen: role of rapid thermal annealing and gate electrode

The high-k dielectric HfO(2) thin films were deposited by pulsed laser deposition in nitrogen atmosphere. Rapid thermal annealing effect on film surface roughness, structure and electrical properties of HfO(2) film was investigated. The mechanism of interfacial reaction and the annealing atmosphere effect on the interfacial layer thickness were discussed. The sample annealed in nitrogen shows an amorphous dominated structure and the lowest leakage current density. Capacitors with high-k HfO(2) film as gate dielectric were fabricated, using Pt, Au, and Ti as the top gate electrode whereas Pt constitutes the bottom side electrode. At the gate injection case, the Pt- and Au-gated metal oxide semiconductor devices present a lower leakage current than that of the Ti-gated device, as well as similar leakage current conduction mechanism and interfacial properties at the metal/HfO(2) interface, because of their close work function and chemical properties.     

TiO2/SiOxNy/SiO2层叠结构栅介质的电容-电压特性研究

本文讨论了以射频磁控溅射为主要工艺制备的TiO2/SiOxNy/SiO2结构高k栅介质.文中重点讨论了不同成分界面SiOxNy薄膜作用下,栅介质整体电容-电压特性的异同,并论述了SiO2界面层在保证栅介质良好电学性能方面的作用.     

部分耗尽环栅CMOS/SOI总剂量辐射效应研究

采用硅离子注入工艺对注氧隔离(SIMOX)材料进行改性,在改性材料和标准SIMOX材料上制作了部分耗尽环型栅CMOS/SOI反相器,并对其进行60Co γ射线总剂量辐照试验.结果表明,受到同样总剂量辐射后,改性材料制作的反相器与标准SIMOX材料制作的反相器相比,转换电压漂移小的多,亚阈漏电也得到明显改善,具有较高的抗总剂量辐射水平.     

Layer-by-layer structured polymer/TiO2 thin film and its gate dielectric application

Composite materials of the polymer and inorganic dielectric material have been investigated due to synergistic effect of both flexible properties of the polymer and dielectric properties of the inorganic material. In this study, poly(methyl methacrylate-co-methacrylic acid)/titanium dioxide (PMMA-co-MAA/TiO2) bilayer films were fabricated using a spin coating method followed by a self assembled sol-gel process and then examined for a gate dielectric application of the OTFT. Fracture and surface morphologies of the bilayer film on silicon wafer was observed via both SEM and AFM. Dielectric constant of the composite film synthesized was found to be larger than that of pure polymer film. In addition, with pentacene as a conducting layer, device performance of the composite film was characterized, and it was found that the threshold gate voltage was reduced while the field induced current was increased.     

Optical and electrical H/sub 2/- and NO/sub 2/-sensing properties of Au/In/sub x/O/sub y/N/sub z/ films

In this paper, we describe the optical and electrical gas-sensing properties of In/sub x/O/sub y/N/sub z/ films with an ultrathin gold promoter overlayer. We have fabricated In/sub x/O/sub y/N/sub z/ films with a nanocrystalline porous structure by RF-sputtering in Ar/N/sub 2/ followed by an annealing process. Gold particles with 20-30-nm diameter have been formed on top of the In/sub x/O/sub y/N/sub z/ films by dc sputtering and an annealing process. We have investigated the optical H/sub 2/and NO/sub 2/-sensing properties (change of absorbance) and also the electrical sensing effect (change of electrical resistance) for these two gases. A combined optical/electrical sensor for H/sub 2//NO/sub 2/ is proposed.     

Nonvolatile floating gate memory containing AgInSbTe-SiO2 nanocomposite layer and capping the HfO2/SiO2 composite blocking oxide layer

An extremely large memory window shift of about 30.7 V and high charge storage density =2.3 × 10(13) cm(-2) at ± 23 V gate voltage sweep were achieved in the nonvolatile floating gate memory (NFGM) device containing the AgInSbTe (AIST)-SiO(2) nanocomposite as the charge trap layer and HfO(2)/SiO(2) as the blocking oxide layer. Due to the deep trap sites formed by high-density AIST nanocrystals (NCs) in the nanocomposite matrix and the high-barrier-height feature of the composite blocking oxide layer, a good retention property of the device with a charge loss of about 16.1% at ± 15 V gate voltage stress for 10(4) s at the test temperature of 85?°C was observed. In addition to inhibiting the Hf diffusion into the programming layer, incorporation of the SiO(2) layer prepared by plasma-enhanced chemical vapor deposition in the sample provided a good Coulomb blockade effect and allowed significant charge storage in AIST NCs. Analytical results demonstrated the feasibility of an AIST-SiO(2) nanocomposite layer in memory device fabrication with a simplified processing method and post-annealing at a comparatively low temperature of 400?°C in comparison with previous NC-based NFGM studies.     

O/sub 2/ sensing properties of Zn- and Au-doped Fe/sub 2/O/sub 3/ thin films

Zn- and Au-doped iron oxide thin films have been prepared by liquid phase deposition. These films have been characterized by X-ray diffraction (XRD) and scanning electron microscopy (SEM). Their performance as oxygen gas sensors has been measured. It has been shown that both the Zn and Au dopants increase the oxygen response of the pure iron oxide films. The XRD and SEM results show that Zn changes both the microstructure and the particles size of the sensing layer through the formation of a solid solution with iron oxide. However, the strong increase in sensitivity to oxygen of the Au-doped Fe/sub 2/O/sub 3/ film has been related to the more favorable chemisorption of oxygen on the small gold particles at the interface with the semiconductor oxide. The results show that Au-doped iron oxide sensors are most promising for oxygen gas sensing.     

Phase-transition temperatures and piezoelectric properties of (Bi/sub 1/2/Li/sub 1/2/)TiO/sub 3/-(Bi/sub 1/2/K/sub 1/2/)TiO/sub 3/ lead-free ferroelectric ceramics

The phase-transition temperatures and piezoelectric properties of x(Bi_1/2Na_1/2)TiO_3-y(Bi_1/2Li_1/2)TiO_3-z(Bi_1/2K_1/2)TiO₃ [x + y + z = 1] (abbreviated as BNLKT100y-100z) ceramics were investigated. These ceramics were prepared using a conventional ceramic fabrication process. The phase-transition temperatures such as depolarization temperatures T_d, rhombohedral-tetragonal phase transition temperature T_R-T, and dielectric-maximum temperature T_m were determined using electrical measurements such as dielectric and piezoelectric properties. The X-ray powder diffraction patterns of BNLKT100y-100z show the morphotropic phase boundary (MPB) between rhombohedral and tetragonal at approximately z = 0.20, and the piezoelectric properties show the maximum at the MPB. The electromechanical coupling factor &33, piezoelectric constant d₃₃ and T_d of BNLKT4-20 and BNLKT8-20 were 0.603, 176 pC/N, and 171degC, and 0.590, 190 pC/N, and 115degC, respectively. In addition, the relationship between d₃₃ and T_d of tetragonal side and rhombohedral side for BNLKT4-100z and BNLKT8-100z were presented. Considering both high T_d and high d₃₃, the tetragonal side of BNLKT4-100z is thought to be the superior composition. The d₃₃ and T_d of BNLKT4-28 were 135 pC/N and 218degC, respectively. Moreover, this study revealed that the variation of Td is related to the variation of lattice distortion such as rhombohedrality 90-alpha and tetragonality c/a.     

Pentacene thin-film transistors and inverters with plasma-enhanced atomic-layer-deposited Al2O3 gate dielectric

The performances of pentacene thin-film transistor with plasma-enhanced atomic-layer-deposited (PEALD) 150 nm thick Al₂O₃ dielectric are reported. Saturation mobility of 0.38 cm²/V s, threshold voltage of 1 V, subthreshold swing of 0.6 V/decade, and on/off current ratio of about 10⁸ have been obtained. Both depletion and enhancement mode inverter have been realized with the change of treatment method of hexamethyldisilazane on PEALD Al₂O₃ gate dielectric. Full swing depletion mode inverter has been demonstrated at input voltages ranging from 5 V to − 5 V at supply voltage of − 5 V.     

Thermal stability of advanced gate stacks consisting of a Ru electrode and Hf-based gate dielectrics for CMOS technology

Metallic Ru and Hf-based dielectrics such as HfO₂, HfSiO_x and HfSiON, are promising materials for the gate electrode and gate dielectrics, respectively. This paper reports on the thermal stability of gate stack systems comprised of Ru/Hf-based dielectrics. Layers of both types of material were prepared on Si substrate by metal-organic chemical vapour deposition (MOCVD). The stacks underwent exposure by rapid thermal annealing (RTA) in pure nitrogen ambience at temperatures 800, 900, and 1000 °C for 10 s. The samples were analysed using Rutherford backscattering spectrometry (RBS). Small changes were found in the stacks treated at 800 and 900 °C. The most stable stack was found to be one with a HfSiON dielectric layer, which was resistant also at temperature 900 °C. However, the annealing at 1000 °C induced massive diffusion at both interfaces for all types of stack. The results imply a limited thermal stability of the Ru/Hf-based dielectric gate stacks during the source/drain activation step.