Autonomous Refresh of Floating-Body Cell due to Current Anomaly of Impact Ionization

Physics of autonomous refresh is presented, which explains the mechanism of a spontaneous recovery of degraded binary states of the floating-body cell (FBC). Input current to the floating body and output current from the body balance to generate an unstable stationary state that is accompanied by two stable stationary ones. The current anomaly of impact ionization is essential for the instability that brings about the bistability and is realized by positive feedback where impact ionization current input increases as the body voltage increases. Experiments with charge pumping current as output show that the autonomous refresh is possible on a single-cell basis. Necessary conditions for a high-density memory to be autonomously refreshed are derived and assessed for state-of-the-art FBCs. FBC is shown in simulation to become an SRAM cell when the autonomous refresh is applied, which uses gate direct tunneling current as output. This is an SRAM cell that is theoretically expected to have the simplest structure ever reported.     

Design of a 128-mb SOI DRAM using the floating body cell (FBC)

A 128-Mb SOI DRAM has been developed featuring the floating body cell (FBC). To keep the cell data state from being degraded by the word-line (WL) disturb due to the charge pumping and to reduce the refresh busy rate, a sense amplifier (S/A) is arranged for every bit-line (BL) and replenishes data "1" cells' bodies with holes which are lost by the disturb in every read and write cycle. The power is reduced by operating the S/As asymmetrically between the selected and the unselected thanks to that the number of holes to be replenished in the unselected S/As for charge pumping is two order of magnitude smaller than that required for writing the data "1". The multi-pair averaging of dummy cells generates a very accurate reference current for distinguishing the data "1" and "0" and a Monte Carlo simulation shows that it achieves a sensing scheme robust enough to realize all good parts of the DRAM with a reasonable amount of redundancy. The cell's feature of quasi-nondestructive read-out is also advantageous for making an SRAM interface of the DRAM or hiding refresh from uses without sacrificing the access time.     

Market Efficiency Analysis between Facility‐Based and Service‐Based Competition

Facility‐based competition (FBC) in the telecommunications market is considered to have lower static efficiency in the short term and higher dynamic efficiency in the long term. Under service‐based competition (SBC), the entrant can reduce its setup costs by leasing network facilities from the incumbent, which makes the entrant viable, pushes the market price down and promotes static efficiency. This paper attempts to measure static efficiency by comparing the profits of the incumbent and entrant in terms of consumer surplus and social welfare under each competition type by extending the Stackelberg model. The results, assuming a linear demand function and variation in regulatory level, show that FBC results in higher social welfare than SBC on the whole. However, SBC accompanied by strong regulation is also shown to have the potential to be superior over FBC. It is also revealed that FBC exhibits a higher producer surplus (particularly, the incumbent's producer surplus) and is, therefore, more desirable in terms of dynamic efficiency. When the entrant's cost is high in FBC, social welfare is shown to be lowered, implying that cost competitiveness is a necessary condition for social welfare.     

Operation voltage dependence of memory cell characteristics in fully depleted floating-body cell

A one-transistor memory cell on silicon-on-insulator, called floating-body cell (FBC), has been developed and demonstrated. Threshold voltage difference between the "0"-state and the "1"-state, which is a key parameter for realizing a large-scale memory by FBCs, is measured and analyzed using a 96 kb array diagnostic monitor (ADM). A function test of the ADM yielded a fail-bit probability of 0.002%. A new metric relating to the fail-bit probability, that is, the ratio of the threshold voltage difference over the total threshold voltage variation, is introduced and applied to the measurement results. Read current distributions are also evaluated for various operation voltages. This paper also investigates substrate bias dependence of the threshold voltage unique to fully-depleted devices. Channel impurity and substrate impurity concentration dependence of the threshold voltage are analyzed based on experimental data and device simulation.     

Gradient match and side match fractal vector quantizers for images

In this paper, we propose gradient match fractal vector quantizers (GMFVQs) and side match fractal vector quantizers (SMFVQs), which are two classes of finite state fractal vector quantizers (FSFVQs), for the image coding framework. In our previous work, we proposed the noniterative fractal block coding (FBC) technique to improve the decoding speed and the coding performance for conventional FBC techniques. To reduce the number of bits for denoting the fractal code of the range block, the concepts of the gradient match vector quantizers (GMVQs) and the side match vector quantizers (SMVQs) are employed to the noniterative FBC technique. Unlike ordinary vector quantizers, the super codebooks in the proposed GMFVQs and SMFVQs are generated from the affine-transformed domain blocks in the noniterative FBC technique. The codewords in the state codebook are dynamically extracted from the super codebook with the side-match and gradient-match criteria. The redundancy in the affine-transformed domain blocks is greatly reduced and the compression ratio can be significantly increased. Our simulation results show that 15%-20% of the bit rates in the noniterative FBC technique are saved by using the proposed GMFVQs.     

Memory design using a one-transistor gain cell on SOI

A 512-kb memory has been developed featuring a one-transistor gain cell of size 7F/sup 2/ (F = 0.18 /spl mu/m) on SOI. The cell named the floating body transistor cell (FBC) has the ability to achieve a 4F/sup 2/ cell using self-aligned contact technologies and is proved to be scalable with respect to a cell signal. A basic operation was verified by device simulation and hardware measurement. An array driving method is disclosed which makes selective write possible. A cell signal sensing system consisting of a pair of reference cells written opposite data and comparing the combined current with the doubled cell current is shown to be robust against cell parameter variations in process and temperature. A random access time of 40 ns was simulated. Nondestructive readout and C/sub b//C/sub s/. free signal development drastically improve cell efficiency.     

余域中分形方块编码的一种快速解码结构

分形方块编码（ＦＢＣ）作为一种具有高压缩比潜力的图像编码方法，正受到越来越多的关注，余域中的分形方块编码（ＦＢＣＲＤ）是对基本ＦＢＣ的一种改进，它使得在编码效应及恢复图像质量基本不变的情况下，解码的迭代次数和计算时间大为减少，本文针对ＦＢＣＲＤ又提出一种快速解码迭代结构，使得解码迭代过程进一步优化，实验表明，总的解码计算时间比基本的ＦＢＣ和非快速解码结构的ＦＢＣＲＤ都大大地减少了，这为分形图像编码     

FRACTAL BLOCK CODING IN RESIDUE DOMAIN

A new block-based fractal image coding algorithm called Fractal Block Coding in Residue Domain (FBCRD) is proposed. In basic Fractal Block Coding (FBC) algorithm, each block (called range block) is encoded by an affine mapping from a domain block within the same image to itself. The decoder uses the parameters of these mappings to synthesize the reconstructed image through an iterative procedure. FBCRD is a modification of basic FBC. In FBCRD, range blocks and domain blocks are all residue blocks subtracted from their block means and both the parameters of affine mappings and block means are coded. This modification leads to fewer iterations at the decoder. An optimized decoding strategy is also introduced which reduces total decoding time by more than half of that of basic FBC. This improvement is favorable for real time implementation of fractal image compression. Supported in Part by the Defence Preresearch Foundation, the National Science Foundation of Guangdong Prooince and the National “Chinbing” Project     

Quantizers with uniform encoders and channel optimized decoders

Scalar quantizers with uniform encoders and channel optimized decoders are studied for uniform sources and binary symmetric channels. It is shown that the natural binary code (NBC) and folded binary code (FBC) induce point density functions that are uniform on proper subintervals of the source support, whereas the Gray code (GC) does not induce a point density function. The mean-squared errors (MSE) for the NBC, FBC, GC, and for randomly chosen index assignments are calculated and the NBC is shown to be mean-squared optimal among all possible index assignments, for all bit-error rates and all quantizer transmission rates. In contrast, it is shown that almost all index assignments perform poorly and have degenerate codebooks.     

Photovoltaic poperties of <Emphasis Type="Italic">n</Emphasis>-ZnO:Al/PbPc/<Emphasis Type="Italic">p</Emphasis>-Si structures

n-ZnO:Al/PbPc/p-Si photosensitive structures are fabricated for the first time. The steady-state current-voltage characteristics and spectral dependences of the relative quantum efficiency of the photoconversion of these structures are studied, and the mechanisms of charge transport and the photosensitivity processes are discussed. It is concluded that they are promising for application as multiband photoconverters of natural light.     

Charge transport in 4<Emphasis Type="Italic">H</Emphasis>-SiC detector structures under conditions of a high electric field

Transport of nonequilibrium charge packets in a structure with a Schottky barrier fabricated on a CVD-grown n-4H-SiC film has been studied at the maximum strength of an electric field at 1.1 MV/cm. The charge was introduced by separate α-particles and recorded by nuclear spectrometric techniques. A superlinear rise in the recorded charge as a function of the reverse bias applied to the structure was observed. Simultaneously, and also superlinearly increased the scatter in the spectrum of the charge amplitude. The observed effect is attributed to the initial stage of impact ionization. The manifestation of the process at unconventionally low fields (～1 MV/cm) is accounted for by specific features of the process of charge generation. Carriers generated by slowing-down α-particles are “hot” from the very beginning.     

分析波导问题的松弛迭代区域分解法

针对基于Schwarz交替法的选代区域分解法,在分析波导问题时遇到的不收敛的困难,该文从实际场分布出发,在划分区域的虚拟边界上给出了连接子域的吸收虚拟边界条件,用以保证相邻子域间的波传播,从而构建了一种能够分析波导问题的收敛的迭代区域分解法。在此基础上进一步引入松弛算法,用于加快迭代收敛速度。数值计算结果表明了该方法的有效性。     

Structurally complex two-hole and two-electron slow traps with bikinetic properties in <Emphasis Type="Italic">p</Emphasis>-ZnTe and <Emphasis Type="Italic">n</Emphasis>-ZnS crystals

Thermal-activation and photoactivation methods were used to ascertain the existence of two-hole traps in p-ZnTe crystals and two-electron traps in n-ZnS. It was found that these traps have a large number of energy states that are grouped in two series of levels: E_V+(0.46–0.66) eV and E_V+(0.06–0.26) eV in p-ZnTe and E_C?(0.6–0.65) eV and E_C?(0.14–0.18) eV in n-ZnS. Both the hole and the electron traps belong to the class of slow traps with bikinetic properties. These traps feature normal kinetic properties in the state with a single trapped charge carrier and feature anomalous kinetic properties in the state with two charge carriers. Multiple-parameter models allowing for a relation of traps in p-ZnTe and n-ZnS to the vacancy-impurity pairs distributed according to their interatomic distances and localized in the region of microinhomogeneities with collective electric fields that repel the majority charge carriers are suggested. The main special features of behavior of electron and hole traps are explained consistently using the above models.     

部分耗尽SOI工艺器件辐射效应的研究

对0.13μm部分耗尽SOI工艺的抗辐射特性进行了研究.首先通过三维仿真研究了单粒子事件中的器件敏感区域,随后通过实验分析了器件的总剂量效应.三维仿真研究了离子入射位置不同时SOI NMOS器件的寄生双极效应和电荷收集现象,结果表明,离子入射在晶体管的体区和漏区时,均可以引起较大水平的电荷收集.对SRAM单元的单粒子翻转效应(SEU)进行了仿真,结果表明,体区和反偏的漏区都是翻转的敏感区域.通过辐照实验分析了器件的总剂量效应,在该工艺下对于隐埋氧化层,关断状态是比传输门状态更劣的辐射偏置条件.     

Effect of hydrogen sulfide on photoelectric characteristics of Al-<Emphasis Type="Italic">n</Emphasis>-Si-SnO<Subscript>2</Subscript>:Cu-Ag isotype heterostructures

Electrical and photoelectric properties of Al-n-Si-SnO₂:Cu-Ag heterostructures are studied. It is established that the charge transport in this structure is caused by double injection of charge carriers in the diffusion approximation. A 35% increase in the photocurrent is observed after exposing the heterostructure to a mixture of 1% of H₂S with N₂. The initial values of the photocurrent are recovered if the heterostructure is subsequently exposed to air. The rise and decay times of the photosignal are relatively short: 1 and 3 min, respectively.     

Intracell charge-transfer structures for signal processing

An approach is presented for implementing a fully programmable transversal filter using surface charge-transfer techniques. Summation of the signals from each output tap is performed automatically by using common output electrodes, and fixed binary tap weights are Provided by selectively controlling the transfer of charge within each cell. Charge packets representing a sampled data input signal are inserted into individual cells where they remain until they are replaced by a new sample. Any combination of these packets can be nondestructively read during any clock cycle with the output being automatically summed. Since the charge does not leave the cell, but is simply "sloshed" back and forth within it during a read-out cycle, charge-transfer losses are not cumulative in this structure. The application of these structures in various familiar signal-processing functions is discussed, and both experimental results and theoretical expressions for their performance are presented. Experimental results on a simple test cell include reading the same charge more than 5 × 10⁵times and demonstrating a charge-transfer loss of less than 10^-7per transfer.     

Charge transport in Fe-<Emphasis Type="Italic">p</Emphasis>-InP diode structures

The mechanism of charge transport in Fe-p-InP diode structures and its dependences on illumination and magnetic field were investigated. It is shown that a double injection in a drift approximation into a high-resistivity π-layer is the main mechanism of charge transport. Phenomena of the suppression of a forward current with light (negative photoresponse) and a sharp increase in the differential resistance in a magnetic field are observed and discussed.     

The effect of the charge state of nonequilibrium vacancies on the nature of radiation defects in <Emphasis Type="Italic">n</Emphasis>-Si crystals

The aim of this study is to gain insight into the effect of the charge state of nonequilibrium vacancies on the processes that occur during irradiation and annealing in silicon crystals. n-Si floating-zone crystals with an electron concentration of N = 6 × 10¹³ cm^?3 are irradiated with 25-MeV protons at 300 K. The irradiated crystals are then studied by the Hall method at temperatures ranging from 77 to 300 K. It is shown that the nature and energy spectrum of radiation defects in n-Si crystals are mainly controlled by the charge state of nonequilibrium vacancies.     

Model for Charge Accumulation in <Emphasis Type="Italic">n</Emphasis>- and <Emphasis Type="Italic">p</Emphasis>-MOS Transistors during Tunneling Electron Injection from a Gate

A quantitative model for charge accumulation in an undergate dielectric during tunneling electron injection from a gate according to the Fowler–Nordheim mechanism is developed. The model takes into account electron and hole capture at hydrogen-free and hydrogen-related traps as well as the generation of surface states during the interaction of holes with hydrogen-related centers. The experimental dependences of the threshold voltage shift and gate voltage shift of n- and p-channel MOS (metal–oxide–semiconductor) transistors on the injected charge in the constant current mode are analyzed based on the model.     

Design of Multi‐time Programmable Memory for PMICs

In this paper, a multi‐time programmable (MTP) cell based on a 0.18 μm bipolar‐CMOS‐DMOS backbone process that can be written into by using dual pumping voltages — VPP (boosted voltage) and VNN (negative voltage) — is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p‐wells are used — one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n‐well is used for the 256‐bit MTP cell array. In addition, a three‐stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of and a user memory area of , is newly proposed in this paper.