Postdeposition-Anneal Effect on Negative Bias Temperature Instability in HfSiON Gate Stacks

The effect of postdeposition anneals in various ambients on negative bias temperature instability (NBTI) in metal-organic chemical-vapor-deposited HfSiO(N) stacks is investigated. The nitrided stacks, either by anneal or decoupled plasma nitridation (DPN) followed by a postnitridation anneal in O₂ or N₂ (DPN + O₂ and DPN + N₂ ), are more degraded by NBTI than the nonnitrided ones (O₂, N₂ anneal, and as deposited stacks). Moreover, none of the nitrided stacks reaches the 10-year NBTI lifetime, while the lifetime for the nonnitrided ones is larger than 10 years. Nitrogen profiles measured by X-ray photoelectrons spectroscopy and charge-pumping-current data show a relation between nitrogen location and positively charged defects in the gate stack. The additional NBT degradation in nitrided stacks is due to filling or generation of nitrogen-related defects by holes that are injected from the channel.     

The Effect of Gate-Bias Stress and Temperature on the Performance of ZnO Thin-Film Transistors

The stability of ZnO thin-film transistors is investigated by using gate-bias stress. It is found that the application of positive and negative stress results in the device transfer characteristics shifting in positive and negative directions, respectively. It is postulated that this device instability is a consequence of charge trapping at or near the channel/insulator interface. In addition, there is a degradation of subthreshold behavior and channel mobility, which is suggested to result from the defect-state creation within the ZnO layer. The effect of elevated temperature stress shows a predominance of interface-state creation in comparison to trapping under gate-bias stress. Device instability appears to be a consequence of the charging and discharging of preexisting trap states at the interface and in the channel region of the devices. All stressed devices recover their original characteristics after a short period at room temperature without the need for any thermal or bias annealing.     

Hot-Carrier- and Constant-Voltage-Stress-Induced Low-Frequency Noise in Nitrided High- $k$ Dielectric MOSFETs

Understanding and minimization of low-frequency noise (LFN) originating from high- $k$ (HK) gate dielectrics in newgeneration MOSFETs are of critical importance to applications in RF, analog, and digital circuits. To understand the effect of stress conditions on noise, nMOSFETs were subjected to accelerated hot-carrier stress (HCS) and positive constant-voltage stress (CVS). The additional LFN introduced through stressing was evaluated on nMOSFETs with TiN metal gate and HfSiON gate dielectric. Nitridation of HfSiO gate-dielectric MOSFETs was achieved by either a high-temperature $hbox{NH}_{3}$ anneal or a lower temperature plasma anneal. Influence of different dielectric nitridation procedures on the stress-induced degradation of transconductance, threshold properties, and LFN was studied. Worst degradation conditions, i.e., $V_{g} = V_{d}$, were used for HCS, whereas for CVS, the vertical field was fixed at 10 MV/cm for all transistors to achieve comparable stressing conditions. Plasma-nitrided devices showed less increase in their noise in the linear operation region than the thermally nitrided devices. This difference in noise behavior is attributed to the nitrogen profile across the HK/Si interface and in the bulk of the HK oxide caused by different nitridation techniques. The dielectric defect profile resultant from different annealing techniques was consistent with the spectral form of the observed drain-voltage LFN.      

High-Field Degradation of Poly-Si Gate p-MOS and n-MOS Devices With Nitrided Oxides

In this paper, the authors investigate polysilicon gate MOS capacitors and MOSFET devices with nitrided oxides. These devices are known to also show a strong negative bias temperature instability (NBTI) effect. The authors analyze the dependence of oxide-trap generation in p-channel and n-channel devices on negative and positive Fowler-Nordheim (FN) charge injection stress by application of various C-V and charge pumping (CP) measurement methods yielding information on traps at different oxide locations. In the case of p-channel devices, a strong evidence for a preexistent very high oxide-trap concentration near the gate already before stress application is obtained. This feature is accompanied by a fast degradation of the p-channel devices under a negative bias stress similar to NBTI degradation. The CP measurements, which, in contrast to classical methods, are able to distinguish between actually fast interface traps and the slower near-interface oxide traps (NIOTs), showed that in all devices, a stress polarity dependence of trap generation occurs only for NIOTs and not for interface traps     

Stress voltage polarity dependence of JVD-Si/sub 3/N/sub 4/ MNSFET degradation

In this paper, we study the stress voltage polarity-dependent reliability of n-channel metal-nitride-silicon field-effect transistors (MNSFETs) with ultrathin jet vapor deposited (JVD) silicon nitride dielectric. Under constant voltage stress, device parameters such as threshold voltage and transconductance degrade. Charge trapping due to interface and bulk traps is observed. Our study shows that the degradation is polarity dependent. MNSFETs show lower degradation under positive stress fields. We have also compared the performance of MNSFETs with conventional MOSFETs under identical stress conditions. Under positive stressing, MNSFETs clearly outperform MOSFETs, but under negative stressing, MNSFETs show more degradation.     

Effect of the Interfacial $hbox{SiO}_{2}$ Layer in High-$k$ $ hbox{HfO}_{2}$ Gate Stacks on NBTI

A relative contribution of the interface and bulk dielectric defects to negative bias temperature instability (NBTI) in the metal/HfO₂/SiO₂ gate stacks was investigated. Interface trap generation was assessed by the direct-current current-voltage (DCIV) technique, which independently measures the interface defect density from bulk oxide charges and delineates the contribution of the interface defect generation to the overall NBTI measured by the threshold voltage shift (DeltaV_TH). The metal/high-fc induced traps in the interfacial SiO₂ layer were found to control the fast transient trap charging/generation processes, which affect the power-law exponents of DeltaV_TH and the stress-generated interface trap density DeltaD_IT stress time dependencies. Similar kinetics of the long-term DeltaV_TH(t) and DeltaD_IT(t) dependencies in the high-fe and SiO₂ gate stacks suggests that the degradation is governed by the same mechanism of trap charging/generation in the SiO₂ film. The investigation leads to a novel methodology for the time-to-failure (TTF) extrapolation, in which the measured DeltaV_TH and DeltaD_IT values are adjusted for the contributions from the fast transient defect charging/generation processes. It is shown that the conventional TTF analysis might greatly overestimate TTF. Post-NBTI stress recovery at zero relaxation voltage measured by the DCIV method showed that oxide charges and interface traps relax at the same rate indicating that the interface processes may dominate DeltaV_TH relaxation. At positive relaxation voltages, however, the oxide charge relaxation exhibits a fast transient component. Relaxation at positive bias also shows an as yet unexplained fast component in the interface trap recovery.     

Dielectric and conductive spectra of the composite of barium titanate and LiClO/sub 4/-doped polyethylene oxide

Dielectric and conductive frequency spectra in a 10 mHz-10 GHz range have been measured for a composite consisting of barium titanate (BaTiO/sub 3/) inclusions dispersed in a LiClO/sub 4/-doped polyethylene oxide (Li-PEO) matrix with volume fraction /spl Phi/ = 0-40%. Pure Li-PEO behaves as a dielectric showing a segmental-mode dielectric relaxation at high frequencies (dielectric regime) and transfers to an ionic conductor below 10 MHz (conductive regime). BaTiO/sub 3/ is a ferroelectric having a very large dielectric permittivity and spontaneous polarization. The introduction of BaTiO/sub 3/ into Li-PEO caused a rapid increase in permittivity in the dielectric regime. In the conductive regime, the composite exhibited an additional relaxation at a frequency related to the ratio of DC conductivity of Li-PEO and the permittivity of BaTiO/sub 3/. This relaxation was attributed to accumulation of dissociated Li/sup +/ and ClO4/sup o/ns at the inclusion/matrix interface which resulted in an increase of effective permittivity and a decrease of effective conductivity. Quantitative analyses based on mixing laws for the two-phase spherical dispersion system have shown that the Bruggeman equation accurately predicted the /spl Phi/-dependence of the effective permittivity over the entire frequency range. Regarding the effective conductivity, it predicted values lower than the observed. We attributed this discrepancy to the spontaneous polarization of BaTiO/sub 3/, which induced ion trapping to reduce the DC conductivity of Li-PEO matrix.     

复合材料的陷阱参数对其在真空中高压脉冲下沿面闪络特性的影响

长期以来真空沿面闪络现象一直制约着真空绝缘材料性能的提高，极大地限制了高功率脉冲设备的小型化和实用化进程。该文针对环氧基复合材料引入真空绝缘的背景，研究了脉冲电压作用下，复合材料的表面陷阱状况对其沿面绝缘特性的影响。通过对Simmons等温电流理论的进一步推导，完善了利用表面电位衰减测量材料表层陷阱能量分布的理论和方法，并分析了填料浓度对于材料表层陷阱的影响机制。在已有的二次电子发射雪崩(SEEA)闪络模型基础上，强调了深电子陷阱在沿面闪络过程中的作用，并定性分析了此过程中的物理机制和影响因素。复合材料中的深陷阱对于抑制材料表面的内二次电子发射有一定的作用，通过提高深陷阱的密度可以在一定程度上提高沿面闪络电压。     

The effect of ITO and Mo electrodes on the properties and stability of In-Ga-Zn-O thin film transistors

The effect of ITO and Mo electrodes on the electrical properties and stability of In-Ga-Zn-O (IGZO) thin film transistors (TFTs) are investigated. While the field effect mobility values of the devices employing ITO and Mo electrodes are similar, the former exhibit smaller threshold voltage (V_th) and subthreshold swing (SS). It is suggested that the relatively large workfunction of Mo (4.7 eV) compared to that of ITO (4.4?~?4.5 eV) induces a large Schottky barrier at the Mo/IGZO junction, which prohibits the effective injection of electrons from the metal into the IGZO semiconductor. The workfunction of IGZO is usually reported to be approximately 4.5 eV. The device stability of the two types of TFTs under negative bias stress (NBS) and positive bias stress (PBS) is similar, which implies that the degradation of the devices under bias stress is mainly affected by the trapping of carriers at the IGZO/gate insulator interface. In the presence of illumination, the devices using optically transparent ITO electrodes allow the penetration of a more abundant concentration of photons into the IGZO active layer, and thus undergo larger V_th shifts under negative bias illumination stress (NBIS). However, under positive bias illumination stress (PBIS), the TFTs using ITO exhibit smaller positive V_th shifts. The latter phenomenon is suggested to result from the excess photo-induced electrons in the bulk that counter the effect of electron trapping near the IGZO/gate insulator boundary.     

Enhanced SiO/sub 2/ reliability on deuterium-implanted silicon

Stress-induced leakage current and time-dependent dielectric breakdown were investigated to examine the reliability of gate oxides grown on hydrogen- and deuterium-implanted silicon substrates. An order of magnitude improvement in charge-to-breakdown was observed for the deuterium-implanted devices as compared with the hydrogen-implanted ones. Such reliability improvement may be explained by the reduction of defects in the SiO/sub 2/ and Si/SiO/sub 2/ interface, such as Si dangling bonds, weak Si-Si bonds, and strained Si-O bonds due to the retention of implanted deuterium at the interface and in the bulk oxide as confirmed by secondary ion mass spectroscopy.     

Doping of SiGe core-shell nanowires

Dopant deactivation in pure Si and pure Ge nanowires (NWs) can compromise the efficiency of the doping process at nanoscale. Quantum confinement, surface segregation and dielectric mismatch, in different ways, strongly reduce the carrier generation induced by intentional addition of dopants. This issue seems to be critical for the fabrication of high-quality electrical devices for various future applications, such as photovoltaics and nanoelectronics. By means of Density Functional Theory simulations, we show how this limit can be rode out in core-shell silicon-germanium NWs (SiGe NWs), playing on the particular energy band alignment that comes out at the Si/Ge interface. We demonstrate how, by choosing the appropriate doping configurations, it is possible to obtain a 1-D electron or hole gas, which has not to be thermally activated and which can furnish carriers also at very low temperatures. Our findings suggest core-shell NWs as possible building blocks for high-speed electronic device and new generation solar cells.     

Impact of STI on the reliability of narrow-width pMOSFETs with advanced ALD N/O gate stack

For the first time, a shallow trench isolation (STI)-induced enhanced degradation in pMOSFETs for ultrathin gate oxide devices has been observed. The I/sub D/ degradation is enhanced as a reduction in the gate width and the hot carrier (HC) or negative bias temperature instability (NBTI) effect. Extensive studies have been compared for atomic layer deposition (ALD)-grown and plasma-treated oxide pMOSFETs. Different temperature dependences were observed. At room temperature, hole trap is dominant for the device degradation, in which hole-trap-induced V/sub T/ is significant, whereas at high temperature under NBTI stress, interface trap becomes more significant, which dominates the device I/sub D/ degradation. In addition, the V/sub T/ rolloff can be modeled as a width narrowing effect specifically for STI. More importantly, the NBTI-induced interface/oxide traps are strongly related to the hydrogen and N/sub 2/ content in the gate oxide formation process. The interface trap generation is suppressed efficiently using the ALD-grown gate oxide. These results provide a valuable guideline for the understanding of the HC and NBTI reliabilities in an advanced ALD-grown gate oxide processes/devices.     

Energy and Spatial Distribution of Traps in SiO2/Al2O3 nMOSFETs

The energy and spatial profiling of the interface and near-interface traps in n-channel MOSFETs with SiO₂/Al₂ O₃ gate dielectrics is investigated by charge-pumping (CP) measurements. By increasing the amplitude as well as lowering the frequency of the gate pulse, an increase of the charge recombined per cycle was observed, and it was explained by the contributions of additional traps located higher in energy and deeper in position at the SiO₂/Al₂O₃ interface. In addition, CP currents, acquired after different constant voltage stress, have been used to investigate the trap generation in this dielectric stack     

Optical properties of pseudomorphic Si1-xGexfor Si-based waveguides at the λ=1300-nm and 1550-nmtelecommunications wavelength bands

The index of refraction for pseudomorphic Si_1-xGe_x layers grown on Si has been measured at wavelengths λ=1310 mn and λ=1550 nm. The refractive index values were obtained from waveguide mode profile measurements on a series of Si-Si_1-xGe _x-Si waveguides with Ge_x concentrations between x=0.01 and x=0.1. The index of refraction, n, is significantly larger for light polarized parallel to the growth direction than for light polarized in the plane of the epilayer. This birefringence is consistent with the anisotropic index change predicted using photoelastic theory, given the biaxial strain present in the pseudomorphic Si_1-xGe _x layers. At all wavelengths and polarizations, n varies linearly with the Ge concentration. The pseudomorphic Si_1-xGe _x waveguides layer are stable against lattice relaxation during short anneals at 950°C, but exhibit partial relaxation after annealing at 1200°C     

Combined Nanoscale and Device-Level Degradation Analysis of $hbox{SiO}_{2}$ Layers of MOS Nonvolatile Memory Devices

In this paper, the impact of an electrical stress applied on MOS structures with a 9.8-nm-thick $hbox{SiO}_{2}$ layer has been investigated at the device level and at the nanoscale with conductive atomic force microscopy (AFM). The goal is to correlate both kinds of measurements when studying the degradation and breakdown (BD) of tunnel oxides of nonvolatile memory devices. In particular, the generation of defects and its impact on leakage current and charge trapping in the tunnel oxide have been analyzed through spectroscopic measurements and current images. The properties and energy of the stress-induced defects (before and after BD) have been roughly estimated by thermally stimulated luminescence and AFM measurements.      

A Study of NBTI and Short-Term Threshold Hysteresis of Thin Nitrided and Thick Non-Nitrided Oxides

Negative bias temperature instability (NBTI) degradation and recovery have been investigated for 7–50-nm non-nitrided oxides and compared to thin 1.8- and 2.2-nm nitrided oxides from a dual work function technology. A wide regime of stress fields from 2.5 to 10 MV/cm has been covered. Thermal activation has been studied for temperatures from 25 $^{circ}hbox{C}$ to 200 $^{circ}hbox{C}$. The NBTI effect for the nitrided oxide is larger than for non-nitrided oxides. The percentage of threshold shift $Delta V_{rm th}$ which is “lost” during a long measurement delay—which is the quantity leading to curved $Delta V_{rm th}$ versus stress-time curves and to errors in extrapolated lifetimes—is about equal for nitrided or thick non-nitrided oxides. The fraction of recovered $Delta V_{rm th}$ is strongly dependent on stress time but only weakly dependent on stress field. Recovery in thick oxides leads to exactly the same problems as for non-nitrided oxides, and clearly, a fast measurement method is needed. The effect of short-term threshold shifts has been studied for extremely short stress times down to 200 ns.      

Quantifying the nature of hot carrier degradation in the spacerregion of LDD nMOSFETs

A detailed quantitative analysis of the hot carrier degradation in the spacer region of LDD nMOSFETs using stress conditions for maximum hole (V_g ~ V_t), substrate (I_submax) and electron (V_g = V_d) current from microseconds is presented. Damage in the spacer region reveals a two-stage drain series resistance degradation with an early stage lasting about 100 ms. The nature of damage is investigated by alternate electron, hole injection, and charge pumping measurements. It is seen that the hot carrier damage in the spacer oxide in the early stage is dominated by interface state creation with no evidence of significant damage by trapping mechanism either by electrons or holes. These results are in contrast to degradation behavior in the channel region where damage by trapping is a well-established mechanism of degradation under electron or hole injection     

Influence of Nitrogen on Negative Bias Temperature Instability in Ultrathin SiON

Negative bias temperature instability (NBTI) and its recovery phenomenon in ultrathin silicon oxynitride (SiON₂) films were investigated. To discuss the influence of nitrogen incorporation into silicon dioxide films, we used NO-nitrided SiON and plasma-nitrided SiON. As a result, it was found that the recovery for plasma-nitrided SiON is less marked than that for NO-nitrided SiON, although NBTI can be suppressed by plasma nitridation. It is also experimentally confirmed that hydrogen plays an important role in these phenomena. On the basis of these results, we proposed nitrogen-originated NBT degradation involving hydrogen at SiON/Si interface and hole trapping/detrapping. Furthermore, NBTI under ac stress was investigated. Not only NBTI was more suppressed under ac stress than under dc stress as already reported, but also, this behavior of dynamic NBTI is independent of nitrogen distribution in SiON.     

The transport and trapping of electrons in polymers

The conductivity of a polymer is determined by the availability of charge carriers and their mobility, and both terms are dominated by the trapping states in the polymer. The distribution in energy of these states may be studied by populating the states and observing the current that results from the relaxation of the trapped charges. In our experiments the states are populated by a pulse of electrons from an injection beam, and the surface potential of the polymer film is monitored by a second electron beam that passes above the charged surface; we have used this technique to study both charge trapping and the isothermal discharge process that follows a charging pulse. The general case of charge decay from an arbitrary distribution of states with retrapping can be analyzed by using a multiple trapping model, and this analysis yields the distribution of trapping states in the polymer. The analysis takes on a particularly simple form in the limit of negligible retrapping. Experimentally we have concentrated on PS-2 polystyrene and on several mono-dispersed polystyrenes. We find a change in the distribution of trapping states with molecular weight; there is also a change in trap distribution near the glass transition temperature     

Space charge characterization for the 21th century

Various methods of characterizing insulating materials by their ability to take up charge, retain it, and release it, are reviewed critically in search of measurable quantities that could be used to predict material behavior under stress up to failure conditions. Space charge characterization data on different types of materials from polymers to inorganic single crystals and ceramics are surveyed. The charging behavior is found to be influenced by many details such as surface condition and residual stresses. The traditional approach of linking dielectric breakdown to an intrinsic critical field for the material is tested against the newly emerging view that breakdown could be linked to space charge trapping at defect sites and to the attendant energetics of the mechanically strained lattice. The characterization process thus requires more care than was previously thought necessary, but after more research should become more predictive