GaAs dual-gate Schottky-barrier FET's for microwave frequencies

The benefits inherent in the tetrode structure and the potential of GaAs are combined to realized a dual-gate FET with low noise and a wide dynamic range at microwave frequencies. A design theory of the dual-gate FET is constructed on the basis of the Lehovec-Zuleeg model for single-gate FET's. The theory has led to a new device structure having a second gate with a deeper pinchoff voltage than the first which shows improved gain and noise performance. Also derived is the importance of minimizing parasitic feedthrough due, for example, to packages. Samples were fabricated using n-type epitaxial GaAs. The first and second gates were Schottky barriers, 1.2 and 2.5 µm long. The improved channel structure was accomplished by reducing the thickness of the epitaxial layer under the first gate. Samples were mounted and characterized in specially designed small-size ceramic packages with a feedthrough capacitance of only 0.004 pF. The possibility of gain control by means of second gate bias over a wide bandwidth is demonstrated.     

Graphical design and iterative analysis of the DC parameters of GaAs FET's

Two-dimensional numerical solutions of Poisson's equation and the carrier continuity equation for the short-gate GaAS field-effect transistor structure have been used to predict device performance. However, a generally accepted simplified approach to FET design has not evolved. In this paper, a simplified design technique and an iterative device analysis procedure are presented for application to GaAs FET's with gate lengths as small as 1 µm. The design technique makes it possible to determine drain saturation current and saturation transconductance for any gate size by simply scaling the appropriate curves for an FET with a 1-µm gate. Curves are also presented that relate the effective transconductance to the intrinsic transconductance for any FET geometry. The iterative analysis procedure makes it possible to determine the doping, ND, and thickness, a, of the epitaxial layer on which the device is fabricated. By simply measuring drain current and transconductance at zero gate bias and the pinchoff voltage, a method is presented which allows the epi parameters to be determined in a self-consistent fashion. This technique provides a way of mapping NDand a over a slice, as opposed to the usual technique of simply measuring pinchoff voltage (only gives ND.a²product variations).     

0.2 Micron length T-shaped gate fabrication using angle evaporation

A new technique has been developed to generate sub-half-micron T-shaped gates in GaAs MESFET's. The technique uses a single-level resist and an angle evaporation process. By using this technique, T-shaped gates with lengths as short as 0.2 µm near the Schottky interface have been fabricated. Measured gate resistance from this structure was 6.1 Ω/mm gate width which is the lowest value ever reported for gates of equal length. GaAs single- and dual-gate MESFET's with 0.3 µm long T-shaped gates have also been fabricated. At 18 GHz, maximum available gain of 9.5 dB in the single-gate FET and maximum stable gain of 19.5 dB in the dual-gate device have been measured.     

X-Band Low-Noise GaAs Monolithic Frequency Converter (Short Paper)

An X-band, low-noise GaAs monolithic frequency converter has been developed. Multicircuit functions, such as amplification, filtering, and mixing, were integrated on to a single GaAs frequency converter chip. The frequency converter consists of an X-band three-stage low-noise amplifier, an image rejection filter, an X-band dual-gate FET mixer, and an IF-band buffer amplifier. To minimize circuit size without degrading performances, an RC-coupled buffer amplifier was connected directly after a dual-gate FET mixer IF port, and one-section parallel and series microstrip lines were adopted for the amplifier. One-half-micron (1/2 µm) single-gate FET's and a one-micron (1 µm) dual-gate FET, which have an ion-implanted closely-spaced electrode structure, were used. Either via hole grounds or bonding wire grounds are selectable for the frequency converter. Chip size is 3.4x1.5 mm. The frequency converter provides less than 3-dB noise figure and more than 34-dB conversion gain.     

Phase Shifts in Single- and Dual-Gate GaAs MESFET's for 2-4-GHz Quadrature Phase Shifters

The variation of transmission phase for single- and dual-gate GaAs MESFET's with bias change and its probable effects on the performance of an active phase shifter have been studied for the frequency range 2 to 4 GHz. from measured S-parameter values for single- and dual-gate transistors, the element values of the equivalent circuits were fitted by using the computer-aided design program SUPER COMPACT. For the normal full-gate voltage range 0 to -2 V at V/sub DS/= 4 V, the single-gate MESFET varies in transmission phase from 142° to 149° at 2 GHz, and from 109° to 119° at 4 GHz. However, with drain voltage varied from 0.3 to 4 V and a constant gate-voltage bias of 0 V, the phase shifts are much larger, 105° to 145° at 2 GHz and 78° to 112° at 4 GHz. this suggests that large phase shifts may be expected in a dual-gate device and this is found to be so. With V/sub DS/= 4 Vand V/sub GS1/= - 1.0 V, variation of control (second) gate bias from 0 to - 1.75 V for the NE463 GaAs MESFET produces a transmission phase variation from 95° to 132° at 2 GHz and 41° to 88° at 4 GHz. Such phase shifts cause both amplitude and phase errors in phase-shifter circuits of the kind where signals from two FET channels are combined in quadrature with their gate voltages controlled to provide 0° to 90° phase control with constant amplitude. For the single-gate FET examined, the expected amplitude and phase errors are 0.30 dB and 6° at 2 GHz, and 0.36 dB and 10° at 4 GHz. If dual-gate FET's are used in similar circuits, the distribution of errors is different. For NE463 devices, the corresponding figures are 0.56 dB and 2° at 2 GHz and 1.2 dB and 3° at 4 GHz. the advantage of the dual-gate configuration is that the input impedance conditions are more constant than for the single-gate configuration.     

Uniformity evaluation of MESFET's for GaAs LSI fabrication

Studies were made on GaAs MESFET I-V characteristic scattering using self-aligned FET's on semi-insulating substrates. Surface treatment before gate-metal evaporation was found to have a satisfactory affect on FET drain current. The two main factors of threshold-voltage scattering in self-aligned FET's were clarified. One is the lack of uniformity in gate lengths, and the other is substrate nonuniformity. An analytical method was proposed to distinguish between threshold-voltage dispersions attributed to the factors without direct measurement of the gate lengths. Threshold-voltage scattering due to crystal inhomogeneity was estimated for both LEC and HB substrates, and for both the entire area of a 2-in wafer and an area as small as 400 µm². It was confirmed that the dislocations making up the firm network structure in LEC crystal affect the threshold voltage of self-aligned FET's and give rise to large dispersion even in the small area. High uniformity was recognized in the small area on HB substrates.     

GaAs LSI-directed MESFET's with self-aligned implantation for n+-layer technology (SAINT)

Self-aligned implantation for n⁺-layer technology (SAINT) has been developed for improvement in normally-off GaAs MESFET's to be used in LSI's. This technology has made it possible to arbitrarily control the spacing between the n⁺-implanted layer and gate contact by a dielectric lift-off process utilizing a multilayer resist with an undercut wall shape. SAINT FET's with a 1-µm gate length have above 200 mS/ mm transconductance in the normally-off region. The K value along the square-lawI - Vfitting has been improved by a factor of 3.4, compared to conventional FET's without the n⁺-layer. Thermal emission for carriers from the source n⁺-layer in the subthreshold region has been experimentally formulated. Threshold-voltage shift due to gate shortening for [011] gate FET's is definitely smaller than that for [011] gate FET's. The threshold-voltage standard deviations for [011] gate FET's with 2- and 1-µm gate lengths, obtained from a 6-mm × 9-mm area, are 9 and 34 mV, respectively. An E/D direct-coupled FET logics (DCFL) 15-stage ring oscillator with a 1-µm gate length shows a high switching speed of 45 ps/gate at a low supply voltage of 0.91 V.     

Beyond-punchthrough current in GaAs MESFET's

In a recent letter published in this journal, Patrick et al. reported on a maximum drain voltage for pinchoff Which varied exponentially with gate length in very short-gate GaAs MESFET's. The I-V characteristics given showed that this variation is associated with beyond-punchthrough drain current. Current flowing across a depleted region is an instance of the triode mode of FET operation described by other researchers in 1966. Triode-mode theory can help in the understanding of the behavior of GaAs MESFET's near pinchoff, including the devices of Patrick et al.     

Optimization of GaAs power MESFET device and material parameters for 15-GHz operation

The results of recent 15-GHz measurements on GaAs power FET's are described. The microwave performance has been determined as a function of epitaxial doping level and thickness, gate recess depth, gate finger width, and source-drain spacing. The optimum values of these parameters for 15-GHz operation are epitaxial doping level approximately 1.6 × 10¹⁷cm^-3, saturated drain current with zero gate voltage in the range 330- to 400-mA/mm gatewidth, gate recess depth between 500 and 1000 Å, gate finger width ≤ 150 µm, and source-drain spacing approximately 5 µm.     

A study of high-speed normally off and normally on Al0.5Ga0.5As heterojunction gate GaAs FET's (HJFET)

The dc, small-signal microwave, and large-signal switching performance of normally off and normally on Al0.5Ga0.5As gate heterojunction GaAs field-effect transistors (HJFET) with submicrometer gate lengths are reported. The structure of both types of devices comprises an n-type 10¹⁷-cm^-3Sn-doped active layer on a Cr-doped GaAs substrate, a p-type 10¹⁸-cm^-3Ge-doped Al0.5Ga0.5As gate layer and a p⁺-type 5 × 10¹⁸-cm^-3Ge-doped GaAs "contact and cap" layer on the top of the gate. The gate structure is obtained by selectively etching the p⁺-type GaAs and Al0.5Ga0.5As. Undercutting of the Al0.5Ga0.5As layer results in submicrometer gate lengths, and the resulting p⁺-GaAs overhang is used to self-align the source and the drain with respect to the gate. Normally off GaAs FET's with 0.5- to 0.7-µm long heterojunction gates exhibit maximum available power gains (MAG) of about 9 dB at 2 GHz. Large-signal pulse measurements indicate an intrinsic propagation delay of 40 ps with an arbitrarily chosen 100-Ω drain load resistance in a 50-Ω microstrip circuit. Normally on FET's with submicrometer gate lengths (∼0.6 µm) having a total gate periphery of 300 µm and a corresponding dc transconductance of 20-30 mmhos exhibit a MAG of 9.5 dB at 8 GHz. The internal propagation delay time measured under the same conditions as above is about 20 ps.     

Submicrometer self-aligned dual-gate GaAs FET

Experimental results show that it is possible to fabricate dual-gate GaAs FET's, with Lg1= 0.6 µm and Lg2= 1.3 µm, using conventional photoprocessing equipment, masks, and alignment tolerances. The initial source mesa establishes both the source and drain edges during the ohmic contact metal deposition. These two edges establish the lengths and positions of the two gates in the channel, during the two subsequent evaporations. Initial experimental devices gave reasonably good small-signal microwave performance: 8-dB packaged net gain with less than 6-dB simultaneous noise figure, at 6 GHz.     

Improvement in threshold-voltage uniformity in submicrometer GaAs MESFET's using an implanted p layer

A significant improvement in threshold-voltage uniformity for submicrometer gate GaAs MESFET's fabricated by direct Si implan, tation was observed using an optimized p-buried layer on conventional undoped LEC-grown substrates. Using an optimized Be-implantation scheme, we have achieved standard deviations of the threshold voltage as low as 7.6 mV from 13 × 13 FET arrays and only 16.8 mV across a 3-in wafer for FET's with a gate length of 0.6 µm. This is a very promising result for extending the GaAs MESFET IC technology into VLSI circuit complexity.     

CW oscillation characteristics of GaAs Schottky-barrier gate field-effect transistors

The CW oscillation characteristics of GaAs Schottky-barrier gate FET's have been examined at 10 GHz. The maximum output power of 41.2 mW and the maximum efficiency of 15.6 percent have been obtained for the GaAs FET with a gate length of 1.5 µm and an electrode width of 300 µm. The experimental results have shown that the GaAs FET possesses promising features for an oscillator application as well as an amplifier application.     

Dual-gate a—Si:H thin film transistors

Dual-gate accumulation mode thin film transistors have been fabricated for the first time in a-Si:H on bulk glass substrates. The devices display exceptionally high performance, as compared to previously reported single-gate a-Si:H transistors. For a channel length of 10 µm and width of 168 µm, drain currents in the range of 5-10 µA were obtained for gate biases of 15 V in both of the two conducting channels induced in the a-Si:H layer. The drain current of the TFT operating in the dual-gate mode was found to be larger than the arithmetic sum of the drain currents through the two individual channels obtained from single-mode operation. A significant difference in dc stability between the two channels was observed. The use of the dual-gate TFT as a diagnostic structure for studying interface properties and contact effects has been demonstrated.     

2-µm Gate-length enhancement mode InGaAs/InP:Fe-JFET's with high transconductance

Investigations of enhancement mode InGaAs junction field-effect transistors (JFET's) grown on InP:Fe-substrate by liquid-phase epitaxy (LPE) are reported. The JFET's with 2-µm gate length and 190- µm gate width show a threshold voltage of 0.4 V, a low drain current of < 10 µA at 0-V gate-source voltage and a maximum transconductance of 105 mS/mm. The measured transconductances of enhancement mode InGaAs/InP:Fe JFET's with different gate lengths but with the same gate width and threshold voltage decrease proportional to the inverse gate length as expected from a constant drift mobility FET model.     

A low-power high-speed ion-implanted JFET for InP-based monolithic optoelectronic IC's

We describe a high-performance fully ion-implanted planar InP junction FET fabricated by a shallow (4000-Å) n-channel implant, an n⁺source-drain implant to reduce FET series resistance, and a p-gate implant to form a shallow (2000-Å) abrupt p-n junction, followed by a rapid thermal activation. From FET's with gates 2 µm long, a transconductance of 50 mS/mm and an output impedance of 400 Ω.mm are measured at zero gate bias with a gate capacitance of 1.2 pF/mm. The FET has a threshold voltage of -2.4 V, and a saturated drain current of 60 mA/mm at Vgs= 0 V with negligible drift.     

Analytical model of GaAs MESFET's

A simple analytical model of GaAs MESFET's is proposed. The model is based on the assumption that the current saturation in GaAs MESFET's is related to the stationary Gunn domain formation at the drain side of the gate rather than to a pinchoff of the conducting channel under the gate. The saturation current, channel conductance, transconductance, charge under the gate, gate-to-source and drain-togate capacitances, cutoff frequency, characteristic switching time, power-delay product, and breakdown voltage are calculated in the frame of this model. The results are verified by two-dimensional computer calculations. They agree well with the results of the computer analysis and experimental data for a 1-µm gate GaAs MESFET. It is shown that a stray gate-to-drain and gate-to-source capacitance sets up a limitation of a gate length which must be larger than or about 0.1 µm for a GaAs MESFET.     

双栅器件的跨导和漏导

本文将双栅MOSFET考虑成四极器件,以电流连续、电压守恒为基础,讨论了其跨导和漏导特性。所提出的分析求解方法。可推广到任何双栅结构器件。结果表明,此方法不仅简洁、适用性广;而且物理概念清楚,将三极器件和四极器件的特性联系了起来,自然地引出了双栅器件特有的耦合概念。对于所选取的单栅模型,跨导、漏导的计算值和实验值符合良好。     

Microwave power double-heterojunction HEMT's

The RF and dc characteristics of microwave power double-heterojunction HEMt's (DH-HEMT's) with low doping density have been studied. Small-signal RF measurements indicated that the cutoff frequency and the maximum frequency of oscillation in DH-HEMT's with 0.8-1 µm gate length and 1.2 mm gate periphery are typically 11- 16 GHz and 36-41 GHz, respectively. However, the cutoff frequency in DH-HEMT's degrades strongly with increasing drain bias voltage. This may be caused by both effects of increasing effective transit length of electrons and decreasing average electron velocity, due to Gunn domain formation. In large-signal microwave measurement, the DH-HEMT (2.4 mm gate periphery) delivered a maximum output power of 1.05 W with 2.8 dB gain and 0.58 W with 1.6 dB gain at 20 and 30 GHz, respectively. These are the highest output powers yet reported for HEMT devices. For the dc characteristics, the onset of two-terminal gate breakdown voltage is found to correlate with the drain current Idssand recessed length, and three-terminal source-drain breakdown characteristics near pinchoff are limited by the gate-drain breakdown. A simple model on gate breakdown voltage in HEMT is also presented.