A CMOS Batcher and Banyan chip set for B-ISDN packet switching

A Batcher and Banyan chip set suitable for broadband packet switch applications is described. Each chip concurrently processes 32 bit-serial packet channels and is a building block for larger networks. Current chip samples have been tested at channel rates of 170 Mb/s in 1.2-μm double-metal single-poly CMOS for both the Batcher and Banyan chips. Each chip requires a 5-V supply, dissipates approximately 1.5 W, provides 5.44 Gb/s of switching capacity, can process 12.8 million asynchronous transfer mode (ATM) cells per second, and is packaged in an 84-pin leadless ceramic chip carrier (LCCC) for convenient testing. The design and implementation of the switching elements capable of supporting the high-speed bit-serial channels and the chip architectures that accommodate them are described in detail     

DIRSMIN: a fault-tolerant switch for B-ISDN applications usingdilated reduced-stage MIN

We have developed and analyzed a dilated high-performance fault-tolerant fast packet multistage interconnection network (MIN). This new switch, (d,d')-DIRSMIN, uses dilation to improve performance and fault-tolerance of a network. The links at the input and output stages of the dilated banyan-based MIN are rearranged to create multiple routes for each source-destination pair in the network, after removing the first stage in the network. These multiple paths are link- and node-disjoint. This new MIN can provide low packet-loss probability and high reliability with very little hardware overhead, compared to d-dilated banyan networks (BN). Fault tolerance at low latency is achieved by transmitting multiple copies of each input-packet simultaneously using different routes. A multiple-priority scheme allows alternate paths to be explored simultaneously, which results in higher throughput and reliability under both fault-free and faulty conditions. This guarantees that high throughput is maintained even in the presence of a fault. Throughput is analyzed using analytic and simulation methods; this new design has considerably higher performance in the presence of a permanent faulty switching-element (SE) or link, in comparison to dilated networks. Under non-faulty conditions, both analytic and simulation results show that a (d,d)-DIRSMIN performs better than the original dilated BN with the same SE complexity. We analyze the network reliability and show that the new design has superior reliability compared to competing proposals. In particular, this new design is considerably better than the SEN+, the best known thus far     

BCSM SWITCH FOR B-ISDN A NEW HIGH-PERFORMANCE SWITCHING ELEMENT

This paper proposes a new high-performance switching element with the new shared-memory queuing policy, which is called blocked-cell shared-memory (BCSM) queuing. As the name means, instead of buffering all cells through them, the BCSM switching elements only buffer the blocked cells at their input ports. Theoretic analysis results under the uniform traffic model prove that BCSM switching elements have better performance than shared-memory switching elements.     

A fault-tolerant GaAs/CMOS interconnection network for scalablemultiprocessors

The design of an interconnection network (ICN) for a scalable multiprocessor system is presented. The tree-structured network (called SHUNT for scalable hierarchical unidirectional network topology) is organized so that it can be scaled not only in width (through the use of bit slicing), but also in number of ports and in data transfer speed. The network is made from three custom chip types: cluster controller, crossbar switch, and network interface. Implementation of the first prototype chips in 2-μm CMOS is discussed, and the results of detailed circuit simulations for GaAs implementations are given. The network is fault tolerant and is able to detect and correct all single-bit transmission errors. In addition, it can detect failures and reconfigure to work around problems in controllers, port interfaces, or user processors. The network is part of the experimental decoupled computer architect project (DART) currently under study and development     

Supporting applications with network intelligence and B-ISDN

The year 2000 is swiftly approaching and, with all the expectations it brings, many telcos are gearing up to provide telecommunications networks that will satisfy the majority of demands that new feature-rich applications will place upon them. To some people, supporting application requirements for a telecommunications netwrok might mean adding more intelligence to the network. Others may crave to transmit data at faster speeds, communicate more freely on the move, or be able to mix and match the appropriate network infrastructure as they, or their applications, choose to do so. These diverse application requirements are shaping the strategies being pursued by telcos to deliver integrated telecommunications networks for the next millennium. After looking back at some of the developments taking place within the broadband and network intelligence domains, this paper summarises some of the application and service requirements that must be addressed when building future telecommunications networks. From the plethora of technical proposals aimed at developing the necessary environment to fulfil these requirements, this article explores the alternatives. Of course, for all of these alternative routes there will be many questions, technical or otherwise, that yet remain unanswered. Some of these issues will be discussed and various options will be considered to provoke thought or socialise possible solutions.     

A fault-tolerant permutation network modulo arithmetic processor

Conventional fault-tolerant modulo arithmetic processors rely on the properties of a residue number system with L redundant moduli to detect up to L/2 errors. In this paper, we propose a new scheme that combines r-out-of-s residue codes with Berger codes to concurrently detect any number of module errors without any redundant moduli. In addition, this scheme can tolerate L faults if L redundant moduli are used, and has the property of graceful degradation when the number of faulty moduli exceeds L. Finally, it is shown that the added cost for fault tolerance is much less than those were reported earlier in the literature     

A new broadcast switching network

A rearrangeable broadcast switching network is proposed. Under the condition that the number of outlets (customers) is much larger that the number of source inlets (video channels), the network normally has fewer switching nodes than other approaches. The approach is based on the decomposition of the multiconnection function into two subfunction: consecutive spreading and routing. I offers modular construction, easy growth, and an easy path hunt. The network is especially suitable for the directional-coupler photonic-switching technology and an implementation based on this technology is presented. The number of crosspoints required for electronic and photonic implementations is compared     

A management architecture for the international B-ISDN

This paper relates to basic management aspects of the interworking of national?-ISDNX. A general architecture of such an interconnection is proposed which is based on concepts of the worldwide intelligent network (WIN) and CCITT telecommunication management network (TMN). Various models supporting theTMN design are considered. Communication aspects of management information transfer within theTMN are discussed in more detail.     

A self-routing multistage switching network for broadband ISDN

A switching network that approaches a maximum throughput of 100% as buffering is increased is proposed. This self-routing switching network consists of simple 2×2 switching elements, distributors, and buffers located between stages and in the output ports. The proposed switching requires a speedup factor of two. The structure and the operation of the switching network are described, and its performance is analyzed. The switch has log₂N stages that move packets in a store-and-forward fashion, incurring a latency of log₂ N time periods. The performance analysis of the switch under uniform traffic pattern shows that the additional delay is small, and a maximum throughput of 100% is achieved as buffering is increased     

A framework for optical burst switching network design

We analyze optical burst switching (OBS) systems. The analysis leads to a framework which provides guidelines for OBS design. We identify conditions for OBS feasibility and the relationship between burst size, or equivalently burst assembly delay, and throughput, taking into consideration control packet processing and the number of available wavelengths per fiber     

Granulated broadband network applicable to B-ISDN and PSTN services

A granulated broadband network (GBN) is proposed as an intermediate asynchronous transfer mode (ATM) based platform to be part of an evolution scenario toward B-ISDN. The GBN enables various types of services to be provided including 64-kb/s-based services and broadband services. In the GBN, information is transformed into ATM cells at subscriber line terminals or at customer premises and is transferred through ATM networks; consequently, the cost feasibility of a single-channel cell assembly/deassembly device is a significant factor in economically providing ATM-based conventional services and interworking between STM and ATM networks. Various virtual path capacities with a fine degree of granularity can be provided in a mesh structure between transit modes in the GBN. Economic feasibility studies of the GBN, by simulating on certain large-size real networks in the greater Tokyo area, indicate the possibility of a more than 50% cost reduction in transit networks     

B-ISDN

An enhanced ISDN (integrated-services digital network) system that provides the switching and transmission capability for 2-Mb/s and 140-Mb/s channels for dialogue and distribution services is discussed. The main subjects are the transmission modules for subscriber-line and subscriber-premises applications     

A multidimensional framework for congestion control in B-ISDN

A multidimensional approach to congestion control in integrated broadband networks is described, and a framework for a congestion control strategy that is applicable to virtual-circuit-based services as well as connectionless services is developed. The proposed congestion control strategy is based on a set of temporal controls, classification of services is based on their traffic characteristics and quality of service (QOS) requirements, and partitioning of the control space is based on the reaction time of the controls and the network time constants. The congestion control framework is simple, scales as the delay-bandwidth product increases, and is well suited for the asynchronous transfer mode that is being promoted as the underlying transport for B-ISDN     

Traffic management for B-ISDN services

A set of asynchronous transfer mode (ATM) bearer service categories, differentiated in terms of quality of service (QOS), that will support the large spectrum of applications expected in broadband integrated services digital networks (B-ISDN) is defined. The evolution of applications and the traffic requirements in B-ISDN/ATM networks are described, and the evolution of network services to address these requirements is discussed. The definition of ATM bearer service categories necessary for the economical support of initial applications and evolution to future B-ISDN services is proposed. The elements of the ATM traffic management strategy to support these service categories are presented     

欧洲B－ISDN试验网：TRIBUNE

ＴＲＩＢＵＮＥ计划是欧洲先进通信技术研究计划（ＲＡＣＥ）的一部分。此计划的目的是在欧洲为先进的通信业务，特别是宽带综合业务数字网（Ｂ－ＩＳＤＮ），建立公共基础设施。本文将简要介绍该计划的概况。     

New structure for digital switching network

Methods for the design of cost-effective one-stage PCM switching networks composed of digital switching matrices are proposed. These one-stage networks have, in many cases, a more regular structure and contain fewer elements than networks currently known. The proposed one-stage networks can also be used as submodules for multistage networks.<>     

A positively self-feedbacked Hopfield neural network architecture for crossbar switching

We propose a positively self-feedbacked Hopfield neural network architecture for efficiently solving crossbar switch problem. A binary Hopfield neural network architecture with additional positive self-feedbacks and its collective computational properties are studied. It is proved theoretically and confirmed by simulating the randomly generated Hopfield neural network with positive self-feedbacks that the emergent collective properties of the original Hopfield neural network also are present in this network architecture. The network architecture is applied to crossbar switching and results of computer simulations are presented and used to illustrate the computation power of the network architecture. The simulation results show that the Hopfield neural network architecture with positive self-feedbacks is much better than the previous works including the original Hopfield neural network architecture, Troudet's architecture and maximum neural network for crossbar switching in terms of both the computation time and the solution quality.     

A three-sided rearrangeable switching network for a binary fat tree

A binary fat tree needs an internal node to interconnect the left-children, right-children and parent terminals to each other. In this article, we first propose a three-stage, 3-sided rearrangeable switching network for the implementation of a binary fat tree. The main component of this 3-sided switching network (3SSN) consists of a polygonal switch block (PSB) interconnected by crossbars. With the same size and the same number of switches as our 3SSN, a three-stage, 3-sided clique-based switching network is shown to be not rearrangeable. Also, the effects of the rearrangeable structure and the number of terminals on the network switch-efficiency are explored and a proper set of parameters has been determined to minimise the number of switches. We derive that a rearrangeable 3-sided switching network with switches proportional to N ^3/2 is most suitable to interconnect N terminals. Moreover, we propose a new Polygonal Field Programmable Gate Array (PFPGA) that consists of logic blocks interconnected by our 3SSN, such that the logic blocks in this PFPGA can be grouped into clusters to implement different logic functions. Since the programmable switches usually have high resistance and capacitance and occupy a large area, we have to consider the effect of the 3SSN structure and the granularity of its cluster logic blocks on the switch efficiency of PFPGA. Experiments on benchmark circuits show that the switch and speed performances are significantly improved. Based on the experimental results, we can determine the parameters of PFPGA for the VLSI implementation.     

A Two-Level Call Model for IN and B-ISDN Integration

1IntroductionIntelligentNetwork(IN)canofferrapidandflexibleservicedeployment,andhasbeenevolvedtoProvideintelligenttelephoneservicesinpublicnetwork.Ontheotherhand,broadbandconUnwhcahonhasbecomeahotissuetomeetvallousservicesrequirementSinmoderninformationsociety.BroadbandoffersaveryPOwerfuldigitalbearerandfleholembopulationofvallouscounechontypes.AnimportantunderlyingcharacterishcofBroadbandISDN(B-ISDN)signalingistheconceptofseparationofcallandbearerconnechoncontrol.msseparationfeatUreal…