超导加速器低电平系统射频前端设计与实现

设计了中物院太赫兹科研装置超导加速器低电平控制系统的射频前端部分,采用了信号源8663A与直接信号发生器板卡AD9858结合的方案,产生射频前端所需的30.72 MHz中频信号和1330.72 MHz本振信号。采用AD9510时钟板产生ADC和DAC采样所需的频率122.88 MHz和245.76 MHz,采样信号时间抖动仅为4 ps,由此引起的幅值采样误差和相位采样误差分别为±0.04%和±0.025%,符合设计要求。     

An Analytical Approach for Quantifying Clock Jitter Effects in Continuous-Time Sigma–Delta Modulators

Continuous-time sigma–delta modulators (CTSDMs) may suffer severe performance degradation from the timing error in a quantizer clock. We present an analytical approach to quantify the performance loss due to clock jitter in a CTSDM. Unlike many prior works that model the timing error of clocks as additive white Gaussian phase noise, we propose a jitter model that exhibits an auto-regression form, so we term it auto regressive (AR) jitter. This AR jitter model shows exactly the same jitter behavior as that of a clock generated by practical phase-locked loops. Based on this AR jitter model, we establish an analytical approach to examine the intricate effects of clock uncertainty on CTSDM system performance. We demonstrate the validity of the proposed analytical method by showing its excellent agreement with simulation results. The analytical method enables a profound insight into the problem of how clock jitter degrades the system performance and also provides a guideline on how to minimize the detrimental effects of clock jitter.     

Coding, decoding, and recovery of clock synchronization in digital multiplexing system

High-speed broadband digital communication networks rely on digital multiplexing technology where clock synchronization, including processing, transmission, and recovery of the clock, is the critical technique. This paper interprets the process of clock synchronization in multiplexing systems as quantizing and coding the information of clock synchronization, interprets clock justification as timing sigma-delta modulation (T/spl Delta/-/spl Sigma/M), and interprets the jitter of justification as quantization error. As a result, decreasing the quantization error is equivalent to decreasing the jitter of justification. Using this theory, the paper studies the existing jitter-reducing techniques in transmitters and receivers, presents some techniques that can decrease the quantization error (justification jitter) in digital multiplexing systems, and presents a new method of clock recovery.     

Analyzing and modeling the performance degradation of flash A/D converters due to substrate noise coupling

This paper presents a model to evaluate the impact of substrate noise on a CMOS regenerative comparator and moreover to predict the resulting performance degradation of a flash analog-to-digital (A/D) converter. The proposed approach initially relates substrate noise to the induced timing uncertainty of the comparator by means of an analytical linear model. In particular, the analysis first focuses on analyzing and expressing the resulting non-uniform sampling distortion in regenerative comparators in the presence of a deterministic ground bounce. Two sources of distortion are identified and evaluated: the input-dependent and the substrate noise-dependent one. For each error contributor, the analysis investigates two cases of timing error, based on the frequency correlation of the interfering signal with the sampling clock. The properties (number and power of distortion tones) of the sampling error spectrum are found to be highly dependent on the spectral content of the interfering signal and the sampling clock, while the model captures accurately the induced distortion. Subsequently, the linear model is extended to estimate the degradation of flash A/D converters and is utilized to predict the performance of practical flash and time-interleaved converters in the presence of substrate noise.     

Reconstruction of Multidimensional Signals From Irregular Noisy Samples

We focus on a multidimensional field with uncorrelated spectrum and study the quality of the reconstructed signal when the field samples are irregularly spaced and affected by independent and identically distributed noise. More specifically, we apply linear reconstruction techniques and take the mean-square error (MSE) of the field estimate as a metric to evaluate the signal reconstruction quality. We find that the MSE analysis could be carried out by using the closed-form expression of the eigenvalue distribution of the matrix representing the sampling system. Unfortunately, such distribution is still unknown. Thus, we first derive a closed-form expression of the distribution moments, and we find that the eigenvalue distribution tends to the MarČenko–Pastur distribution as the field dimension goes to infinity. Finally, by using our approach, we derive a tight approximation to the MSE of the reconstructed field.      

Over GHz low-power RF clock distribution for a multiprocessordigital system

Conventional interconnections for digital clock distribution pose a severe power consumption problem for GHz clock distribution due to transmission line losses. Therefore, we have proposed an RF clock distribution (RCD) scheme for high-speed digital applications, in particular a multiprocessor system using global clocking. This paper first reports system power and signal integrity analysis results including skew, jitter, impedance mismatch, and noise for RF clock distribution,especially in the GHz range. Based on this analysis, a novel signal integrity design methodology for RF clock distribution systems is proposed. The clock skew created by process parameter variations are modeled and predicted. The system comprises a RF clock transmitter as a clock generator, an H-tree with junction couplers as a clock distributing network and a RF receiver as a digital clock-recovery module. Flip-chip interconnections for the chip-to-substrate assembly and 0.35 μm TSMC CMOS technology for the RF clock receiver are assumed. EMI analysis for 2 GHz 16-node-board-level RF clock distribution networks is conducted using 3D full-wave EM simulation. Finally, the RCD as a low power and high performance clocking method is demonstrated using HP's Advanced Design System (ADS) simulation, considering microwave frequency interconnection models and process parameter variations. In addition, test vehicles for both 2 GHz 16-node and 5 GHz 64-node board-level RF clock distribution networks were implemented and measured using thin, low-loss, and low permittivity Rogers^Lt; RO3003 high-frequency organic substrate     

一种高速A/D转换器时域重构技术研究

A/D转换器在航空航天系统中的重要元器件,随着器件转换时钟频率不断提高而其工作环境不断恶化,如何准确测试其时间参数对于全面评价A/D转换器性能特别重要。目前对于高速A/D转换器时间参数测试,主流方法是通过示波器直接测试其输出,该方法对于示波器采样速度要求比较高。文章提出一种高速A/D转换器时域重构技术,可以通过计算机数字信号处理方法来实现高速A/D转换器时间参数测试,同时避免对示波器采样速度的依赖。同时,在研究高速A/D转换器时域重构技术方法及其应用的基础上,通过了相关试验验证。     

Block-Based Methods for the Reconstruction of Finite-Length Signals From Nonuniform Samples

Two novel block-based algorithms are presented for the reconstruction of uniform samples given the nonuniform samples. The first algorithm uses a sinc interpolator whereas the second one uses a DFT-based interpolator. It is shown that the proposed algorithms are stable and the error due to noise and sampling jitter is bounded by the corresponding error norms of noise and jitter, respectively. We show that both of the block-based algorithms provide nearly perfect reconstruction for a class of practically time and bandlimited signals. Boundary effects are considered and single and multiblock processing is discussed. A modified block-based algorithm is developed by using the windowing technique in order to improve the mean-squared error (MSE) performance for nonbandlimited signals. It is shown that this algorithm performs better than a group of alternative algorithms, including Yen's third algorithm, for a variety of signal, noise, and sampling grids     

A performance analysis of an all-optical clock extraction circuitbased on Fabry-Perot filter

A performance analysis of an optical clock extraction circuit based on a Fabry-Perot filter (FPF) is presented. Two analytical methods, time-domain and frequency-domain analysis, are developed in this paper. Time-domain analysis shows that there is no phase jitter in the extracted optical clock if the free spectral range (FSR) of the FPF is exactly equal to the signal clock frequency. Based on this, we obtain an analytical expression for root mean square (rms) amplitude jitter of the extracted optical clock in time domain, in which we have taken the impacts of carrier frequency drift and carrier phase noise into account. When the FSR of the FPF deviates from the signal clock frequency, both phase jitter and amplitude jitter will occur in the extracted optical clock. In this situation, a more general frequency-domain method is developed to deal with the timing performance under the assumption that carrier phase noise is negligible. This method allows us to calculate both rms phase jitter and rms amplitude jitter of the extracted optical clock. Using the developed two methods, we present a detailed numerical investigation on the impacts of finesse of the FPF, carrier frequency drift, resonator detuning, carrier phase noise, and optical pulse chirp on the timing performance. Finally, the application of this circuit in multiwavelength clock recovery is discussed     

基于FPGA的数字锁相环实现与性能分析

在数字通信系统中,对传输数据的位同步信号提取非常重要.在基于FPGA的数字系统中,通常是设计一个数字锁相环(DPLL)来解决这些问题.文章设计一种新的利用bang-bang鉴相器实现的DPLL,bang-bang鉴相器能直接从接收数据流中提取位时钟信号,且在减少抖动、侪频、时钟恢复和数据同步有很好的优越性.分析了,整个数字锁相环在无高斯白噪声环境下的性能,最后给出了整个锁相环的波形仿真.     

Evaluation of cellular mobile telephone data receivers

Some measurement techniques and results employed to evaluate advanced mobile phone system (AMPS) data receivers being driven by a Rayleigh fading channel are described. These performance measurements were used as a mechanism for comparing the design effectiveness of various bit clock recovery systems. Of five data receiver types evaluated, two models employed a full-wave rectifier in the bit clock recovery system. In this system nominal diode unbalance may cause the derived bit clock to lock 180° from the phase required to properly decode the incoming bit stream. This condition may even occur at high carrier-to-noise ratios when message structures containing long strings of ones or zeros are received. The other data receiver types employed digital signal processing for clock recovery to circumvent this phase ambiguity problem. The performance data of five data receivers are compared to noncoherent frequency-shift keying (FSK) as a model. In most cases, the test results are in good agreement with this model. The performance measurements presented include derived clock jitter and single and average bit error rates as a function of average carrier-to-noise ratios. The implementation of test instrumentation and the interpretation of test results are discussed. The objective is to stress the capability of simulation measurements to evaluate mobile receiver designs in a laboratory environment.     

High-Rate Interpolation of Random Signals From Nonideal Samples

We address the problem of reconstructing a random signal from samples of its filtered version using a given interpolation kernel. In order to reduce the mean squared error (MSE) when using a nonoptimal kernel, we propose a high rate interpolation scheme in which the interpolation grid is finer than the sampling grid. A digital correction system that processes the samples prior to their multiplication with the shifts of the interpolation kernel is developed. This system is constructed such that the reconstructed signal is the linear minimum MSE (LMMSE) estimate of the original signal given its samples. An analytic expression for the MSE as a function of the interpolation rate is provided, which leads to an explicit condition such that the optimal MSE is achieved with the given nonoptimal kernel. Simulations confirm the reduction in MSE with respect to a system with equal sampling and reconstruction rates.      

A DSP-based hearing instrument IC

This paper presents a digital signal processing IC, including AD/DA converters, for one-chip hearing instruments. An on-chip infrared remote control receiver is used to load a program Into the digital signal processor (DSP). The complete IC consumes 2 mW from a single cell battery and operates with supply voltages down to 0.9 V. The oversampling A/D and D/A converters show a dynamic range of 77 and 93 dBA, respectively. Only a few external capacitors are needed. The chip area is 35 mm² in a low-threshold 0.8-μm CMOS process     

Mean-Squared Error Sampling and Reconstruction in the Presence of Noise

One of the main goals of sampling theory is to represent a continuous-time function by a discrete set of samples. Here, we treat the class of sampling problems in which the underlying function can be specified by a finite set of samples. Our problem is to reconstruct the signal from nonideal, noisy samples, which are modeled as the inner products of the signal with a set of sampling vectors, contaminated by noise. To mitigate the effect of the noise and the mismatch between the sampling and reconstruction vectors, the samples are linearly processed prior to reconstruction. Considering a statistical reconstruction framework, we characterize the strategies that are mean-squared error (MSE) admissible, meaning that they are not dominated in terms of MSE by any other linear reconstruction. We also present explicit designs of admissible reconstructions that dominate a given inadmissible method. Adapting several classical estimation approaches to our particular sampling problem, we suggest concrete admissible reconstruction methods and compare their performance. The results are then specialized to the case in which the samples are processed by a digital correction filter     

PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits

A design technique for an over-10-Gb/s clock and data recovery (CDR) IC provides good jitter tolerance and low jitter. To design the CDR using a PLL that includes a decision circuit with a certain phase margin affecting the pull-in performance, we derived a simple expression for the pull-in range of the PLL, which we call the "limited pull-in range," and used it for the pull-in performance evaluation. The method allows us to quickly and easily compare the pull-in performance of a conventional PLL with a full-rate clock and a PLL with a half-rate clock, and we verified that the half-rate PLL is advantageous because of its wider frequency range. For verification of the method, we fabricated a half-rate CDR with a 1:16 DEMUX IC using commercially available Si bipolar technology with f/sub T/=43 GHz. The half-rate clock technique with a linear phase detector, which is adopted to avoid using the binary phase detector often used for half-rate CDR ICs, achieves good jitter characteristics. The CDR IC operates reliably up to over 15 Gb/s and achieves jitter tolerance with wide margins that surpasses the ITU-T specifications. Furthermore, the measured jitter generation is less than 0.4 ps rms, which is much lower than the ITU-T specification. In addition, the CDR IC can extract a precise clock signal under harsh conditions, such as when the bit error rate of input data is around 2/spl times/10/sup -2/ due to a low-power optical input of -24 dBm.     

Sampling Jitter Effect on a Reconfigurable Digital IF Transceiver to WiMAX and HSDPA

This paper outlines the time jitter effect of a sampling clock on a software‐defined radio technology‐based digital intermediate frequency (IF) transceiver for a mobile communication base station. The implemented digital IF transceiver is reconfigurable to high‐speed data packet access (HSDPA) and three bandwidth profiles: 1.75 MHz, 3.5 MHz, and 7 MHz, each incorporating the IEEE 802.16d worldwide interoperability for microwave access (WiMAX) standard. This paper examines the relationship between the signal‐to‐noise ratio (SNR) characteristics of a digital IF transceiver with an under‐sampling scheme and the sampling jitter effect on a multichannel orthogonal frequency‐division multiplexing (OFDM) signal. The simulation and experimental results show that the SNR of the OFDM system with narrower band profiles is more susceptible to sampling clock jitter than systems with relatively wider band profiles. Further, for systems with a comparable bandwidth, HSDPA outperforms WiMAX, for example, a 5 dB error vector magnitude improvement at 15 picoseconds time jitter for a bandwidth of WiMAX 3.5 MHz profile.     

DDS线性调频信号时钟抖动误差分析

直接数字频率合成(DDS)是产生线性调频(LFM)信号常用方法,时钟抖动是影响其信号质量的因素之一.从时域出发,建立了由时钟抖动引起的DDS输出误差模型,推导出了抖动引起的LFM信号信噪比理论预测公式.分析指出随着时钟频率的提高,时钟抖动对信噪比的影响更加明显;当时钟抖动低于10 ps时,信噪比对时钟抖动的变化更为敏感.针对给定的信噪比要求和确知的LFM信号,给出了时钟抖动的限定公式,设计者可据此选择恰当的时钟源.最后,通过实验验证了理论推导的正确性.     

Performance of sigma-delta quantizers in oversampled odd-stacked CMFB systems

In this paper, we investigate the performance of the joint use of odd-stacked cosine modulated filter banks (CMFBs) and the first- and second-order Sigma-Delta (ΣΔ) quantization for communication systems when the signal expansion frame is infinite. This performance is evaluated in terms of the decrease of the reconstruction error of the signal that is jointly represented through the CMFBs and the ΣΔ quantization schemes. To begin with, we derive closed-form expressions of upper-bounds on the signal reconstruction minimum square error (MSE) for both first- and second-order ΣΔ quantization cases. Such upper-bounds are derived irrespectively of any quantization noise assumption that could be made in the considered ΣΔ quantization scheme. Exploiting the obtained upper bound closed-form expressions, we demonstrate that under a set of conditions, this signal reconstruction MSE decays as \(\frac {1}{r^{2}} \) where r denotes the redundancy of the signal expansion frame. The obtained results are shown to be true under the widely used additive white quantization noise assumption, where we determine also explicit analytical signal reconstruction MSE expressions when the CMFBs are combined with first- and second-order quantizers. Simulation results are given to support our claims.     

Jitter requirements of the sampling clock in software radio receivers

The effective number of bits of an analog-to-digital converter (ADC) is not only limited by the quantization step inaccuracy but also by sampling time uncertainty. According to a commonly used model, the error caused by timing jitter, integrated over the whole bandwidth, should not be bigger than the quantization noise, for a full swing input signals at the maximum input frequency. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. However, for a radio receiver not the total integrated error is relevant, but only the error signal in the channel bandwidth. This paper explores the clock jitter requirements for a software radio application, using a more realistic model and taking into account the power spectrum of both the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter requirements are very similar to reciprocal mixing requirements of superheterodyne receivers.     

Short-term frequency stability of clock generators for multigigahertz rapid-single-flux quantum digital circuits

Superconducting digital systems based on Josephson junctions have generally used a synchronous timing strategy. A master clock signal is used to delimit a data window during which the system changes state and data is transferred from one block to the next. The temporal stability of the clock signal has a profound effect on the performance of rapid single flux quantum (RSFQ) digital systems. In particular, short-term clock fluctuations, or clock jitter, can degrade system performance due to the hazard of timing constraint violations. The successful development of large-scale RSFQ digital systems will require highly stable multigigahertz on-chip clock sources. To meet this need, methods for characterizing and measuring the short-term stability of such sources are required. We identify the relevant figure of merit to characterize and compare various clocks: the cycle-to-cycle standard deviation of the clock periods. We present experimental techniques for the measurement of this figure of merit and apply them to the measurement of jitter in a clock generator used often in RSFQ systems, the ring oscillator. High-frequency phase noise measurements found the jitter of a 9.6-GHz clock to be in the range from 0.6% to 0.36% of the clock period. The measured values of clock jitter fell within the 95% confidence interval of our stochastic circuit simulations. This was sufficient evidence to conclude that thermal noise from the resistors in the circuit may be the dominant source of jitter in the ring oscillator.