Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation

Issues related to substrate noise in system-on-chip design are described including the physical phenomena responsible for its creation, coupling transmission mechanisms and media, parameters affecting coupling strength, and its impact on mixed-signal integrated circuits. Design guidelines and best practices to minimize the generation, transmission, and reception of substrate noise are outlined, and different modeling approaches and computer simulation methods used in quantifying the noise coupling phenomena are presented. Finally, experiments that validate the modeling approaches and mitigation techniques are reviewed     

Schematic-Driven Substrate Noise Coupling Analysis in Mixed-Signal IC Designs

This paper presents an approach to reduce substrate cross-talk noise between noisy and sensitive circuitry in mixed-signal integrated circuits at different stages of design and layout development. Silencer! a new, fully automated, schematic-driven substrate noise coupling analysis tool is introduced to accomplish this task. The tool seamlessly enables substrate noise coupling analysis in a standard mixed-signal design flow. Two different methods, fast scalable macro-models and a boundary element solver are integrated into Silencer!. These methods allow extractions of a substrate network from geometric layout information. Simulation results obtained with Silencer! are accurate to within 10% of measured integrated circuits     

混合信号集成电路的衬底耦合噪声分析

本文系统分析了混合信号集成电路的衬底噪声耦合的研究进展.简要分析了衬底噪声的基本机理,及其对混合信号电路的影响,在此基础上分析比较了目前已提出的几种主要的衬底耦合噪声模型.通过分析不同类型衬底内的噪声耦合,介绍了一些电路设计中的去耦方法.最后讨论了衬底耦合噪声研究的发展方向.     

Verification techniques for substrate coupling and theirapplication to mixed-signal IC design

This paper presents techniques for the analysis of substrate-coupled noise in mixed-signal integrated circuits. Advantages and limitations of some commonly employed verification techniques for substrate coupling are outlined. A preprocessed boundary element method introduced in this paper utilizes precomputed z parameters to generate an analytical model for substrate impedance in a preprocessing stage. Truncated series expansions of the analytical impedance model are used to accelerate solution of the resulting boundary element equations. A methodology that applies these fast techniques to the verification of large mixed-signal circuits and results that confirm its efficiency are described. This complete methodology has been applied to the design and verification of an industrial mixed-signal video analog-to-digital converter IC for substrate noise problems     

Cost and performance tradeoff analysis in radio and mixed-signal system-on-package design

An optimal total solution for radio and mixed-signal system integration needs tradeoffs between different design options. Among various design metrics, cost and performance are probably the two most important factors for design decisions. In this paper, we review and analyze cost-performance tradeoffs of system-on-chip (SOC) versus system-on-package (SOP) solutions for radio and mixed-signal applications. A new design methodology, which quantitatively predicts performance and cost gains of SOP versus SOC, is presented. The performance model evaluates various mixed-signal isolation techniques between sensitive analog/RF circuits and noisy digital circuits in SOC or SOP. The cost analysis includes new factors such as extra chip area and additional process steps for mixed-signal isolation, seamless integration of "virtual components" or intellectual property (IP) modules, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip, and extra costs for moving passives off chip. In addition to these, a complete and systematic analysis method for on-chip versus off-chip passives tradeoffs is presented. The analysis and modeling techniques explore tradeoffs between performance, cost, robustness, and yield when different on-chip or off-chip passives are used. It thus provides a complete picture of quantitative tradeoffs for using on-chip or off-chip passives. The design methodology and analysis techniques are then demonstrated through several design examples in wireless applications. It is clearly shown that for all complex and high performance mixed-signal systems, SOP is a lower cost solution than SOC. Finally, some design guidelines for SOC versus SOP and on-chip versus off-chip are concluded.     

Efficient methods for modelling substrate coupling in mixed-signalintegrated circuits

A key problem in the design of large mixed-signal circuits is the noise caused by the coupling of digital signals into the substrate. This paper describes methods that allow circuit designers to model efficiently such substrate noise in large mixed-signal SPICE designs. In the light of these techniques a new methodology is presented for efficiently modelling the substrate noise caused by current injection and its coupling to analogue signals; this is then extended to provide a real-time modelling capability. The practicality and the numerical efficiency of the methods are demonstrated on several prototype example circuits     

混合信号衬底耦合噪声的传播及抑制方法

介绍了衬底噪声耦合效应在不同工艺衬底中的传播,应用medici模拟了不同衬底中,噪声发生端和噪声接收端噪声在不同间距下噪声传播的情况,并从工艺和电路设计两个方面介绍了一系列抑制衬底噪声的方法。     

Computer-aided design of analog and mixed-signal integratedcircuits

This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved     

One-chip wonders

Consumer demand for portable computing and mobile wireless communications will continue to drive development of functionally integrated, ultra-low-power systems on a chip. CMOS bulk processing is likely to emerge as the foundation of mixed-signal, ultra-low-power ICs because of its inherent advantages for low-power logic and flexibility in RF applications. To successfully meet time-to-market goals and shrink product-development cycles, computer-aided design tools must guide a design from conceptualization to physical implementation. Estimates of floorplan arrangement and interconnect and package parasitics are necessary early in the design flow, since these undesirable contributions can dominate over the intrinsic device parasitics     

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter, digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7×8 mm² and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication.     

Substrate coupling in digital circuits in mixed-signal smart-power systems

This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effects created by high-power analog circuits and affecting sensitive digital circuits on the same integrated circuit. The sources and mechanism of the noise behavior of such digital circuits are identified and analyzed. The results are obtained primarily from a set of dedicated test circuits specifically designed, fabricated, and evaluated for this work. The conclusions drawn from the theoretical and experimental analyses are used to develop physical and circuit design techniques to mitigate the substrate noise problems. These results provide insight into the noise immunity of digital circuits with respect to substrate coupling.     

Cost and performance analysis for mixed-signal system implementation: system-on-chip or system-on-package?

Advances in integrated circuits and packaging technologies provided us more implementation options for mixed-signal systems. Emerging technologies are represented by system-on-chip (SoC) and system-on-package (SoP). In order to make a design decision for optimal system implementation, it is hence becoming more and more important to address the cost and performance issues for various implementation options early in a system deign phase. In this paper, we develop a modeling technique for a priori cost and performance estimations for mixed-signal system implementations. The performance model evaluates various noise isolation technologies, such as using guard rings, increasing the separation between digital and analog/RF circuitry parts, using special substrate materials (e.g., silicon-on-insulator), and partitioning the system into several chips. In cost analysis, new factors such as extra chip area and additional process steps due to mixed signal isolation, integration of intellectual property (IP) right module or "virtual components," yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip, are considered. Finally, an efficient computation algorithm, namely COMSI, was developed for cost estimation under various mixed-signal performance constraints. Case studies for SoC and SoP integration are performed using COMSI.     

Efficient parasitic substrate modeling for monolithic mixed-A/D circuit design and verification

Parasitic analog-digital noise coupling has been identified as a key issue facing designers of mixed-signal integrated circuits. In particular, signal crosstalk through the common chip substrate has become increasingly problematic. This paper demonstrates a methodology for developing simulation, synthesis, and verification models to analyze the global electrical behavior of the non-ideal semiconductor substrate. First, a triangular discretization method is employed to generate RC equivalent-circuit substrate models which are far less complex than those formulated by conventional techniques. The networks are then accurately approximated for subsequent analysis by an efficient reduction algorithm which uses a well-conditioned Lanczos moment-matching process. Through congruence transformations, the network admittance matrices are transformed to reduced equivalents which are easily post-processed to derive passive, SPICE-compatible netlist representations of the reduced models. The pure-RC properties of the extracted substrate networks are fully exploited to formulate an efficient overall algorithm. For validation, the strategy has been successfully applied to several mixed-signal circuit examples.     

Single-package integration of RF blocks for a 5 GHz WLANapplication

Transceivers for future digital telecommunications applications (third generation cellular, wireless LAN) need to be portable (compact), battery-powered and wireless. Today's single-chip solutions for RF front-ends do not yield complete system integration. For example, they typically still need external components for impedance matching, for antenna switches, for power amplifiers and for RF bandpass filters (BPFs). Furthermore, problems of substrate coupling (either manifesting as analog crosstalk or as noise coupling from the digital part to the analog part on mixed-signal chip) become more important with increasing integration. A system-in-a-package (SiP) approach can address these problems. High quality components can be integrated in the package, avoiding lower quality on-chip passives or circumventing expensive chip technology adaptations. Virtually all external components can be integrated, as shown in this paper for the case of the bandpass filters and the impedance matching. Even the antenna is a candidate for integration in the package. Further, a clever chip partitioning can reduce the substrate coupling problem. Partitioning also allows using the best IC-technoiogy for each component. This paper reports on a fully integrated single-package RF prototype module for a 5 GHz WLAN receiver front-end, which is intended to demonstrate the concept of SiP integration. The approach, that is illustrated here with prototype RF blocks for a 5 GHz WLAN application, is implemented with a thin film multichip module (MCM-D) interconnect technology. This technology also allows the integration of high quality passive components. With these passives, low-loss filters can be implemented. The use of passives, filters and off-the-shelf, active, bare die components opens the way to successful system integration     

Parasitic modeling and noise mitigation in advanced RF/mixed-signal silicon germanium processes

The potential for highly integrated radio frequency (RF) and mixed-signal (AMS) designs is today very real with the availability cost-effective scaled silicon-germanium (SiGe) process technologies. However, the lack of effective parasitic modeling and noise mitigation significantly restrict opportunities for integration, due to a lack of computer-aided design solutions and practical guidance for designers. This tutorial paper provides a broad in-depth coverage of the key technical areas that designers need to understand in estimating and mitigating IC parasitic effects. A detailed analysis of the parasitic effects in passive devices, the interconnect (including transmission line modeling) and substrate impedance, and isolation estimation is presented-referencing a large number of key publications in these areas.     

Full-wave simulation of electromagnetic coupling effects in RF and mixed-signal ICs using a time-domain finite-element method

This paper describes the computer simulation and modeling of distributed electromagnetic coupling effects in analog and mixed-signal integrated circuits. Distributed electromagnetic coupling effects include magnetic coupling of adjacent interconnects and/or planar spiral inductors, substrate coupling due to stray electric currents in a conductive substrate, and full-wave electromagnetic radiation. These coupling mechanisms are inclusively simulated by solving the full-wave Maxwell's equations using a three-dimensional (3-D) time-domain finite-element method. This simulation approach is quite general and can be used for circuit layouts that include isolation wells, guard rings, and 3-D metallic structures. A state-variable behavioral modeling procedure is used to construct simple linear models that mimic the distributed electromagnetic effects. These state-variable models can easily be incorporated into a VHDL-AMS simulation providing a means to include distributed electromagnetic effects into a circuit simulation.     

一种混合信号集成电路衬底耦合噪声分析方法

讨论分析了混合信号集成电路衬底噪声耦合的机理,及对模拟电路性能的影响。提出了一种混合信号集成电路衬底耦合噪声分析方法,基于TSMC 0.35μm 2P4M CMOS工艺,以14位高速电流舵D/A转换器为例,给出了混合信号集成电路衬底耦合噪声分析方法的仿真结果,并与实际测试结果进行比较,证实了分析方法的可信性。     

Challenges in analog and mixed-signal fault models

The design and testing of mixed-signal integrated circuits have enjoyed a renaissance in recent years. As is customary with past developments, however, design outpaces testing, and the drive to integrate analog and digital circuits on the same chip exacerbates the test problems. This article reviews the recent results in analog fault modeling-a critical area of mixed-signal testing-and describes the coming challenges for both industrial and university researchers     

A programmable microsystem using system-on-chip for real-time biotelemetry

A telemetry microsystem, including multiple sensors, integrated instrumentation and a wireless interface has been implemented. We have employed a methodology akin to that for System-on-Chip microelectronics to design an integrated circuit instrument containing several "intellectual property" blocks that will enable convenient reuse of modules in future projects. The present system was optimized for low-power and included mixed-signal sensor circuits, a programmable digital system, a feedback clock control loop and RF circuits integrated on a 5 mm x 5 mm silicon chip using a 0.6 microm, 3.3 V CMOS process. Undesirable signal coupling between circuit components has been investigated and current injection into sensitive instrumentation nodes was minimized by careful floor-planning. The chip, the sensors, a magnetic induction-based transmitter and two silver oxide cells were packaged into a 36 mm x 12 mm capsule format. A base station was built in order to retrieve the data from the microsystem in real-time. The base station was designed to be adaptive and timing tolerant since the microsystem design was simplified to reduce power consumption and size. The telemetry system was found to have a packet error rate of 10(-3) using an asynchronous simplex link. Trials in animal carcasses were carried out to show that the transmitter was as effective as a conventional RF device whilst consuming less power.