SODEL FET: novel channel and source/drain profile engineering schemes by selective Si epitaxial growth technology

In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the silicon-on-depletion layer FET (SODEL FET), has the depletion layer beneath the channel region, which works as an insulator like a buried oxide in a silicon-on-insulator MOSFET. Thanks to this channel structure, junction capacitance (C/sub j/) has been reduced in SODEL FET, i.e., C/sub j/ (area) was /spl sim/0.73 fF//spl mu/m/sup 2/ both in SODEL nFET and pFET at Vbias =0.0 V. The body effect coefficient /spl gamma/ is also reduced to less than 0.02 V/sup 1/2/. Nevertheless, current drives of 886 /spl mu/A//spl mu/m (I/sub off/=15 nA//spl mu/m) in nFET and -320 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) in pFET have been achieved in 70-nm gate length SODEL CMOS with |V/sub dd/|=1.2 V. New circuit design schemes are also proposed for high-performance and low-power CMOS applications using the combination of SODEL FETs and bulk FETs on the same chip for 90-nm-node generation and beyond.     

Graded base type-II InP/GaAsSb DHBT with f/sub T/=475 GHz

The first demonstration of a type-II InP/GaAsSb double heterojunction bipolar transistor (DHBT) with a compositionally graded InGaAsSb to GaAsSb base layer is presented. A device with a 0.4/spl times/6 /spl mu/m/sup 2/ emitter dimensions achieves peak f/sub T/ of 475 GHz (f/sub MAX/=265 GHz) with current density at peak f/sub T/ exceeding 12 mA//spl mu/m/sup 2/. The structure consists of a 25-nm InGaAsSb/GaAsSb graded base layer and 65-nm InP collector grown by MBE with breakdown voltage /spl sim/4 V which demonstrates the vertical scaling versus breakdown advantage over type-I DHBTs.     

A new metal-ferroelectric (PbZr/sub 0.53/Ti/sub 0.47/O/sub 3/)-insulator (Dy/sub 2/O/sub 3/)-semiconductor (MFIS) FET for nonvolatile memory applications

Metal-ferroelectric-insulator-semiconductor (MFIS) field-effect transistors with Pb(Zr/sub 0.53/,Ti/sub 0.47/)O/sub 3/ ferroelectric layer and dysprosium oxide Dy/sub 2/O/sub 3/ insulator layer were fabricated. The out-diffusion of atoms between Dy/sub 2/O/sub 3/ and silicon was examined by secondary ion mass spectrometry profiles. The size of the memory windows was investigated. The memory windows measured from capacitance-voltage curves of MFIS capacitors and I/sub DS/-V/sub GS/ curves of MFIS transistors are consistent. The nonvolatile operation of MFIS transistors was demonstrated by applying positive/negative writing pulses. A high driving current of 9 /spl mu/A//spl mu/m was obtained even for long-channel devices with a channel length of 20 /spl mu/m. The electron mobility is 181 cm/sup 2//V/spl middot/s. The retention properties of MFIS transistors were also measured.     

Process and Device Performance of Submicrometer-Channel CMOS Devices Using Deep-Trench Isolation and Self-Aligned TiSi/sub 2/ Technologies

According to our scaling study, a deeper n-well allows for a lower n-well surface concentration with improved short-channel effects in submicrometer-channel PMOS-FET's. The deep n-well, however, requires a large space between n- and p-channel devices. This large space limits the integration density in scaled bulk CMOS VLSI's. The deep-trench isolation combined with an epitaxial layer resolves this drawback with significantly improved device-to-device isolation and latchup susceptibility. The 6-/spl mu/m-deep with 2-/spl mu/m-wide deep trench is etched in the epitaxial layer and is refilled with 1500 /spl Aring/ of thermal silicon-dioxide film and 2/spl mu/m of polysilicon film. The sheet resistances of N/sup +/ and P/sup +/ diffusion and N/sup +/ -doped polysilicon layers were reduced to 3 to 4 /spl Omega//spl square/ by using the self-aligned TiSi/sub 2/ layer with an oxide sidewall spacer. As a result of this low sheet resistance, the saturation drain current of submicrometer n- and p-channel MOSFET's was improved approximately 33 to 37 percent compared with conventional MOSFET's without the self-aligned TiSi/sub 2/ layer. The 0.5-/spl mu/m-channel CMOS devices using the deep-trench isolation with an epitaxial layer and the self-aligned TiSi/sub 2/ layer operated at a propagation delay time of 140 ps with a power dissipation of 1.1 mW per inverter and attained a maximum clock frequency of 400 MHz in a static /spl divide/ 4 counter without suffering from Iatchup even at the Iatchup trigger current of 200 mA.     

High-f/sub max/ AlGaAs/InGaAs and AlGaAs/GaAs HBT's with p/sup +//p regrown base contacts

The present paper describes a new approach to fabricating high performance HBT's with low base resistance. Their base contact resistance is reduced by using MOMBE selective growth in the extrinsic base region-a key process in the fabrication of high-f/sub max/ AlGaAs/InGaAs and AlGaAs/GaAs HBT's. A p/sup +//p regrown base structure, which consists of a 40-nm-thick graded InGaAs strained layer and a heavily C-doped regrown contact layer, is used for the AlGaAs/InGaAs HBT's to reduce both their base transit time and base resistance, while preventing aluminum oxide incorporation at the regrowth interface. An h/sub fe/ of 93, an f/sub T/ of 102 GHz, and an f/sub max/ of 224 GHz are achieved for a 1.6-/spl mu/m/spl times/4.6-/spl mu/m HBT, together with reduced base push-out effects and improved reliability. AlGaAs/GaAs HBT's with an 80-nm-thick uniform base layer that have high f/sub max/ values ranging from 140-216 GHz are also fabricated using the selective growth technique. These results confirm the high potential of the proposed HBT's, especially for microwave and millimeter-wave applications.<>     

InGaAs-InP mesa DHBTs with simultaneously high f/sub /spl tau// and f/sub max/ and low C/sub cb//I/sub c/ ratio

We report an InP-InGaAs-InP double heterojunction bipolar transistor (DHBT), fabricated using a conventional triple mesa structure, exhibiting a 370-GHz f/sub /spl tau// and 459-GHz f/sub max/, which is to our knowledge the highest f/sub /spl tau// reported for a mesa InP DHBT-as well as the highest simultaneous f/sub /spl tau// and f/sub max/ for any mesa HBT. The collector semiconductor was undercut to reduce the base-collector capacitance, producing a C/sub cb//I/sub c/ ratio of 0.28 ps/V at V/sub cb/=0.5 V. The V/sub BR,CEO/ is 5.6 V and the devices fail thermally only at >18 mW//spl mu/m/sup 2/, allowing dc bias from J/sub e/=4.8 mA//spl mu/m/sup 2/ at V/sub ce/=3.9 V to J/sub e/=12.5 mA//spl mu/m/sup 2/ at V/sub ce/=1.5 V. The device employs a 30 nm carbon-doped InGaAs base with graded base doping, and an InGaAs-InAlAs superlattice grade in the base-collector junction that contributes to a total depleted collector thickness of 150 nm.     

Long-wavelength In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As large-area avalanche photodiodes and arrays

Large-area (500-/spl mu/m diameter) mesa-structure In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As avalanche photodiodes (APDs) are reported. The dark current density was /spl sim/2.5/spl times/10/sup -2/ nA//spl mu/m/sup 2/ at 90% of breakdown; low surface leakage current density (/spl sim/4.2 pA//spl mu/m) was achieved with wet chemical etching and SiO/sub 2/ passivation. An 18 /spl times/ 18 APD array with uniform distributions of breakdown voltage, dark current, and multiplication gain has also been demonstrated. The APDs in the array achieved 3-dB bandwidth of /spl sim/8 GHz at low gain and a gain-bandwidth product of /spl sim/120 GHz.     

Reliability investigation of 0.07-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel

The authors have investigated the reliability performance of G-band (183 GHz) monolithic microwave integrated circuit (MMIC) amplifiers fabricated using 0.07-/spl mu/m T-gate InGaAs-InAlAs-InP HEMTs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel on 3-in wafers. Life test was performed at two temperatures (T/sub 1/ = 200 /spl deg/C and T/sub 2/ = 215 /spl deg/C), and the amplifiers were stressed at V/sub ds/ of 1 V and I/sub ds/ of 250 mA/mm in a N/sub 2/ ambient. The activation energy is as high as 1.7 eV, achieving a projected median-time-to-failure (MTTF) /spl ap/ 2 /spl times/ 10/sup 6/ h at a junction temperature of 125 /spl deg/C. MTTF was determined by 2-temperature constant current stress using /spl Delta/G/sub mp/ = -20% as the failure criteria. The difference of reliability performance between 0.07-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel and 0.1-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with In/sub 0.6/Ga/sub 0.4/As channel is also discussed. The achieved high-reliability result demonstrates a robust 0.07-/spl mu/m pseudomorphic InGaAs-InAlAs-InP HEMT MMICs production technology for G-band applications.     

Characterization and modeling of AlGaN/GaN MOS capacitor with leakage for large signal transistor modeling

Dual mode AlGaN/GaN metal oxide semiconductor (MOS) heterostructure field-effect transistor (HFET) devices were fabricated and characterized. In HFET mode of operation the devices showed an f/sub t//spl middot/L/sub g/ product of 12GHz/spl middot//spl mu/m at Vgs=-2 V. The AlGaN devices showed formation of an accumulation layer under the gate in forward bias and a f/sub t//spl middot/L/sub g/ product of 6GHz/spl middot//spl mu/m was measured at Vgs=5 V. A novel piecewise small signal model for the gate capacitance of MOS HFET devices is presented and procedures to extract the capacitance in presence of gate leakage are outlined. The model accurately fits measured data from 45MHz to 10GHz over the entire bias range of operation of the device.     

A novel germanium doping method for fabrication of high-performance p-channel poly-Si/sub 1-x/Ge/sub x/ TFT by excimer laser crystallization

In this letter, a novel process for fabricating p-channel poly-Si/sub 1-x/Ge/sub x/ thin-film transistors (TFTs) with high-hole mobility was demonstrated. Germanium (Ge) atoms were incorporated into poly-Si by excimer laser irradiation of a-Si/sub 1-x/Ge/sub x//poly-Si double layer. For small size TFTs, especially when channel width/length (W/L) was less than 2 /spl mu/m/2 /spl mu/m, the hole mobility of poly-Si/sub 1-x/Ge/sub x/ TFTs was superior to that of poly-Si TFTs. It was inferred that the degree of mobility enhancement by Ge incorporation was beyond that of mobility degradation by defect trap generation when TFT size was shrunk to 2 /spl mu/m/2 /spl mu/m. The poly-Si/sub 0.91/Ge/sub 0.09/ TFT exhibited a high-hole mobility of 112 cm/sup 2//V-s, while the hole mobility of the poly-Si counterpart was 73 cm/sup 2//V-s.     

InGaAs/InP DHBTs with 120-nm collector having simultaneously high f/sub /spl tau//, f/sub max//spl ges/450 GHz

InP/In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (DHBT) have been designed for increased bandwidth digital and analog circuits, and fabricated using a conventional mesa structure. These devices exhibit a maximum 450 GHz f/sub /spl tau// and 490 GHz f/sub max/, which is the highest simultaneous f/sub /spl tau// and f/sub max/ for any HBT. The devices have been scaled vertically for reduced electron collector transit time and aggressively scaled laterally to minimize the base-collector capacitance associated with thinner collectors. The dc current gain /spl beta/ is /spl ap/ 40 and V/sub BR,CEO/=3.9 V. The devices operate up to 25 mW//spl mu/m/sup 2/ dissipation (failing at J/sub e/=10 mA//spl mu/m/sup 2/, V/sub ce/=2.5 V, /spl Delta/T/sub failure/=301 K) and there is no evidence of current blocking up to J/sub e//spl ges/12 mA//spl mu/m/sup 2/ at V/sub ce/=2.0 V from the base-collector grade. The devices reported here employ a 30-nm highly doped InGaAs base, and a 120-nm collector containing an InGaAs/InAlAs superlattice grade at the base-collector junction.     

1.3-/spl mu/m InAs quantum-dot laser with high dot density and high uniformity

We realized a triple-stacked 1.3-/spl mu/m InAs quantum dot (QD) with a high density of 2.4/spl times/10/sup 11/ cm/sup -2/ and a high uniformity of below 24 meV that employs an As/sub 2/ source and a gradient composition (GC) strain-reducing layer (SRL) grown on a GaAs substrate. We demonstrated the 1.3-/spl mu/m wavelength emission of this triple-stacked QD laser with a 0.92-mm cavity length and a cleaved facet at room temperature. In addition, we realized the highest maximum modal gain yet reported of 8.1 cm/sup -1/ per QD layer at beyond 1.28 /spl mu/m by using our high-density and high-uniformity QD.     

High-T/sub 0/ strain-compensated InGaAsSb-AlGaAsSb quantum-well lasers emitting at 2.43 /spl mu/m

Strain-compensated InGaAsSb-AlGaAsSb quantum-well (QW) lasers emitting near 2.5 /spl mu/m have been grown by solid-source molecular beam epitaxy. The relatively high arsenic composition causing a tensile strain in the Al/sub 0.25/GaAs/sub 0.08/Sb barriers lowers the valence band edge and the hole energy level, leading to an increased hole confinement and improved laser performance. A 60% external differential efficiency in pulsed mode was achieved for 1000-/spl mu/m-long lasers emitting at 2.43 /spl mu/m. A characteristic temperature T/sub 0/ as high as 163 K and a lasing-wavelength temperature dependence of 1.02 nm//spl deg/C were obtained at room temperature. For 2000 /spl times/ 200 /spl mu/m/sup 2/ broad-area three-QW lasers without lateral current confinement, a low pulsed threshold of 275 A/cm/sup 2/ was measured.     

Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

The authors demonstrate high-performing n-channel transistors with a HfO/sub 2//TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 /spl Aring/, a leakage current of 1.5 A/cm/sup 2/ at V/sub G/=1 V, a peak mobility of 190 cm/sup 2//V/spl middot/s, and a drive-current of 815 /spl mu/A//spl mu/m at an off-state current of 0.1 /spl mu/A//spl mu/m for V/sub DD/=1.2 V. Identical gate stacks processed with a 1000-/spl deg/C spike anneal have a higher peak mobility at 275 cm/sup 2//V/spl middot/s, but a 5-/spl Aring/ higher EOT and a reduced drive current at 610 /spl mu/A//spl mu/m. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 /spl deg/C) for a ten-year lifetime, whereas positive-bias temperature-instability measurements indicate a sufficient lifetime for operating voltages below 0.75 V.     

Efficient PDFA module using high-NA PbF/sub 2//InF/sub 3/-based fluoride fiber

The highest reported single-pass gain coefficient of 0.36 dB/mW has been achieved using a newly developed Pr/sup 3+/-doped high-NA PbF/sub 2//InF/sub 3/-based fluoride fiber, with a /spl Delta/n of 6.6%, a core diameter of 1.2 /spl mu/m and a transmission loss of 250 dB/km at 1.2 /spl mu/m. This fiber was used to construct an efficient PDFA module with a MOPA-LD. A small-signal net gain of 22.5 dB was achieved at 1.30 /spl mu/m with a pump power of 23m mW.     

4H-SiC power bipolar junction transistor with a very low specific ON-resistance of 2.9 m/spl Omega//spl middot/cm/sup 2/

This letter reports a newly achieved best result on the specific ON-resistance (R/sub SP/spl I.bar/ON/) of power 4H-SiC bipolar junction transistors (BJTs). A 4H-SiC BJT based on a 12-/spl mu/m drift layer shows a record-low specific-ON resistance of only 2.9 m/spl Omega//spl middot/cm/sup 2/, with an open-base collector-to-emitter blocking voltage (V/sub ceo/) of 757 V, and a current gain of 18.8. The active area of this 4H-SiC BJT is 0.61 mm/sup 2/, and it has a fully interdigitated design. This high-performance 4H-SiC BJT conducts up to 5.24 A at a forward voltage drop of V/sub CE/=2.5 V, corresponding to a low R/sub SP-ON/ of 2.9 m/spl Omega//spl middot/cm/sup 2/ up to J/sub c/=859 A/cm/sup 2/. This is the lowest specific ON-resistance ever reported for high-power 4H-SiC BJTs.     

Room-temperature self-organised In/sub 0.5/Ga/sub 0.5/As quantum dot laser on silicon

The first room-temperature operation of In/sub 0.5/Ga/sub 0.5/As quantum dot lasers grown directly on Si substrates with a thin (/spl les/2 /spl mu/m) GaAs buffer layer is reported. The devices are characterised by J/sub th//spl sim/1500 A/cm/sup 2/, output power >50 mW, and large T/sub 0/ (244 K) and constant output slope efficiency (/spl ges/0.3 W/A) in the temperature range 5-95/spl deg/C.     

Continuous-wave operation up to 36/spl deg/C of 1.3-/spl mu/m GaInAsP-InP vertical-cavity surface-emitting lasers

We introduced ion-beam assisted deposition in order to improve the quality of Al/sub 2/O/sub 3/ and SiO/sub 2/, which were used as part of the mirrors of 1.3-/spl mu/m GaInAsP-InP vertical-cavity surface-emitting lasers (VCSELs). The refractive index of Al/sub 2/O/sub 3/ was improved to 1.63 from 1.56 and the one of SiO/sub 2/ increased to 1.47 from 1.45. Low-threshold room-temperature continuous-wave (CW) operation of 1.3-/spl mu/m VCSEL with the improved mirrors was demonstrated. The threshold current was 2.4 mA at 20/spl deg/C. The CW operating temperature was raised to 36/spl deg/C, which is a record high temperature for 1.3-/spl mu/m VCSEL.     

AlGaN/GaN/InGaN/GaN DH-HEMTs with an InGaN notch for enhanced carrier confinement

We report an AlGaN/GaN/InGaN/GaN double heterojunction high electron mobility transistors (DH-HEMTs) with high-mobility two-dimensional electron gas (2-DEG) and reduced buffer leakage. The device features a 3-nm thin In/sub x/Ga/sub 1-x/N(x=0.1) layer inserted into the conventional AlGaN/GaN HEMT structure. Assisted by the InGaN layers polarization field that is opposite to that in the AlGaN layer, an additional potential barrier is introduced between the 2-DEG channel and buffer, leading to enhanced carrier confinement and improved buffer isolation. For a sample grown on sapphire substrate with MOCVD-grown GaN buffer, a 2-DEG mobility of around 1300 cm/sup 2//V/spl middot/s and a sheet resistance of 420 /spl Omega//sq were obtained on this new DH-HEMT structure at room temperature. A peak transconductance of 230 mS/mm, a peak current gain cutoff frequency (f/sub T/) of 14.5 GHz, and a peak power gain cutoff frequency (f/sub max/) of 45.4 GHz were achieved on a 1/spl times/100 /spl mu/m device. The off-state source-drain leakage current is as low as /spl sim/5 /spl mu/ A/mm at V/sub DS/=10 V. For the devices on sapphire substrate, maximum power density of 3.4 W/mm and PAE of 41% were obtained at 2 GHz.     

RF noise in 0.18-/spl mu/m and 0.13-/spl mu/m MOSFETs

Studied the gate finger number and gate length dependence on minimum noise figure (NF/sub min/) in deep submicrometer MOSFETs. A lowest NF/sub min/ of 0.93 dB is measured in 0.18-/spl mu/m MOSFET at 5.8 GHz as increasing finger number to 50 fingers, but increases abnormally when above 50. The scaling gate length to 0.13 /spl mu/m shows larger NFmin than the 0.18-/spl mu/m case at the same finger number. From the analysis of a well-calibrated device model, the abnormal finger number dependence is due to the combined effect of reducing gate resistance and increasing substrate loss as increasing finger number. The scaling to 0.13-/spl mu/m MOSFET gives higher NF/sub min/ due to the higher gate resistance and a modified T-gate structure proposed to optimize the NF/sub min/ for further scaling down of the MOSFET.