共查询到19条相似文献,搜索用时 156 毫秒
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针对高频感应加热电源负载参数随时间变化引起固有谐振频率变化,从而导致逆变器偏离最佳工作点,效率降低的现象,提出并实现了一种以集成高速锁相环CD4046为核心,在一台50kW的基于DSP的高频感应加热电源实验样机的基础上,对电源的输出频率进行实时控制,实现逆变器工作频率对负载谐振频率的同步跟踪,并对相关参数和外围电路进行... 相似文献
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高频电源及感应加热技术目前对金属材料加热效率最高、速度最快,且低耗环保。它已经广泛应用于各行各业对金属材料的热加工、热处理、热装配及焊接、熔炼等工艺中。基于DSP的50kW/200KHZ的的高频感应加热电源的硬件设计,系统总体结构以TMS320LF2407A作为主控制芯片进行设计,并通过样机对相关输出情况做跟踪反馈。通过实验证明,该系统输出性能良好,能达到预期效果。 相似文献
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采用基于DSP的数字锁相环(DPLL)对高频逆变电源输出频率的实时控制,可实现逆变器工作频率对负载谐振频率的同步跟踪,确保逆变器开关器件工作在零电压电流软开关(ZVZCS)状态,显著减小功率器件的开关损耗和提高装置效率。文中在给出DSP控制的逆变电源拓扑结构基础上,推出了适用于高频逆变电源的锁相环数学模型,在Z域中对二阶数字锁相环进行了稳定性分析和动态设计。在对锁相环Z域传递函数分析的基础上,得出二阶数字锁相环的稳定条件,并给出数字锁相环的软件实现,最后进行了实验验证。实验结果表明在Z域中对基于DSP的二阶数字锁相环的动态分析和设计是合理可行的。用此方法设计的电源具有良好的动态响应和抗扰性能。 相似文献
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随着电力电子技术的发展,感应加热技术也迅速发展。尤其是数字技术的发展,使感应加热电源的调功技术有了新突破。本文主要对感应加热电源常见的几种调功方武进行比较,并对各种方案的优缺点及适用场合进行了分析。 相似文献
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提出了一种用于DSP的高性能低噪声高速电荷泵锁相环电路。其鉴频鉴相器模块具有高速、无死区等特点;电荷泵模块在提高开关速度的基础上改进了拓扑结构,使充放电电流的路径深度相同,更好地实现了匹配。为了达到宽调谐范围的目的,电荷泵模块采用1.8V电源电压,而压控振荡器模块采用3.3V,这样可充分利用电荷泵的输出电压范围实现宽调谐。电路设计基于0.18μm1P6MCMOS工艺,结果表明,锁相环电路功耗为34mW,中心频率100MHz,频率输出范围50MHz~400MHz,各项性能满足设计指标要求,并使芯片噪声、速度和功耗最优。各模块电路可应用于其他相应的功能电路,对相关领域的设计具有一定的参考意义。 相似文献
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Surge analysis of induction heating power supply with PLL 总被引:12,自引:0,他引:12
Mu-Ping Chen Jan-Ku Chen Murata K. Nakahara M. Harada K. 《Power Electronics, IEEE Transactions on》2001,16(5):702-709
Surges are undesirable with respect to both the reliability and the efficiency of power devices. In this paper, the surge mechanism of an induction heating power supply is studied. First, a modified phase locked loop (PLL) controller is proposed such that the changing resonant frequency of the heated load can be tracked correctly and the zero voltage switching (ZVS) can be reliably maintained simultaneously. Then, a very simple and practical surge model is proposed. Surge analyses for both ZVS and non-ZVS modes are made in sequence. It is found that the extra energy built up in the line inductance during the reverse recovery process of the diodes plays a very important role in generating huge voltages. Finally, some simulation and measured results are provided to verify the validity of the proposed surge model 相似文献
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针对现阶段感应加热领域逐渐数字化的趋势,将DSP芯片应用在感应加热电源的逆变器控制上,以达成频率跟踪与定角控制,从而实现智能控制,使得逆变器的控制与调整更加简单可行。分析了感应加热电源装置的发展趋势及其电源中逆变器的控制要求,设计了基于DSP的并联谐振式感应加热电源中的逆变器的控制主电路,成功实现了频率跟踪和定角控制。 相似文献
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A low power and low phase noise phase-locked loop(PLL) design for low voltage(0.8 V) applications is presented.The voltage controlled oscillator(VCO) operates from a 0.5 V voltage supply,while the other blocks operate from a 0.8 V supply.A differential NMOS-only topology is adopted for the oscillator,a modified precharge topology is applied in the phase-frequency detector(PFD),and a new feedback structure is utilized in the charge pump(CP) for ultra-low voltage applications.The divider adopts the extende... 相似文献
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This paper presents a 10-GHz low spur and low jitter phase-locked loop (PLL).An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs (1 kHz to 10 MHz); the phase noise is -89 and-118.1 dBc/Hz at 10 kHz and 1 MHz frequency offset,respectively; and the reference frequency spur is below -77 dBc.The chip size is 0.32 mm2 and the power consumption is 30.6 mW. 相似文献
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介绍了一种C波段宽带下变频型锁相高速跳频合成器,主要用于雷达及通信领域。该频率合成器采用锁相环(PLL)与外插电路组合的方式,将较高的输出频率迁移到较低频率后送至鉴相器,大大降低N分频器的工作频率,提高了频率合成器的最高输出频率,且输出频率间隔不变,解决了提高合成器输出频率和不降低频率分辨率的矛盾,实现低相位噪声输出。测试结果表明,输出频率4 460 MHz时,在频偏10 kHz处相位噪声为-123 dBc/Hz。采用可控输出的稳压芯片给HMC704LP4供电,通过控制电源的通断,保证HMC704LP4进入正确的工作模式,有效解决了HMC704LP4上电模式选择错误造成的失锁问题。 相似文献
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High frequency electrical power supplies used in many industrial applications have to be able to withstand appreciable variations in load impedance. This paper describes the use of a computer to control a Class-E amplifier power supply which is being developed for high frequency induction and dielectric heating applications. 相似文献
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von Kaenel V. Aebischer D. Piguet C. Dijkstra E. 《Solid-State Circuits, IEEE Journal of》1996,31(11):1715-1722
This paper describes a low-power microprocessor clock generator based upon a phase-locked loop (PLL). This PLL is fully integrated onto a 2.2-million transistors microprocessor in a 0.35-μm triple-metal CMOS process without the need for external components. It operates from a supply voltage down to 1 V at a VCO frequency of 320 MHz. The PLL power consumption is lower than 1.2 mW at 1.35 V for the same frequency. The maximum measured cycle-to-cycle jitter is ±150 ps with a square wave superposed to the supply voltage with a peak-to-peak amplitude of 200 mV and rise/fall time of about 30 ps. The input frequency is 3.68 MHz and the PLL internal frequency ranges from 176 MHz up to 574 MHz, which correspond to a multiplication factor of about 100 相似文献