A 3.3-V/5-V low power TTL-to-CMOS input buffer

A separately self-biased transistor-transistor logic (TTL)-to-CMOS input buffer (SSIB) is proposed. Its logic threshold voltage is kept at 1.4 V when supply voltage is changed from 3.3 V to 5 V, making it suitable for 3.3-V/5-V dual voltage applications. It has low power dissipation, high operating speed, and a logic threshold voltage less sensitive to process and supply voltage variations. The proposed SSIB input buffer was realized in a 0.8-μm single-polysilicon double-metal (SPDM) CMOS technology, The measured logic threshold voltage variations due to process variations are ±24 mV for 5 V supply and ±16 mV for 3.3 V supply, respectively. Its logic threshold voltage variations due to supply voltage variation from 3.3 V to 5 V are within 10 mV. In ring oscillator configuration, the measured delay and power dissipation are 0.45 ns and 0.37 mW for 5-V supply and 0.51 ns and 0.14 mW for 3.3-V supply, respectively     

A low-power rail-to-rail input-range linear delay element circuit

Delay elements are one of the key components in many time-domain circuits such as time-based analog-to-digital converters. In this paper, a new rail-to-rail current-starved delay element is proposed which not only presents good linearity for the voltage-delay curve over the input range of ground to supply voltage, but also it consumes a dynamic power only during the transition times without consuming any static power. The proposed delay element is designed and simulated in a 0.13-µm CMOS technology with a supply voltage of 1.2 V. Post-layout simulation results demonstrate that the proposed circuit has a linear voltage-delay transfer function with a voltage-to-time gain of −1.33 ps/mV. Moreover, when samples of a full-scale sin-wave input signal are applied to the proposed circuit with a clock frequency of 100 MHz, the power consumption is 30 µW, and signal-to-noise-and-distortion ratio (SNDR) of the output delay times is 30.4 dB, making it suitable for use in a time-based analog-to-digital converter with up to 5-bit resolution.     

A 140 mV 0.8μA CMOS voltage reference based on sub-threshold MOSFETs

A CMOS voltage reference circuit based on sub-threshold MOSFETs is proposed,which utilizes a temperature-dependent threshold voltage,a peaking current mirror and sub-threshold technology.The reference has been fabricated in an SMIC 0.13μm CMOS process with only MOS transistors and resistors.The experimental results show a reference voltage variation of 2 mV for a supply voltage ranging from 0.5 to 1.2 V and 0.8 mV for temperatures from -20 to 120℃.The proposed circuit generates a reference voltage of 140 mV and consumes a supply current of 0.8μA at room temperature.The occupied area is only 0.019 mm~2.     

A PVT aware differential delay circuit and its performance variation due to power supply noise

Delay circuits are one of the key components in time domain blocks such as pulse width modulator. This work describes the working of a differential delay circuit under process, voltage and temperature. The proposed design is also coupled to a typical power delivery network (PDN) and a central processing unit (CPU) core ramping current from 0 A to 10–40A in 10 ns Simulated in a 90-nm CMOS technology and power supply voltage (Vdd) of 1.1 V, the post-layout delay was noted to be 227 ps During this time, differential signals at the input are switching at 1GHz while the rise, fall times are about 0.1ns The power thus dissipated corresponds to 235 μW. But, delay changes by about 0.4–0.9 ps at every process corner while temperature increases by 1^OC. The corresponding variation for 1mV drop in power supply voltage is 0.1–0.4ps In addition to that, a change in temperature enables the average power to fluctuate between 192.8 and 264μW, whereas, 0.6μW for 1mV drop in power supply voltage. The study of 500 runs Monte-Carlo analysis for a NN process indicates an almost identical behavior with the no skew data in post-layout. The rms jitter is within 0.01–0.3ps while the delay per mV change in power supply is 0.21 ps/mV. But a sudden current drawn by the CPU causes the voltage V_P close to the die to oscillate. This enables the delay to vary than those obtained with zero power supply noise. The sudden current also introduces jitter in the output swing. The jitter so induced varies linearly with the AC first droop.     

一种低功耗CMOS可编程模拟延时电路

提出了一种基于65 nm CMOS工艺的5位可编程模拟延时电路。采用1.2 V的电源电压和0.01 V的步进控制电压来实现方波输入信号的延时控制。利用Cadence软件对该延时电路进行了性能分析。仿真结果表明,在典型低阈值工艺角下,该延时电路利用5位延时控制信号达到了0.34 ns/LSB的最高延时分辨率和41.47 ns的最长输出延时,实现了对1 kHz~1 MHz范围的数字方波信号的有效延时控制。该延时电路适用于低频数据采集、数据存储等系统。     

一种10-ppm/~oC低压CMOS带隙电压基准源设计

在对传统CMOS带隙电压基准源电路分析和总结的基础上,综合一级温度补偿、电流反馈和电阻二次分压技术,提出了一种10-ppm/oC低压CMOS带隙电压基准源。采用差分放大器作为基准源的负反馈运放,简化了电路的设计,放大器的输出用于产生自身的电流源偏置,提高了电源抑制比(PSRR)。整个电路采用TSMC 0.35mm CMOS工艺实现,采用Hspice进行仿真,仿真结果证明了基准源具有低温度系数和高电源抑制比。     

一种无电阻高电源抑制比的CMOS带隙基准源

提出一种输出低于1V的、无电阻高电源抑制比的CMOS带隙基准源(BGR).该电路适用于片上电源转换器.用HJTC0.18μm CMOS工艺设计并流片实现了该带隙基准源,芯片面积(不包括pad和静电保护电路)为0.031mm2.测试结果表明,采用前调制器结构,带隙基准源电路的输出在100Hz与lkHz处分别获得了-70与-62dB的高电源抑制比.电路输出一个0.5582V的稳定参考电压,当温度在0～85℃范围内变化时,输出电压的变化仅为1.5mV.电源电压VDD在2.4～4V范围内变化时,带隙基准输出电压的变化不超过2mV.     

采用新的抬高源漏工艺技术制作的全耗尽SOI CMOS器件和电路

采用新的工艺技术,成功研制了具有抬高源漏结构的薄膜全耗尽SOI CMOS器件.详细阐述了其中的关键工艺技术.器件具有接近理想的亚阈值特性,nMOSFETs和pMOSFETs的亚阈值斜率分别为65和69mV/dec.采用抬高源漏结构的1.2μm nMOSFETs的饱和电流提高了32%,pMOSFETs的饱和电流提高了24%.在3V工作电压下101级环形振荡器电路的单级门延迟为75ps.     

250 mV Supply Voltage Digital Low‐Dropout Regulator Using Fast Current Tracking Scheme

This paper proposes a 250 mV supply voltage digital low‐dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a 0.11 μm CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over‐voltage and under‐voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at 20 μA to 200 μA load current.     

Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits

The supply voltage to threshold voltage ratio is reduced with each new technology generation. The gate overdrive variation with temperature plays an increasingly important role in determining the speed characteristics of CMOS integrated circuits. The temperature-dependent propagation delay characteristics, as shown in this brief, will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of circuits in a 45-nm CMOS technology is enhanced when the temperature is increased at the nominal supply voltage. Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable operation under temperature fluctuations. A design methodology based on optimizing the supply voltage for temperature-variation-insensitive circuit performance is proposed in this brief. The optimum supply voltage is 45% to 53% lower than the nominal supply voltage in a 180-nm CMOS technology. Alternatively, the optimum supply voltage is 15% to 35% higher than the nominal supply voltage in a 45-nm CMOS technology. The speed and energy tradeoffs in the supply voltage optimization technique are also presented     

衬底驱动超低压CMOS带隙基准电压源

采用二阶温度补偿和电流反馈技术,设计实现了一种基于衬底驱动技术和电阻分压技术的超低压CMOS带隙基准电压源。采用衬底驱动超低压运算放大器作为基准源的负反馈,使其输出用于产生自身的电流源偏置,其电源抑制比(PSRR)为-63.8dB。采用Hspice仿真,在0.9V电源电压下,输出基准电压为572.45mV,温度系数为13.3ppm/°C。在0.8~1.4V电源电压范围内,输出基准电压变化3.5mV。基于TSMC0.25μm2P5MCMOS工艺实现的衬底驱动带隙基准电压源的版图面积为203μm×478.1μm。     

High-performance CMOS circuits fabricated by excimer-laser-annealedpoly-Si TFTs on glass substrates

High-performance CMOS circuits are fabricated from excimer-laser-annealed poly-Si TFTs on a glass substrate (300×300 mm). The propagation delay time of the 121 stage CMOS ring oscillators with 0.5 μm gate length is 0.18 nsec at 5 V supply voltage. The maximum operating frequency of the 40-stage shift registers with 1 μm gate length is 133 MHz at 5 V supply voltage. This value is high enough for peripheral CMOS circuits with line-at-a-time addressing     

High-Precision Differential-Input Buffered and External Transconductance Amplifier for Low-Voltage Low-Power Applications

Recently, the demand for low-voltage low-power integrated circuits design has grown dramatically. For battery-operated devices both the supply voltage and the power consumption have to be lowered in order to prolong the battery life. This paper presents an attractive approach to designing a low-voltage low-power high-precision differential-input buffered and external transconductance amplifier, DBeTA, based on the bulk-driven technique. The proposed DBeTA possesses rail-to-rail voltage swing capability at a low supply voltage of ±400 mV and consumes merely 62 μW. The proposed circuit is a universal active element that offers more freedom during the design of current-, voltage-, or mixed-mode applications. The proposed circuit is particularly interesting for biomedical applications requiring low-voltage low-power operation capability where the processing signal frequency is limited to a few kilohertz. An oscillator circuit employing a minimum number of active and passive components has been described in this paper as one of many possible applications. The circuit contains only a single active element DBeTA, two capacitors, and one resistor, which is very attractive for integrated circuit implementation. PSpice simulation results using the 0.18 μm CMOS technology from TSMC are included to prove the unique results.     

Yield and speed optimization of a latch-type voltage sense amplifier

A quantitative yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It investigates the impact of supply voltage, input DC level, transistor sizing, and temperature on the input offset voltage. The input DC level turns out to be most significant. Also, an analytical expression for the sensing delay is derived which shows low sensitivity on the input DC bias voltage. A figure of merit indicates that an input dc level of 0.7 V/sub DD/ is optimal regarding speed and yield. Experimental results in 130-nm CMOS technology confirm that the yield can be significantly improved by lowering the input DC voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19 to 8.5 mV without affecting the delay.     

New Curvature-Compensated CMOS Bandgap Voltage Reference

A novel curvature-compensated CMOS bandgap voltage reference is presented. The reference utilizes two first order temperature compensations generated from the nonlinearity of the finite current gain β of vertical pnp bipolar transistor. The proposed circuit, designed in a standard 0.18 μm CMOS process, achieves a good temperature coefficient of 2.44 ppm/℃ with temperature range from --40℃ to 85 ℃, and about 4 mV supply voltage variation in the range from 1.4 V to 2.4 V. With a 1.8 V supply voltage, the power supply rejection ratio is -56dB at 10MHz.     

22–29 GHz Ultra-Wideband CMOS Pulse Generator for Short-Range Radar Applications

The pseudo-millimeter-wave ultra-wideband (UWB) is attractive for applications in short-range automotive radar systems using 22 to 29 GHz in order to realize road safety and intelligent transportation. Although the CMOS is suitable for short- range radar since processing units can be implemented in the same chip as the UWB front-end building block, it is difficult to operate CMOS pulse generators at such a high frequency. To realize the pseudo-millimeter-wave band using CMOS, we have proposed a new pulse generator consisting of a series of delay cells and edge combiners with waveform shaping for short-range radar. As a result of measurement using 90-nm CMOS technology, 1 Gb/s/bit pulses with 71 mV peak-to-peak, 39.2 ps monopulse width and 552 ps envelope width are successfully generated with a power consumption of 1.4 mW at a supply voltage of 0.91 V. This result can be the basis for developing the key technology for one-chip short-range radar sensors.     

A low-voltage low-power threshold voltage monitor for CMOS process sensing

In this paper a low-voltage low-power threshold voltage monitor for CMOS process sensing is presented. This circuit works in weak inversion and it can be used as an elementary circuit block for on-chip compensation of the intra-die or inter-die threshold voltage variations in low-power analog and mixed-signal SoC, since it is robust to temperature and power supply voltage variations (similar to the bandgap voltage reference). The proposed threshold voltage monitor has been successfully verified in a standard 0.35-μm n-well CMOS TSMC process. Experimental results have confirmed that the circuit generates an average reference voltage of 758 mV (very close to the typical threshold voltage when extrapolated to absolute zero) for a 950 mV power supply voltage, with a variation of 39 ppm/°C for the −20 to 80°C temperature range.     

New Curvature-Compensation Technique for CMOS Bandgap Reference With Sub-1-V Operation

A new sub-1-V curvature-compensated CMOS bandgap reference, which utilizes the temperature-dependent currents generated from the parasitic n-p-n and p-n-p bipolar junction transistor devices in the CMOS process, is presented. The new proposed sub-1-V curvature-compensated CMOS bandgap reference has been successfully verified in a standard 0.25-$muhboxm$CMOS process. The experimental results have confirmed that, with the minimum supply voltage of 0.9 V, the output reference voltage at 536 mV has a temperature coefficient of 19.5$hboxppm/^circhboxC$from 0$^circhboxC$to 100$~^circhboxC$. With a 0.9-V supply voltage, the measured power noise rejection ratio is$-hbox25.5~hboxdB$at 10 kHz.     

薄膜积累型SOI pMOSFET

对薄膜积累型SOI pMOSFET的制备和特性进行了研究.把一些特性和反掺杂型SOI pMOSFET进行了比较.其亚阈值斜率只有69mV/decade,而且几乎没有DIBL效应.漏击穿电压为10.5V,与反掺杂型相比,提高了40%.饱和电流为130μA/μm,比反掺杂型提高了27%以上.在3V工作电压下,101级SOI CMOS环形振荡器的单级门延迟为56ps.     

A novel precision curvature-compensated bandgap reference

A high precision high-order curvature-compensated bandgap reference compatible with the standard CMOS process, which uses a compensation proportional to V_TlnT realized by utilizing voltage to current converters and the voltage current characteristics of a base-emitter junction, is presented. Experiment results of the proposed bandgap reference implemented with the CSMC 0.5-μm CMOS process demonstrate that a temperature coefficient of 3.9 ppm/℃ is realized at 3.6 V power supply, a power supply rejection ratio of 72 dB is achieved, and the line regulation is better than 0.304 mV/V dissipating a maximum supply current of 42μA.