Electrical characteristics of high quality La2O3 gate dielectric with equivalent oxide thickness of 5 Å

Electrical and reliability properties of ultrathin La₂O ₃ gate dielectric have been investigated. The measured capacitance of 33 Å La₂O₃ gate dielectric is 7.2 μF/cm² that gives an effective K value of 27 and an equivalent oxide thickness of 4.8 Å. Good dielectric integrity is evidenced from the low leakage current density of 0.06 A/cm² at -1 V, high effective breakdown field of 13.5 MV/cm, low interface-trap density of 3×10¹⁰ eV^-1/cm², and excellent reliability with more than 10 years lifetime even at 2 V bias. In addition to high K, these dielectric properties are very close to conventional thermal SiO₂      

Electrical characteristics of highly reliable ultrathin hafniumoxide gate dielectric

Electrical and reliability properties of ultrathin HfO₂ have been investigated. Pt electroded MOS capacitors with HfO₂ gate dielectric (physical thickness ~45-135 Å and equivalent oxide thickness ~13.5-25 Å) were fabricated. HfO₂ was deposited using reactive sputtering of a Hf target with O₂ modulation technique. The leakage current of the 45 Å HfO₂ sample was about 1×10^-4 A/cm ² at +1.0 V with a breakdown field ~8.5 MV/cm. Hysteresis was <100 mV after 500°C annealing in N₂ ambient and there was no significant frequency dispersion of capacitance (<1%/dec.). It was also found that HfO₂ exhibits negligible charge trapping and excellent TDDB characteristics with more than ten years lifetime even at V_DD=2.0 V     

High-Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1 A/mm

High-performance inversion-type enhancement- mode (E-mode) n-channel In_0.65Ga_0.35As MOSFETs with atomic-layer-deposited Al₂O₃ as gate dielectric are demonstrated. A 0.4-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 10 nm shows a gate leakage current that is less than 5 times 10^-6 A/cm² at 4.0-V gate bias, a threshold voltage of 0.4 V, a maximum drain current of 1.05 A/mm, and a transconductance of 350 mS/mm at drain voltage of 2.0 V. The maximum drain current and transconductance scale linearly from 40 mum to 0.7 mum. The peak effective mobility is ~1550 cm²/V ldr s at 0.3 MV/cm and decreases to ~650 cm²/V ldr s at 0.9 MV/cm. The obtained maximum drain current and transconductance are all record-high values in 40 years of E-mode III-V MOSFET research.     

Accumulation gate capacitance of MOS devices with ultrathin high-/spl kappa/ gate dielectrics: modeling and characterization

A quantum-mechanical (QM) model is presented for accumulation gate capacitance of MOS structures with high-/spl kappa/ gate dielectrics. The model incorporates effects due to penetration of wave functions of accumulation carriers into the gate dielectric. Excellent agreement is obtained between simulation and experimental C-V data. It is found that the slope of the C-V curves in weak and moderate accumulation as well as gate capacitance in strong accumulation varies from one dielectric material to another. Inclusion of penetration effect is essential to accurately describe this behavior. The physically based calculation shows that the relationship between the accumulation semiconductor capacitance and Si surface potential may be approximated by a linear function in moderate accumulation. Using this relationship, a simple technique to extract dielectric capacitance for high-/spl kappa/ gate dielectrics is proposed. The accuracy of the technique is verified by successfully applying the method to a number of different simulated and experimental C-V characteristics. The proposed technique is also compared with another method available in the literature. The improvements made in the proposed technique by properly incorporating QM and other physical effects are clearly demonstrated.     

High-κ Al2O3−HfTiO Nanolaminates With Less Than 0.8-nm Equivalent Oxide Thickness

High quality nanolaminate stacks consisting of five Al₂O₃-HfTiO layers with an effective dielectric constant of about 22.5 are reported. A dielectric constant for binary HfTiO thick films of about 83 was also demonstrated. The electrical characteristics of as-deposited structures and ones which were annealed in an O₂ atmosphere at up to 950 degC for 5-10 min were investigated. Two types of gate electrodes: Pt and Ti were compared. The dielectric stack which was annealed up to 500 degC exhibits a leakage current density as small as ~1times10^-4 A/cm² at an electric of field 1.5 MV/cm for a quantum-mechanical corrected equivalent oxide thickness of ~0.76 nm. These values change to ~1times10^-8 A/cm² and 1.82 nm, respectively, after annealing at 950 degC     

The effect of 1300-1380°C anneal temperatures and materialcontamination on the characteristics of CMOS/SIMOX devices

The characteristics of CMOS transistors fabrication on silicon implanted with oxygen (SIMOX) materials were measured as a function of the silicon superficial layer contamination levels. In addition, postimplant anneal temperatures of 1300°C, 1350°C, and 1380°C were examined. It is found that the transistor leakage currents as well as the integrity of the gate oxide and implanted SIMOX oxide are functions of the carbon content in the starting material. Leakage currents below 1.0×10^-12 A/μm of channel width have been measured when the carbon concentration is reduced to 2×10¹⁸/cm². In addition, the integrity of the transistor gate dielectric, SIMOX implanted oxide, and oxygen precipitate density are seen to be a function of the postimplant anneal temperature. A gate dielectric breakdown field of 10 MV/cm has been achieved when the postimplant temperature is increased to 1380°C     

Electrical conduction and dielectric breakdown in aluminum oxideinsulators on silicon

Leakage currents and dielectric breakdown were studied in MIS capacitors of metal-aluminum oxide-silicon. The aluminum oxide was produced by thermally oxidizing AlN at 800-1160°C under dry O₂ conditions. The AlN films were deposited by RF magnetron sputtering on p-type Si (100) substrates. Thermal oxidation produced Al ₂O₃ with a thickness and structure that depended on the process time and temperature. The MIS capacitors exhibited the charge regimes of accumulation, depletion, and inversion on the Si semiconductor surface. The best electrical properties were obtained when all of the AlN was fully oxidized to Al₂O₃ with no residual AlN. The MIS flatband voltage was near 0 V, the net oxide trapped charge density, Q_0x, was less than 10¹¹ cm ^-2, and the interface trap density, D_it, was less than 10¹¹ cm^-2 eV^-1, At an oxide electric field of 0.3 MV/cm, the leakage current density was less than 10^-7 A cm^-2, with a resistivity greater than 10 ¹² Ω-cm. The critical field for dielectric breakdown ranged from 4 to 5 MV/cm. The temperature dependence of the current versus electric field indicated that the conduction mechanism was Frenkel-Poole emission, which has the property that higher temperatures reduce the current. This may be important for the reliability of circuits operating under extreme conditions. The dielectric constant ranged from 3 to 9. The excellent electronic quality of aluminum oxide may be attractive for field effect transistor applications     

Deposition of uniform Zr-Sn-Ti-O films by on-axis reactivesputtering

We describe the deposition of amorphous Zr-Sn-Ti-O (aZTT) dielectric thin films using conventional on-axis reactive sputtering. Thin films of composition Zr_0.2Sn_0.2Ti_0.6 O₂ have excellent dielectric properties: 40-50-nm thick films with a dielectric constant of 50-70 were obtained, depending on the processing conditions, yielding a specific capacitance of 9-17 fF/μm². Breakdown fields were measured to be 3-5 MV/cm, yielding a figure of merit εε₀E_br=15-30 μC/cm², up to eightfold higher than conventional deposited SiO₂. Leakage currents, measured at 1.0 MV/cm, were in the range 10^-9-10^-7 A/cm². This material appears well-suited for use in Si-IC device technology, for example as storage capacitors in DRAM     

Investigation of inductively coupled plasma gate oxide on lowtemperature polycrystalline-silicon TFTs

By optimizing the inductively coupled plasma (ICP) oxidation condition, a thin oxide of 10 nm has been grown at 350°C to achieve excellent gate oxide integrity of low leakage current<5×10^-8 A/cm² (at 8 MV/cm), high breakdown field of 9.3 MV/cm and low interface trap density of 1.5×10¹¹ /eV cm². The superior performance poly-Si TFTs using such a thin ICP oxide were attained to achieve a high ON current of 110 μA/μm at V_D=1 V and V_G=5 V and the high electron field effect mobility of 231 cm²/V·S     

Oxidized Ta2O5/Si3N4dielectric films on poly-crystalline Si for dRAMs

A dielectric film technology characterized by a novel multilayer structure formed by oxidation of Ta₂O₅/Si₃ N₄ films on polysilicon has been developed to realize high-density dRAMs. The dry oxidation of the Ta₂O₅/Si₃N₄ layers was performed at temperatures higher than 900°C. This film has a capacitance per unit area from 5.5 to 6.0 fF/ μm², which is equivalent to that of a 6.0- to 6.5-nm-thick SiO₂. The leakage current at an effective electric field of 5 MV/cm is less than 10^-9 A/cm². Under such an electric field, the extrapolated time to failure for 50% cumulative failure can be as high as 1000 years     

High-voltage accumulation-layer UMOSFET's in 4H-SiC

A novel silicon carbide UMOSFET structure is reported. This device incorporates two new features: a self-aligned p-type implantation in the bottom of the trench that reduces the electric field in the trench oxide, and an n-type epilayer under the p-base to promote lateral current spreading into the drift region. This UMOS structure is capable of supporting the full blocking voltage of the pn junction while keeping the electric field in the gate oxide below 4 MV/cm. An accumulation channel is formed on the sidewalls of the trench by epigrowth, and the gate oxide is produced by a polysilicon oxidation process, resulting in a uniform oxide thickness over both the sidewalls and bottom of the trench. The fabricated 4H-SiC devices have a blocking voltage of 1400 V (10 μm drift region), a specific on-resistance of 15.7 mΩ-cm ² at room temperature, and a gate oxide field of 3 MV/cm     

具有栅介质电场屏蔽作用的新型GaN纵向槽栅MOSFET器件设计

基于氮化镓(GaN)等宽禁带(WBG)半导体的金氧半场效应晶体管(MOSFET)器件在关态耐压下,栅介质中存在与宽禁带半导体临界击穿电场相当的大电场,致使栅介质在长期可靠性方面受到挑战。为了避免在GaN器件中使用尚不成熟的p型离子注入技术,提出了一种基于选择区域外延技术制备的新型GaN纵向槽栅MOSFET,可通过降低关态栅介质电场来提高栅介质可靠性。提出了关态下的耗尽区结电容空间电荷竞争模型,定性解释了栅介质电场p型屏蔽结构的结构参数对栅介质电场的影响规律及机理,并通过权衡器件性能与可靠性的关系,得到击穿电压为1 200 V、栅介质电场仅0.8 MV/cm的具有栅介质长期可靠性的新型GaN纵向槽栅MOSFET。     

High Mobility Strained Ge pMOSFETs With High-κ/Metal Gate

Compressively strained Ge long channel ring-type pMOSFETs with high-kappa Si/SiO₂/HfO₂/TiN gate stacks are fabricated on Si_0.2Ge_0.8 virtual substrates. Effective oxide thickness is approximately 1.4 nm with low gate leakage current. A peak hole mobility of 640 cm²/ Vldrs and up to a four times enhancement over the Si/SiO₂ universal curve are observed. Parasitic conduction within the Si-cap layers degrades the mobility at large vertical fields, although up to a 2.5 times enhancement over universal remains at a field of 0.9 MV/cm.     

Improved Ge Surface Passivation With Ultrathin SiOX Enabling High-Mobility Surface Channel pMOSFETs Featuring a HfSiO/WN Gate Stack

To realize high-mobility surface channel pMOSFETs on Ge, a 1.6-nm-thick SiO_X passivation layer between the bulk Ge substrate and HfSiO gate dielectric was introduced. This approach provides a simple alternative to epitaxial Si deposition followed by selective oxidation and leads to one of the highest peak hole mobilities reported for unstrained surface channel pMOSFETs on Ge: 332 cm² middotV^-1middots^-1 at 0.05 MV/cm-a 2times enhancement over the universal Si/SiO₂ mobility. The devices show well-behaved output and transfer characteristics, an equivalent oxide thickness of 1.85 nm and an I_ON/I_OFF ratio of 3times10³ without detectable fast transient charging. The high hole mobility of these devices is attributed to adequate passivation of the Ge surface     

A new model of gate capacitance as a simple tool to extract MOSparameters

This paper tackles the difficult task to extract MOS parameters by a new model of the gate capacitance that takes into account both poly-Si depletion and charge quantization and includes temperature effects. A new fast and iterative procedure, based on this simplified self-consistent model, will be presented to estimate simultaneously the main MOS system parameters (oxide thickness, substrate, and poly-Si doping) and oxide field, surface potentials at the Si/SiO₂ and at the poly-Si/SiO₂ interfaces. Its effectiveness will be demonstrated by comparing oxide field and oxide thickness to those extracted by other methods proposed in the literature. Moreover, these methods are critically reviewed and we suggest improvements to reduce their errors. The agreement between CV simulation and experimental data is good without the need of any free parameter to improve the fitting quality for several gate and substrate materials combinations. Finally, a simple law to estimate substrate and poly-Si doping in n⁺/n ⁺ MOS capacitors from CV curves is proposed     

High-Work-Function Ir/HfLaO ${rm p}$-MOSFETs Using Low-Temperature-Processed Shallow Junction

We report a high effective work function (Phi_m-eff) and a very low Vt Ir gate on HfLaO p-MOSFETs using novel self-aligned low-temperature shallow junctions. This gate-first process has shallow junctions of 9.6 or 20 nm that are formed by solid phase diffusion using SiO₂-covered Ga or Ni/Ga. At 1.2-nm effective oxide thickness, good Phi_m-eff of 5.3 eV, low V_t of +0.05 V, high mobility of 90 cm²/V-s at -0.3 MV/cm, and small 85degC negative bias-temperature instability (NBTI) of 20 mV (10 MV/cm for 1 h) are measured for Ir/HfLaO p-MOSFETs.     

Conduction mechanisms in barium tantalates films and modificationof interfacial barrier height

The leakage current-voltage characteristics of rf-magnetron sputtered BaTa₂O₆ film in a capacitor with the top aluminum and the bottom indium-tin-oxide electrodes have been investigated as a function of applied field and temperature. In order to study the effect of the surface treatment on the electrical characteristics of as-deposited film we performed an oxygen plasma treatment on BaTa₂O₆ surface. The dc current-voltage, bipolar pulse charge-voltage, dc current-time, and small ac signal capacitance-frequency characteristics were measured to study the electrical and the dielectric properties of BaTa₂O ₆ thin film. All of the BaTa₂O₆ films in this study exhibited a low leakage current, a high breakdown field strength (3-4.5 MV/cm), and a high dielectric constant (20-30). From the temperature dependence of the leakage current, we could conclude that the dominant conduction mechanism under high electrical fields (>1 MV/cm) is ascribed to the Schottky emission while the ohmic conduction is dominant at low electrical fields (<1 MV/cm). Furthermore, the oxygen plasma treatment on the surface of as-deposited BaTa₂O ₆ resulted in a lowering of the interface barrier height and thus, a reduction of the leakage current at Al under a negative bias. This can be explained by the formation of Ba-rich metallic layer by surface etching effect and by filling the oxygen vacancies in the bulk     

Carrier mobility in MOSFETs fabricated with Hf-Si-O-N gate dielectric, polysilicon gate electrode, and self-aligned source and drain

A study of electron and hole mobilities for MOSFET devices fabricated with Hf-Si-O-N gate dielectric, polysilicon gate electrodes and self-aligned source and drain is presented. High effective electron and hole mobilities, 250 cm/sup 2//V/spl middot/s and 70 cm/sup 2//V/spl middot/s, respectively, were measured at high effective field (>0.5 MV/cm). The NMOSFETs have an equivalent oxide thickness (EOT) of 1.3 nm and the PMOSFETs have an EOT of 1.5 nm. The effect of interface engineering on the electron and hole mobilities is discussed.     

Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited Al2O3 as Gate Dielectric

High-performance inversion-type enhancement-mode n-channel In_0.53Ga_0.47As MOSFETs with atomic-layer-deposited (ALD) Al₂O₃ as gate dielectric are demonstrated. The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors in general. A 0.5-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 8 nm shows a gate leakage current less than 10^-4 A/cm² at 3-V gate bias, a threshold voltage of 0.25 V, a maximum drain current of 367 mA/mm, and a transconductance of 130 mS/mm at drain voltage of 2 V. The midgap interface trap density of regrown Al₂O₃ on In_0.53Ga_0.47As is ~1.4 x 10¹²/cm² ldr eV which is determined by low-and high-frequency capacitance-voltage method. The peak effective mobility is ~1100 cm² / V ldr s from dc measurement, ~2200 cm²/ V ldr s after interface trap correction, and with about a factor of two to three higher than Si universal mobility in the range of 0.5-1.0-MV/cm effective electric field.     

Room-Temperature Deposited Titanium Silicate Thin Films for MIM Capacitor Applications

High-k titanium silicate (i.e., TiSiO₄) thin films of various thicknesses (in the 4.5- to 160-nm range) were successfully deposited by means of a sputter deposition process at room-temperature and integrated into metal-insulator-metal (MIM) capacitors. It is shown that the TiSiO₄-based capacitors can exhibit a capacitance density as high as 30 fF/mum² while maintaining low dielectric dispersion and losses. An excellent voltage linearity was also obtained ( alpha~600 ppm/V² at 8.2 fF/mum²) together with a high dielectric constant of 16.5 and low leakage current of about 10 nA/cm² at 1 MV/cm. Our results thus show that TiSiO₄ films constitute a very promising approach for the achievement of high performance MIM capacitors