4-µm LSI on SOS using coplanar-II process

SOS Si-gate 4-µm NMOS devices using a coplanar process (Coplanar-II process) have been investigated for the purpose of improving thé power-delay product and SOS LSI reliability. The gate breakdown field is improved by more than a factor of two (8.7 MV/cm) over that of transistors fabricated by a conventional SOS process. Two types of anomalous drain leakage currents which flow along the edge of the silicon island formed by using the conventional SOS process are suppressed. A typical drain leakage current is7 times 10^{-11}A/8 µm. The typical values of speed and power-delay product are 0.70 ns and 0.21 pJ for 4-µm channel length devices and 0.57 ns and 0.17 pJ for 3-µm devices. These values are 1.6 times faster than that of MOS/bulk due to a lack of stray capacitance in MOS/SOS. The temperature dependence of the delay time in NMOS/SOS E/D devices can be minimized by choosing the load transistor threshold voltage (VTD) to be -2.1 V. This is attributed to the higher temperature dependence of VTDthan that of MOS/bulk. The Coplanar-II process with Si-gate 4-µm NMOS/SOS is successfully applied to the fabrication of a 1300-gate LSI, RF0 (Register File 0). The circuitry has a unique register port which can be addressed from two independent ports simultaneously. In order to obtain higher speed and lower power, four kinds of threshold voltages are used. The circuits give rise to stable operation without any timing pulse such as a precharge and a higher internal access time of 25 ns in RF0, which consists of 256-bit memory and peripheral control circuit.     

Characteristics of a 1.2-µm CMOS technology fabricated on an RF-heated zone-melting recrystallized SOI

0.7-5-µm CMOSFET's were fabricated on SOI which was recrystallized using an RF-heated zone-melting recrystallization (RFZMR) method. The leakage currents of n-channel MOSFET's having gate lengths between 5- and 0.7-µm range between 10^-14and 10^-12A/µm and show no dependence on channel length. Those of the p-channel MOSFET's were 10^-14-10^-12A/µm when the gate lengths were longer than 1.2 µm, and increased when the gate lengths were shorter than 1.0 µm. The propagation delay time of the CMOSFET inverter was 0.13 ns per stage at a supply voltage of 3.5 V.     

High-transconductance p-channel modulation-doped AlGaAs/GaAs heterostructure FET's

p-channel modulation-doped AlGaAs-GaAs heterostructure FET's (p-HFET's) employing two-dimensional hole gas (2DHG) were fabricated under various geometrical device parameter conditions. The p-HFET characteristics were measured at 300 and 77 K for the following three device-parameter ranges: the gate length Lg(1-320 µm), the gate-source distance Lgs(0.5-5 µm), and the layer thickness dt(35-58 nm) of AlGaAs beneath the gate. Based on the obtained results, a high-performance enhancement-mode p-HFET was fabricated with the following parameters:L_{g} = 1µm,L_{gs} = 0.5µm, andd_{t} = 35nm. The achieved extrinsic transconductance gmwas 75 mS . mm^-1at 77 K. This experimental result indicates that a gmgreater than 200 mS . mm^-1at 77 K Can be obtained in 1-µm gate p-HFET devices.     

High-speed polysilicon emitter—base bipolar transistor

High-speed polysilicon emitter and base electrode Si n-p-n bipolar devices were fabricated showing performances of 55-ps ECL gate delay (FI = FO = 1) and cutoff frequency of 15.6 GHz (at VCE= 3 V, LVCEO= 6.8 V). These devices were built on an oxide-isolated substrate produced by planarizing oxide which is deposited after device Si island etching. The final emitter width is 0.5 µm, and a 1.3-µm-thick arsenic-doped LPCVD epitaxial layer of 0.25 Ω.cm is utilized. Emitter-base (E-B) junctions formed by direct implantations of arsenic and boron ions into a substrate were compared with junctions induced by diffusing dopants from implanted polysilicon. In the case of diffused junctions, an emitter junction depth of less than 500 Å along with a 1000-Å base width can be obtained.     

101-Stage 2 µm gate ring oscillators in laser-grown silicon islands embedded in SiO2

E/D MOS test transistors and 101-stage 2 µm gate E/D MOS ring oscillators were fabricated in laser-grown single- and multicrystal islands embedded in oxide substrates. Most transistors showed goodI-Vcharacteristics, short-channel effects, and kink effects. Ring oscillators had a switching delay per stage (τPd) of 0.4 ns and a power-delay product (τ_{Pd} middot P_{d}) of 2.5 PJ at a supply voltage (VDD) of 10-15 V. It was noted that different crystal orientations of the islands posed no difficulty in processing and VTcontrol when applied to short channel devices, and that enhanced boundary diffusion results in occasional malfunctional transistors and erroneous high surface electron mobilities (µse).     

Submicrometer polysilicon gate CMOS/SOS technology

A process is described for the fabrication of CMOS/SOS submicrometer devices and integrated circuits. The process utilizes the lateral diffusion of boron into polycrystalline silicon and a subsequent anisotropic etchant to define the narrow poly gates. Devices with channel lengths as small as 0.3 µm have been fabricated and characterized. Both avalanche and tunnel injection of carriers into the gate dielectric have been measured and both can have an impact on the limit of voltage operation. At present, these mechanisms appear to place an upper limit of about 8 V on the operating voltage of dynamic circuits containing 0.5- µm channel length devices. The propagation delay of 0.5-µm channel length CMOS/SOS inverters is about 200 ps at 5 V and dynamic binary counters will operate with a maximum input frequency of 550 MHz and 8 V while dissipating 130 mW.     

2-µm Gate-length enhancement mode InGaAs/InP:Fe-JFET's with high transconductance

Investigations of enhancement mode InGaAs junction field-effect transistors (JFET's) grown on InP:Fe-substrate by liquid-phase epitaxy (LPE) are reported. The JFET's with 2-µm gate length and 190- µm gate width show a threshold voltage of 0.4 V, a low drain current of < 10 µA at 0-V gate-source voltage and a maximum transconductance of 105 mS/mm. The measured transconductances of enhancement mode InGaAs/InP:Fe JFET's with different gate lengths but with the same gate width and threshold voltage decrease proportional to the inverse gate length as expected from a constant drift mobility FET model.     

Si-gate CMOS devices on a Si/CaF2/Si structure

Si-gate CMOS inverter chains and 1/8 dynamic frequency dividers have been fabricated on a Si/CaF2/Si structure. A high-quality heteroepitaxial Si/CaF2/Si structure was formed by successive molecular-beam epitaxy of CaF2and Si. Transistors have been fabricated with an improved CMOS process that prevents crystal degradation during the fabrication process as much as possible. The maximum effective mobilities are about 570 and 240 cm²/V . s for n-channel and p-channel transistors, respectively. The inverter chain with an effective channel length of 2.0 µm has a delay time per gate of 360 ps. A maximum operating frequency of 300 MHz is obtained in the divider with an effective channel length of 2.5µm at a supply voltage of 5 V. These results indicate that the Si/CaF2/Si structure has potential for the fabrication of high-speed silicon-on-insulator devices.     

Self-aligned-gate GaInAs microwave MISFET's

A self-aligned-gate GaInAs metal-insulator-semiconductor FET (MISFET) fabrication process that minimizes gate overlap capacitance and offers the potential of achieving submicrometer gate lengths is described. GaInAs MISFETs (1-µm gate length) fabricated with this process have given 0.49-W/mm gate width and corresponding power-added efficiencies of 48 and 39 percent at 4 and 8 GHz, respectively, at a drain voltage of 5.5. V. A small-signal gain of 3.2 dB was obtained at 15 GHz. The estimated carrier velocity was 1.7 × 10⁷cm/s. More recent devices have carrier velocities of 2.5 × 10⁷cm/s and are expected to have improved microwave performance.     

Very short gate-length GaAs MESFET's

GaAs MESFET's with gate lengths ranging from 0.36 µm down to 0.055 µm, the smallest so far reported, have been fabricated using electron-beam lithography. DC output characteristics were obtained from all of the devices tested and transconductances up to 300 mS/mm were measured. However it was observed that there is a maximum drain-source voltage that can be pinched off in these short gate devices. This voltage varies exponentially from 1 V in the 0.055-µm gate devices to 6 V in the 0.36-µm device. It is speculated that this effect is due to current injection into the buffer layer.     

1-µm MOS process using anisotropic dry etching

Anisotropic and selective etching of silicon has been obtained using a planar-reactive sputter-etching system and CCl3F gas. The Si to SiO2etch-rate ratio was 5 : 1. This etch process in CCl3F was interpreted as mainly involving physical reaction as opposed to etching in SF6. The influence of reactive sputter etching on junction leakage and threshold voltage shift, in comparison with a conventional wetetch process, could not be observed in the electrical characteristics of polysilicon gate MOS devices. An all dry-etched MOS process, consisting of an anisotropic etching for Si3N4, polysilicon, SiO2, and aluminum, was applied to the fabrication of a 1-kbit static RAM with 1-µm minimum geometry. It was confirmed that this anisotropic etching technology was useful for very fine-geometry patterning and could be applied to a 1-µm MOSLSI manufacturing process.     

Double heterostructure Ga0.47In0.53As MESFETs with submicron gates

MESFETs with GA0.47In0.53As active channel grown by MBE on InP substrates were successfully fabricated. Thin layers of MBE grown Al0.48In0.52As seperated both the single crystal aluminum gate from the active channel and the active channel from the InP substrate so raising the Schottky barrier height of the gate and confining the electrons to the channel. The MESFETs with 0.6µm long gates and gate-to-source separations of 0.8 um exhibited an average gmof 135 mS mm^-1of gate width for Vds= 2V and Vg= 0. This is higher than that reported for GaAs MESFETs with a similar geometry in spite of the intermediate layer between the gate metal and the active layer.     

An optically defined 1.3-µm NMOS ring oscillator

n-channel enhancement/depletion (E/D) gate MOS ring-oscillators (RO) based on 1.3- and 2-µm layout design rules have been fabricated using 10:1 reduction projection aligner. A delay/stage of 80 ps and a power-delay product of 3.6 fJ have been obtained for a 401-stage RO consisting of 1.3-µm feature-size devices.     

Scaled GaAs MESFET's with gate length down to 100 nm

Fully ion-implanted GaAs depletion MESFET's with gate lengths from 1 µm down to 0.1 µm and with closely spaced source and drain contacts have been fabricated with electron-beam lithography. Gate-length dependence of transconductance, capacitance, output conductance, and threshold voltage is presented. Maximum transconductance obtained was 370 mS/mm for 0.1-µm gate length. The experimental data indicate that shallow implants do indeed result in better devices, but further vertical scaling of the devices is mandatory.     

A JMOS transistor fabricated with 100-Å low-pressure nitrided-oxide gate dielectric

A Junction MOS (JMOS) transistor is proposed to offer increased performance over conventionally scaled NMOS devices as the gate dielectric thickness is reduced. The design, fabrication, and characterization of the JMOS device with a 100-Å gate dielectric is presented. Conventionally scaled NMOS and JMOS devices with gate lengths down to 1 µm are compared. The JMOS devices show a 25- percent increase in channel electron mobility and a 15-percent increase in drain current for equivalent gate drives with minimal adverse short-channel effects.     

Small geometry MOS transistor capacitance measurement method using simple on-chip circuits

A method of measuring the gate capacitance of very small geometry devices using simple on-chip circuits is described. Short-channel effects observed in gate capacitance measurements of an MOS transistor with Weff/Leff= 9.2 µm/0.8 µm are presented. Measurement results show that the resolution of the technique is much better than 0.1 fF.     

A dc and microwave comparison of GaAs MESFET's on GaAs and Si substrates

In order to assess GaAs on Si technology, we have made a performance comparison of GaAs MESFET's grown and fabricated on Si and GaAs substrates under identical conditions and report the first microwave results. The GaAs MESFET's on Si with 1.2-µm gate length (290-µm width) exhibited transconductances (gm) of 180 mS/mm with good saturation and pinchoff whereas their counterparts on GaAs substrates exhibited gmof 170 mS/mm. A current gain cut-off frequency of 13.5 GHz was obtained, which compares with 12.9 GHz observed in similar-geometry GaAs MESFET's on GaAs substrates. The other circuit parameters determined from S-parameter measurements up to 18 GHz showed that whether the substrate is Si or GaAs does not seem to make a difference. Additionally, the microwave performance of these devices was about the same as that obtained in devices with identical geometry fabricated at Tektronix on GaAs substrates. The side-gating effect has also been measured in both types of devices with less than 10-percent decrease in drain current when 5 V is applied to a pad situated 5 µm away from the source. The magnitude of the sidegating effect was identical to within experimental determination for all side-gate biases in the studied range of 0 to -5 V. The light sensitivity of this effect was also very small with a change in drain current of less that 1 percent between dark and light conditions for a side gate bias of -5 V and a spacing of 5 µm. Carrier saturation velocity depth profiles showed that for both MESFET's on GaAs and Si substrates, the velocity was constant at 1.5 × 10⁷cm/s to within 100-150 Å of the active layer-buffer layer interface.     

TaSi2gate for VLSI CMOS circuits

It is shown, that lateral shrinkage of 2-µm CMOS devices and reduction of the gate oxide thickness to about 20 nm is significantly facilitated by replacing the n⁺-poly-Si or polycide gates by TaSi2. Due to its higher work function, TaSi2allows the simultaneous reduction of the channel doping in the n-channel and the charge compensation in the p-channel without changing the threshold voltages. Thus compared with n⁺-poly-Si gate n-channel transistors substrate sensitivity and substrate current are reduced, and low-level breakdown strength is raised. In p-channel transistors, the subthreshold current behavior and UT(L)-dependence are improved. Consequently, the channel length of both n- and p-channel transistors can be reduced by about 0.5 µm without significant degradation. The MOS characteristics Nss, flatband and threshold voltage stability, and dielectric strength appear similar for TaSi2and n+-poly Si gate transistors.     

Gate-length dependence of the speed of SSI circuits using submicrometer selectively doped heterostructure transistor technology

Frequency dividers and ring oscillators have been fabricated with submicrometer gates on selectively doped AIGaAs/GaAs heterostructure wafers. A divide-by-two frequency divider operated up to 9.15 GHz at room temperature, dissipating 25 mW for the whole circuit at a bias voltage of 1.6 V, with gate length ∼ 0.35 µm. A record propagation delay of 5.8 ps/gate was measured for a 0.35-µm gate 19- stage ring oscillator at 77 K, with a power of 1.76 mW/gate, and a bias voltage of 0.88 V. The maximum switching speed at room temperature was 10.2 ps/gate at 1.03 mW/gate and 0.8 V bias, for a ring oscillator with the same gate length. With a range of gate lengths on the same wafer fabricated by electron-beam lithography, a clear demonstration of gate-length dependence on the propagation delay was observed for both dividers and ring oscillators.     

Design and performance of "1.25-µm" CMOS for digital applications

This paper presents a detailed approach for the design and performance analysis of 1.25-µm CMOS digital circuit technology based on relatively simple sets of fundamental device parametric and circuit equations. As a start, a topological and "in-depth" baseline is assumed for this 1.25-µm CMOS technology, based, in part, on a set of achievable lithographic feature sizes and alignment tolerances together with a set of reasonable process geometric parameters. The process baseline is TWIN-WELL CMOS using n^-epi on an n⁺substrate as the host starting material. Two of the key geometric parameters defined are effective channel length, Le= 1 µm, and gate oxide thickness, tox= 250 Å. Other dimensions have been selected using quasi-scaling rules consistent with a 2λ of 1.25 µm. The design process starts with the selection of the average "well" doping levels from a consideration of some key short-channel effects: simple charge sharing and drain-induced barrier lowering (DIBL). The selection of a suitable operating voltage, VDD, is considered during this process as it effects junction breakdown voltage, gate oxide fields, and more importantly, potential hot-electron injection. Additional process design analyses are presented with respect to the establishment of gate threshold voltages and field inversion voltages. A simple transient analysis procedure is developed for a basic inverter structure which yields results close to those obtained through more detailed SPICE simulations. A unit delay (single fan-out) analysis is performed yielding delays of 214 ps for a VDDof 5 V and 270 ps for a VDDof 3.3 V.