Built-in redundancy analysis for memory yield improvement

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. The yield improvement and testing issues have become the most critical challenges for memory manufacturing. Conventionally, redundancies are applied so that the faulty cells can be repairable. Redundancy analysis using external memory testers is becoming inefficient as the chip density continues to grow, especially for the system chip with large embedded memories. This paper presents three redundancy analysis algorithms which can be implemented on-chip. Among them, two are based on the local-bitmap idea: the local repair-most approach is efficient for a general spare architecture, and the local optimization approach has the best repair rate. The essential spare pivoting technique is proposed to reduce the control complexity. Furthermore, a simulator has been developed for evaluating the repair efficiency of different algorithms. It is also used for determining certain important parameters in redundancy design. The redundancy analysis circuit can easily be integrated with the built-in self-test circuit.     

逆向统计模拟及在VLSI统计分析中的应用

本文在理论上提出了逆向统计模拟思想,并用以开发了NMOS数字集成电路统计模拟通用软件——STANMOS。应用该软件可定量得到工艺涨落及工艺干扰对电路性能的影响,分析电路性能的工艺灵敏度及成品率,确定主要影响电路性能一致性的工艺步骤。     

MOSFET substrate current model for circuit simulation

A simple, accurate MOSFET substrate current model suitable for a circuit simulator is presented. The effect of substrate bias on substrate current is modeled without introducing additional parameters. The accuracy of this model is demonstrated by its ability to fit the experimental data for both standard and LDD devices with average errors of less than 6%. The new model is compared with the substrate current models reported in the literature. In addition, the temperature dependence of the substrate current in the range of 0-120°C is also modeled. The new model has been implemented in a circuit-level hot-electron reliability simulator, and the results obtained from simulation of an inverter circuit are presented     

Modeling MOS VLSI circuits for transient analysis

Modeling plays a significant role in the efficient simulation of VLSI circuits. By simplifying the models used to analyze these circuits, it is possible to perform transient analyses with reasonable accuracy at speeds of one or two orders of magnitude faster than in conventional circuit simulation programs. The author discusses the models that are used in the second-generation MOTIS timing simulator. The methods used have been applied to a wide variety of MOS digital integrated circuits. All MOS transistors are modeled as voltage-controlled current sources using multidimensional tables. The actual currents are computed by approximation using variation-diminishing tensor splines. Nonlinear device capacitances in the circuit are approximated using linear models which are derived from experimental simulations using a circuit simulator. At the subcircuit level, special structures in the circuit are identified automatically by a preprocessor and are modeled using macro-models. Driver-load MOS transistor gates and bootstrapped circuits are examples of these structures. Their modeling is achieved by an experimental process before implementation in the preprocessor. The simplifications in the device and circuit models presented here have provided a significant improvement in the speed of transient analysis for large MOS digital circuits with relatively little loss in accuracy. This has resulted in a viable design verification environment using MOTIS.     

VIPMOS-a novel buried injector structure for EPROM applications

A buried injector is proposed as a source of electrons for substrate hot electrons injection. To enhance the compatibility with VLSI processing, the buried injector is formed by the local overlap of the n-well and p-well of a retrograde twin-well CMOS process. The injector is activated by means of punchthrough. This mechanism allows the realization of a selective injector without increasing the latchup susceptibility. The p-well profile controls the punchthrough voltage. The high injection probability and efficient electron supply mechanism lead to oxide current densities up to 1.0 Å.×cm^-2. Programming times of 10 μs have been measured on nonoptimized cells. The realization of a structure for 5-V-only digital and analog applications is viable. A model of the structure for implementation in a circuit simulator, such as SPICE, is presented     

Integrated-circuit reliability simulation with emphasis on hot-carrier effects

Reliability assurance and enhancement of analog VLSI circuits are of fundamental importance in the design of high quality signal processing and computing systems. An analog integrated circuit may fial due to degradation of some critical transistors. In this paper, strategies for use in a hierarchical reliability simulation environment covering various levels of VLSI circuit design are presented. Hot-carrier effects are used to demonstrate the prediction of degradation in circuit performance. This degradation information is propagated through the design hierarchy, with the data at each stage conforming with the complexity of representation at that stage. Circuit topology changes may be made at different levels to reduce the intensive electrical stress applied to weak components. At the top level the chip degradation information is essential for the design of reliable VLSI systems. The method used to include the first-order ac degradation effects into the circuit reliability simulator is described. Experimental results on inverters, precharging circuitry for sense amplifiers, and operational amplifiers designed in submicron technologies are presented.This research was partially supported by National Science Foundation under grant MIP-8710825 and by industrial grants from Samsung Electronics Co. and TRW Inc.     

MOS and bipolar VLSI technologies using electron-beam lithography

Key issues for micrometer and submicrometer MOS and bipolar device fabrication are discussed, including lithography, device and circuit scaling limitations, and process considerations. Lithographic requirements are presented in terms of an overall technology-machine, resist and pattern transfer methods-and an electron-beam alice writing technology is described which satisfies those needs. Viable micrometer and submicrometer MOS and bipolar process technologies are demonstrated by scaling complex LSI circuits to VLSI density using electron lithography. For the MOS case, scaling of static memories is discussed in detail, including fabrication of a 4K SRAM with 1.5-µm minimum feature sizes, 12-15-ns access times, and a chip size of only 6K mil². A discussion of bipolar device and process scaling issues is highlighted by the successful fabrication of a scaled 16-bit integrated injection logic (I²L) microprocessor with 1.25-µm minimum feature sizes and a clock frequency of 10 MHz with a chip current of only 250 mA.     

重掺杂型混合信号集成电路衬底的噪声模型研究

应用器件模拟软件SILVACO模拟三种结构重掺杂型衬底中注入高频电流的分布,根据模拟结果分析得出重掺杂型衬底的简化模型为一单节点,进而将简化模型与实际的混合信号集成电路结合,建立起重掺杂型衬底的噪声模型,并给出了参数估算式。     

精确的短沟MOSFET电路模型及参数提取

给出一套具有较高精度且同时适用于数字电路和模拟电路ＣＡＤ的短沟ＭＯＳ器件直流模型。该模型精确、高效，可移植到ＨＳＰＩＣＥ等通用线路分析软件中。结合解析和数值两种参数提取方法，文中采用局部优化参数提取法进行ＭＯＳ器件参数提取。优化算法采用单纯形直接搜索法。参数提取过程中考虑了输出电导的精确性。通过对１．２μｍＣＭＯＳ工艺ＮＭＯＳ器件的测试及参数提取，并进行模型计算，结果表明理论和实际值符合很好。     

Resistive interpolation biasing: a technique for compensatinglinear variation in an array of MOS current sources

A new technique called resistive interpolation biasing for accurately biasing a large number of analog cells on a VLSI chip is presented. Variations in oxide thickness, mobility, doping concentration, etc., cause inaccuracies in current ratios of two identically biased transistors if they are placed sufficiently far apart on a chip. The proposed technique compensates for these inaccuracies without using any sampling or switching. The technique has been verified using a 2 μm n-well CMOS process. Measurements show a factor of 3 improvement in terms of current ratio accuracy when the resistive interpolation technique is used. The circuit can be implemented with a small chip area and low power dissipation. This technique finds applications where extensive current duplication over a large area is required (e.g., analog memories, D/A converters, continuous-time filters, imaging arrays, neural networks, and fuzzy logic systems)     

Compact modeling of a flash memory cell including substrate-bias-dependent hot-electron gate current

We propose a compact model for a Flash memory cell that is suitable for circuit simulation. The model includes a hot-electron gate current model that considers not only channel hot electron injection but also channel initiated secondary electron injection to express properly substrate bias dependence of gate current. Tunneling gate current for erasing is expressed by the BSIM4 tunneling gate current model. Good agreement between measured and simulated results of both programming and erasing characteristics for 130-nm technology Flash memory cells indicates that our model is useful in designing and optimizing circuit for Flash memories.     

Yield-enhancement of a large systolic array chip

This paper examines the feasibility of enhancing the yield of a very large VLSI circuit through the use of fault-tolerant circuitry. The example of a linear array architecture has been selected because it appears to be the next most promising candidate after memories. An example is presented which shows that with rather simple circuitry a chip 8 times larger than a conventional design could actually turn out to have a higher yield. This combined with economies of scale make the approach look attractive.     

用分量匹配法实现对高速时钟电路的动态优化

本文讨论如何设计工作在GHz频率下的VLSI芯片时钟电路.时钟树采用平衡平面布局消除时钟偏差;利用插入缓冲器对电路性能进行动态优化.最后用一个电路模拟软件对电路进行评估.和以往的工作相比较,本文实现了在频域内对时钟电路的优化,显著地提高了仿真速度.     

BMM-ESD模拟器有源电路的模型构建

针对BMM-ESD模拟器电路的电感L等无源器件在线性和集成方面存在困难等诸多问题,提出一种BMM-ESD模拟器有源电路的设计.设计基于一个考虑寄生振荡的六阶BMM-ESD模拟器无源LC电路,通过数学计算的方法,构建形成基于线性放大器的有源BMM-ESD模拟器电路模型.模拟仿真表明,六阶BMM-ESD模拟器自有源电路与无源LC电路的BMM-ESD 电流仿真结果完全吻合,验证了电路模型的正确性与可行性.     

Low-power high-performance double-gate fully depleted SOI circuitdesign

Double-gate fully depleted (DGFD) SOI circuits are regarded as the next generation VLSI circuits. This paper investigates the impact of scaling on the demand and challenges of DGFD SOI circuit design for low power and high performance. We study how the added back-gate capacitance affects circuit power and performance; how to tradeoff the enhanced short-channel effect immunity with the added back-channel leakage; and how the coupling between the front- and back-gates affects circuit reliability. Our analyses over different technology generations using the MEDICI device simulator show that DGFD SOI circuits have significant advantages in driving high output load. DGFD SOI circuits also show excellent ability in controlling leakage current. However, for low output load, no gain is obtained for DGFD SOI circuits. Also, it is necessary to optimize the back-gate oxide thickness for best leakage control. Moreover, threshold variation may cause reliability problems for thin back-gate oxide DGFD SOI circuits operated at low supply voltage     

Electro-thermal and logi-thermal simulation of VLSI designs

Due to severe thermal problems of today's VLSI integrated circuits the need for reliable and quick thermal, electro-thermal and logi-thermal simulation tools is increasing, In this paper, we discuss the latest advances in the SISSI package (simulator for integrated structures by simultaneous iteration) which is a tool developed originally for analog VLSI design. The improvements include electro-thermal ac and transient simulation and the consideration of the thermal voltage of Si-Al contacts. Furthermore, we introduce a new module of SISSI, LOGITHERM, which is aimed at the self-consistent logic and thermal simulation of large digital VLSI designs. The features of our simulator package are highlighted by simulation examples that are compared in most cases with measurement results     

体硅衬底上的CMOS Fin FET

介绍了一种制作在普通体硅上的 CMOS Fin FET.除了拥有和原来 SOI上 Fin FET类似的 Fin FET结构 ,器件本身在硅衬底中还存在一个凹槽平面 MOSFET,同时该器件结构与传统的 CMOS工艺完全相容 ,并应用了自对准硅化物工艺 .实验中制作了多种应用该结构的 CMOS单管以及 CMOS反相器、环振电路 ,并包括常规的多晶硅和 W/Ti N金属两种栅电极 .分析了实际栅长为 110 nm的硅基 CMOS Fin FET的驱动电流和亚阈值特性 .反相器能正常工作并且在 Vd=3V下 2 0 1级 CMOS环振的最小延迟为 14 6 ps/门 .研究结果表明在未来 VL SI制作中应用该结构的可行性     

体硅衬底上的CMOS FinFET

介绍了一种制作在普通体硅上的CMOS FinFET.除了拥有和原来SOI上FinFET类似的FinFET结构,器件本身在硅衬底中还存在一个凹槽平面MOSFET,同时该器件结构与传统的CMOS工艺完全相容,并应用了自对准硅化物工艺.实验中制作了多种应用该结构的CMOS单管以及CMOS反相器、环振电路,并包括常规的多晶硅和W/TiN金属两种栅电极.分析了实际栅长为110nm的硅基CMOS FinFET的驱动电流和亚阈值特性.反相器能正常工作并且在Vd=3V下201级CMOS环振的最小延迟为146ps/门.研究结果表明在未来VLSI制作中应用该结构的可行性.