Formation of silicided,ultra-shallow junctions using low thermal budget processing

The tradeoffs involved in alternative processes for the formation of ultra shallow junctions are described. Low energy implantation, preamorphization to eliminate channeling and low thermal budget processing are adequate to form junctions that are 0.1 to 0.3μm deep. For junctions less than about 100 nm, however, the enhanced diffusion resulting from the amorphization implant reduces its benefits. Athermal diffusion can result in considerable junction motion even when low thermal budget processing is used. Junctions this shallow typically require silicide or metal cladding to reduce the sheet resistance; however, the dopant redistribution associated with siliciding pre-existing junctions increases the contact resistance which diminishes the potential benefit of silicidation. In addition, high leakage can result from excessive silicon consumption. While the use of silicide as a diffusion source can overcome some of the limitations of silicided junctions, this technique can be especially hindered by slow dopant diffusion or compound formation in the silicide and by the limited thermal stability of the silicide. One outstanding issue associated with silicide diffusion sources is understanding the seemingly enhanced diffusivity of dopant in the silicon.     

Fabrication of submicron junctions-proximity rapid thermaldiffusion of phosphorus, boron, and arsenic

Various techniques used in fabrication of deep submicron junctions are reviewed with respect to their advantages and disadvantages in silicon very large scale integration (VLSI) circuits technology. Proximity rapid thermal diffusion is then presented as an alternative process which results in very shallow junctions with high dopant concentrations at the surface. The feasibility of Si doping with B, P, and As for both planar and 3-D structures such as trench capacitors used in high density DRAM memories is shown based on sheet resistance measurements, secondary ion mass spectroscopy and scanning electron micrographs. Retardation effect of arsenic diffusion similar to the well known inhibition of silicon or SiO₂ deposition in chemical vapor deposition (CVD) processes is identified and discussed     

Nonmelt laser annealing of 5-KeV and 1-KeV boron-implanted silicon

Nonmelt laser annealing has been investigated for the formation of ultrashallow, heavily doped regions. With the correct lasing and implant conditions, the process can be used to form ultrashallow, heavily doped junctions in boron-implanted silicon. Laser energy in the nonmelt regime has been supplied to the silicon surface at a ramp rate greater than 10 ¹⁰°C/s. This rapid ramp rate will help decrease dopant diffusion while supplying enough energy to the surface to produce dopant activation. High-dose, nonamorphizing boron implants at a dose of 10¹⁵ ions/cm² and energies of 5 KeV and 1 KeV are annealed with a 308-nm excimer laser. Subsequent rapid thermal anneals are used to study the effect of laser annealing as a pretreatment. SIMS, sheet resistance and mobility data have been measured for all annealing and implant conditions. For the 5-KeV implants, the 308-nm nonmelt laser preanneal results in increased diffusion. However, for the 1-KeV implant processed with ten laser pulses, the SIMS profile shows that no measurable diffusion has occurred, yet a sheet resistance of 420 Ω/sq was produced     

Two-step rapid thermal diffusion of boron into silicon using a boron nitride solid diffusion source

A two-step rapid thermal diffusion process of boron into silicon using a boron nitride solid diffusion source is described. During the first step, HBO² glass is transferred onto the silicon wafer from the diffusion source by keeping the temperature of the silicon wafer at 750° C while the diffusion source is at about 900° C. Boron is, then, diffused into the silicon wafer from HBO² glass at 1000° C or 1100° C in N₂ during the second step. Extremely shallow junctions with junction depths of about 20 nanometers and sheet resistances of about 350 ohms/sq can be achieved with this method as well as relatively deep junctions with junction depths of about 175 nanometers and sheet re-sistances of about 55 ohms/sq. When the diffusion is performed at 1100° C, both the junction depth and electrically active boron concentration at the surface increase as the ambient gas is changed from N₂ to O₂ while the sheet resistance decreases. A boron rich layer which has high resistivity is not formed at the surface when the diffusion is performed at 1100° C in O₂ ambient. This work was supported by Ministry of Science and Technology, Korea     

Trench sidewall implantation with a parallel scanned ion beam

The sidewalls of trenches on 100-mm wafers were doped by implantation with an implanter whose beam scan is accurately parallel over the whole wafer surface. The doping was characterized with a staining technique and transmission electron microscopy. All the trenches exhibited symmetrical doping, with the main differences between trenches from the center and edge of a wafer being due to nonuniformity of the trench etching rather than the implant step. Although the measurements were made on 100-mm wafers, symmetrical doping should be achievable for all trenches on wafers up to 200 nm in diameter     

Fabrication of p-i-n photodiodes on LPE-grown substrates

Epitaxial growth of a thick heavily doped silicon layer on a highly resistive silicon wafer by the yo-yo solute feeding method and its application to p-i-n photodiodes are discussed. An abrupt transition of the impurity profile is obtained between the n⁺ layer (1.95×10¹⁹ cm^-3, 450 μm) and the n^- layer (7.0×10¹¹ cm^-3, 80 μm). It is possible to use the thick intrinsic layers as the active region of power devices     

On approaches to the built-in electric-field calculations in shallow silicon n+-p junctions

A critical appraisal of recent approaches to the built-in electric-field E calculations in shallow heavily doped strongly asymmetric silicon n⁺-p junctions is performed. The existence of a large (≃ 1 - V/µm), positive field E of built-in nature on the surface of the n⁺-layer-reported previously through the computation of E as a gradient of erfc impurity profile in very steep n⁺-p junctions-is refuted on the grounds of semiconductor fundamentals. Alternatively, it is shown that: 1) under thermal equilibrium conditions and a "free" (air or vacuum) silicon surface, the built-in field should necessarily go to zero at the semiconductor surface; 2) if the projected built-in field E nears the surface on the heavily doped side of a junction, then it is compulsory to take into account the interaction between E and the prevailing surface charges. The results of this work suggest that all processes in the surface-controlled region of the heavily doped layer are being shaped by the interplay of the bulk field E created by the impurity gradients with the field Esurforiginated in the surface states.     

Plasma-Assisted Diffusion Doping of Porous-Silicon Films

An experiment is conducted on the diffusion of arsenic or phosphorus from an RF plasma into a porous-silicon film intended to serve as a source for the next diffusion step, the film being made by plasma etching or electrolytic anodization. The ultimate goal is to reduce the wafer temperature. It is shown that much lower temperatures are indeed possible with the diffusion technique considered. It is established that doping concentration is more uniform over the wafer surface if pores are arranged regularly, as with porous silicon produced by plasma etching. It is also established that plasma-assisted diffusion is mainly affected by the dispersion of pores in size, total pressure, the partial pressure of the doping agent (AsH₃ or PH₃), RF power, and wafer temperature. Porous-silicon films doped with As or P by plasma-assisted diffusion could be employed in power devices.     

Optical effects during rapid thermal diffusion

The formation of n⁺-p or n⁺-p-p⁺ junctions by rapid thermal diffusion of phosphorus or co-diffusion of phosphorus and aluminum into silicon is opening new possibilities for low-cost and environmentally safe solar cell production. In this work, we analyze the influence of the higher energetic part of the lamp spectrum on phosphorus diffusion, and the impact of evaporated aluminum for back surface field formation during a P-Al co-diffusion step. The diffusion of phosphorus from doped glass films spun onto monocrystalline silicon material in various furnace configurations with front, back, or double sided heating is studied to investigate the influence of the radiation spectra on the dopant profiles. The experiments reveal a relation of the dopant profile to the amount of ultraviolet radiation reaching the surface. Therefore, a modified RTP-System is used for further investigations to demonstrate the influence of the ultraviolet (UV) light on the diffusion profiles. These experiments clearly show that the influence of the UV light is mainly on the densification of the spin-on-glass and not on diffusion kinetics in silicon. Furthermore, the simultaneous formation of a back surface field is of special interest for solar cells. Earlier studies of the simultaneous diffusion of phosphorus and aluminum in order to form a n⁺-p-p⁺ structure show (compared to a single phosphorus diffusion) deeper n⁺ emitters. Using glass densification experiments on such samples, a correlation was found between the decrease in emissivity on the aluminum-coated part of the wafer and the increase in temperature, which seems to be responsible for the deeper profiles.     

Influence of the dopant density profile on minority-carrier current in shallow,heavily doped emitters of silicon bipolar devices

Experimental determination of the dependence of recombination current in p⁺ and n⁺ regions on the dopant profile for shallow emitters of ion-implanted silicon solar cells is described. The results are analyzed by extending a previous analytical model for the transport of minority carriers in heavily doped regions. The extension accounts for an effective electric field, defined by heavy-doping effects at the surface, and suggests that the energy-gap narrowing for p⁺ silicon is slightly smaller than that for n⁺ silicon and/or that minority-carrier diffusivities are substantially lower than the majority-carrier ones at comparable dopant densities. The very high dopant densities achieved with the ion implantation/laser annealing technique provide an in situ surface passivation that supresses surface recombination and minimizes the emitter recombination current.     

NMOS Ring oscillators with cobalt-silicided P-diffused shallow junctions formed during the "Poly-plug" contact doping cycle

Composite silicided source-drains are being developed to provide low-resistance shallow junctions for high performance fine-line circuits. The junctions are usually formed either by implantation and drive prior to silicide formation or else by implantation immediately after, followed by a heat cycle. This paper describes a novel approach for the fabrication of CoSi2/n⁺-p junctions (2 . 5 Ω/□ sheet resistance), wherein the junctions are doped by diffusion through the contact windows using the conventional "poly-plug" doping cycle [1], [2]. LPCVD poly-Si is deposited on windows to previously silicided gate and source-drain regions, and exposed to PBr3at an elevated temperature. Since the diffusivity of dopants in silicides is higher than in bulk Si, this step transports the P through the poly-Si via the windows laterally into the silicide, to form uniformly doped junction surrounds. This poly-Si doping scheme for junction fabrication eliminates an ion-implant step, provides an independent means of tailoring channel length, and can potentially result in low-resistance contacts even if the window etch step has punched through the silicide, Electrical characteristics of 1.25-µm gate-length ring oscillators are similar to those of circuits processed with the conventional As implant and drive. TransistorI-V's and subthreshold behavior remain unaffected by the silicide doping process. Junction depth and leakage are sensitive functions of the poly-plug thermal cycle, with a 950°C 30-min drive resulting in 0.3-µm junctions. For a 1-µm design rule circuit layout, 30 to 45 min at 950°C is judged adequate.     

The formation of shallow low-resistance source—Drain regions for VLSI CMOS technologies

As a result of MOS device scaling, very shallow source-drain structures are needed to minimize short-channel effects in 1-µm transistors. This can be readily achieved with highly doped arsenic regions for NMOS devices but is more difficult using boron for PMOS devices. In addition, shallow junctions suffer from inherently high sheet resistances due to dopant solid solubility limitations. This paper proposes an improved CMOS source-drain technology to overcome both these problems. The technique employs amorphizing silicon implants prior to dopant implantation to eliminate ion channeling and platinum silicidation to substantially reduce sheet resistance. Counterdoping of the p⁺regions by high-concentration arsenic implantation is used to enable both NMOS and PMOS devices to be manufactured with only one photolithographic masking operation. Using this technique, n⁺and p⁺junction depths are 0.22 µm and of 8 Ω/sq. sheet resistance. By creating oxide sidewalls on gate conductors, polysilicon can be silicided simultaneously with diffusions. Results of extensive materials analysis are discussed in detail. The technique has been incorporated into a VLSI CMOS process schedule at our laboratories.     

Sensitivity of subthreshold current to profile variations inlong-channel MOSFETs

The sensitivity of MOSFET behavior to small variations in doping profiles increases as the devices become smaller. This increased sensitivity raises new issues regarding the accuracy needed in manufacturing, modeling and measurement of small devices. A formalism has been developed to determine the maximum profile variations consistent with any prescribed allowable variation in gate bias δV _GS/V_GS. This formalism has been developed for arbitrary profiles, and has been applied to retrograde box profiles (that is, profiles with a low surface level of doping out to some box depth, followed by a more heavily doped region at greater depths). The results show that profile sensitivity can vary dramatically from one device to another in a family of devices designed to operate with similar threshold voltages. As box depth increases, sensitivity to box depth and to surface doping also increases (the allowed tolerances decrease), while sensitivity to the bulk doping value Is reduced (tolerance increases). The worst-case scenario (smallest tolerance) for variations in the box depth d occurs for depths where the depletion layer width w_I is least i.e. for cases near the onset of the condition w_I≈d. It is known that this condition results in devices with the best short channel immunity. It is found for a typical 1/4 μm device with an oxide thickness of 5 nm and a threshold voltage of 355 mV, a change in the depth of a box profile by ≈3 nm, or a change in the surface doping level of δN_s≈≈7×10¹⁶/cm³ is sufficient to require a compensating change in gate bias of 35 mV. Consequently, any profile measurement or process model that aims to predict 1/4 μm-MOSFET thresholds to within ±30 mV will have to locate dopant ions within ±30 mV will have to locate dopant concentrations to better than a few 10¹⁶/cm³     

Methods of defect-engineering shallow junctions formed by B+-implantation in Si

Control of dopant diffusion during high-temperature cycling is critical in forming shallow electrical junctions in silicon as needed in integrated-circuit manufacturing. However, junctions formed by implantation can be anomalously deep due to a transiency associated with ion-induced defects which greatly enhances dopant diffusion. The purpose of this work was to investigate methods of defect engineering the implantation process to control or eliminate transient-enhanced diffusion (TED). TED of boron has been attributed to excess interstitials introduced into the lattice during implantation, known as the plus-one model. Effects of pre-amorphization (i.e., amorphization prior to dopant implantation using isoelectric ions) on TED of boron, and particularly, the role of the end-of-range (EOR) defects at the amorphous-crystalline interface, are discussed. These EOR defects were varied by altering the implantation conditions during pre-amorphization. Also, other means of controlling the transiency are discussed, in particular, the use of high-energy ions to introduce excess vacancies into the lattice where dopant diffusion occurs. These vacancies are shown to interact with the excess interstitials introduced during dopant implantation to suppress TED.     

Cobalt disilicide as dopant diffusion source for polysilicon gates in MOS devices

In this paper, a novel p-channel metal oxide semiconductor (PMOS) device fabrication process using BF₂-implanted CoSi₂ as a boron diffusion source for both polycrystalline-silicon (polysilicon) gate doping and shallow source/drain junction formation is studied. Important issues including thermal stability of the CoSi₂/polysilicon stacked layer and boron redistribution in the CoSi₂/polysilicon stacked layer are discussed in detail. The data show that the thermal stability of CoSi₂/polysilicon stacked layers can be significantly improved by using as-deposited amorphous silicon films rather than as-deposited polysilicon films. Samples with 120 nm CoSi₂ on 180 nm polysilicon are thermally stable up to 1000°C for 60 s in a N₂ ambient. Secondary ion mass spectroscopy analyses show that degenerately doped polysilicon gates and shallow source/drain junctions can be achieved simultaneously. Furthermore, a simple method to study the electrically active dopant redistribution in CoSi₂polysilicon gates using MOS capacitors is proposed.     

Selective doping of silicon by rapid thermal and laser assisted processes

The selective doping technique, made by the combination of spin-on dopant (SOD) source deposition, rapid thermal annealing (RTA) and laser treatments is proposed as an innovative process for large area devices, like silicon solar cells.Rapid thermal diffusion (RTD) is first carried out from phosphorus SOD layers to form a lightly doped junction followed by pulsed laser irradiation to induce overdoping in selectively chosen regions.Here we present extensive study on the dependence of selective doping efficiency through different working variables, such as dopant source dilution, diffusion temperature and time for RTPs, and power and translation velocity for lasers. Electrical and structural characterizations have been performed by using several techniques: SIMS, stripping-Hall, four-point probe resistivity, SEM and TEM analysis.The combined use of these processes has been applied to the realization of selective emitter structures for silicon solar cells.     

Dual-polycide gate technology using regrowth amorphous-Si tosuppress lateral dopant diffusion

Process techniques for dual-polycide gate CMOS have been developed. The origin of lateral dopant diffusion is analyzed, and an enlarged-grain dual-polycide gate technology using regrowth amorphous-Si (a-Si) is proposed. Reduction of the dopant absorption into the silicide layer has been observed in the regrowth of a-Si polycide gate structure. Lateral dopant diffusion has been suppressed to less than 0.1 μm, and, as a result, 0.2 μm n-MOS/p-MOS spacing has been realized under an 850°C furnace annealing process. This technology can also achieve current drivability improvement by suppressing the gate depletion simultaneously. Suppression of boron penetration through the gate oxide to the channel region from the p⁺ gate has been realized by gate doping ion implantation into the a-Si, and no threshold voltage lowering with small standard deviation has been confirmed. It has been recognized that the above techniques are a possible solution for the dual-polycide gate CMOS structure     

Preparation,characterization and application of RF sputter deposited boron doped silicon dioxide thin films

We report the preparation of thin film boron doped silicon dioxide (also called borosilicate–glass or BSG) by RF magnetron and its use as a boron diffusion source, especially for shallow junctions. For this purpose, a sputtering target of BSG was prepared through conventional solid state reaction route. Deposition rates of sputter deposited BSG film at different sputtering parameters were studied. The presence of boron in the deposited film was confirmed by hot probe and sheet resistance techniques on silicon wafer following a diffusion step. The structural evaluation of BSG thin film was performed using Fourier Transform Infrared Spectroscopy (FTIR). Secondary Ion Mass Spectroscopy (SIMS) was used to measure the concentration profile of boron in the BSG film. The effect of sputtering parameters on boron concentration in the deposited BSG film was also studied. A p–n junction diode was fabricated using BSG thin film as diffusion source of boron. The junction depth was measured to be in the range of 0.06–1.0 µm for different sputtering and diffusion parameters.     

A new method of forming a thin single-crystal silicon diaphragmusing merged epitaxial lateral overgrowth for sensor applications

Merged epitaxial lateral overgrowth (MELO) of silicon was combined with an SiO₂ etch stop to form a 9-μm-thick and 250-μm×1000-μm single-crystal Si membrane for micromechanical sensors. When epitaxial lateral overgrowth (ELO) silicon merges on SiO₂ islands, it forms a local silicon-on-insulator (SOI) film of moderate doping concentration. The SiO₂ island then acts as a near-perfect etch top in a KOH- or ethylenediamine-based solution. The silicon diaphragm thickness over a 3-in wafer has a standard deviation of 0.5 μm and is precisely controlled by the epitaxial silicon growth rate (≈0.1 μm/min) rather than by conventional etching techniques. Diodes fabricated in the substrate and over MELO regions have nearly identical reverse-bias currents, indicating good quality silicon in the membrane