DDR4并行互连传输串扰特性仿真与分析

为满足高带宽存储应用需求,访存速率和互连密度越来越高。DDR4作为主存领域应用广泛且速率较快的并行存储互连技术,上升/下降沿时间或低至百ps量级,信号间串扰不容忽视。以某DDR4驱动模型和板级嵌入式应用为研究对象,建立多线打扰模型,从时域角度仿真分析布线间距、打扰源相位、数据速率、耦合传输线长对带状线传输串扰的影响。结果显示：5倍介质厚度布线间距条件下串扰接近于0 mV,不同相位关系打扰源形成的总串扰具有成倍双向差异。对于特定访存速率,耦合传输线长度与串扰极值存在周期性对应关系,据此合理设计DDR数据组线长,可以有效规避串扰极大值。     

串扰最小化的网格模式下的双层通道布线

超深亚微米IC设计中互连线的串扰情况与详细布线方案和信号波形密切相关。基于这一事实，在网格模式下的通道布线算法中建立了最小化串扰的目标函数。提出获得最小化串扰布线方案的方法。与以往算法不同的是，本方法将相邻平行线间信号跳变的方式和频度作为目标函数中的影响因子。可以更准确地估计出布线区内串扰总和的大小。并且通过构造布线生成树的方法求得精简的布线方案。有效地减少了求解具有最小串扰的布线方案的计算量。     

调整门和连线尺寸以减小串扰的拉格朗日松弛法

本文给出了一个布线后减小串扰噪声的算法。该算法通过调整逻辑门和互连线的尺寸有效地减小了串扰噪声,在减小噪声的同时约束电路的最大延时,使得在串扰噪声和时序都满足约束的条件下最小化芯片面积。算法保证了改变逻辑门和线网尺寸不会破坏电路的时序约束。实验结果证明,本算法有效地减小了串扰。此算法不需回到布线阶段来优
优化串扰,减少了设计迭代次数,加快了设计收敛时间。     

信号相关的串扰优化详细布线

针对超深亚微米IC布线设计中的串扰问题,提出基于改进遗传算法的串扰优化的详细布线方法．该方法同时考虑了产生串扰的动态和静态的因素,能够更加准确地反映线间串扰的情况,为布线的调整提供更大的余地．实验证明,该方法不但比现有的方法能更好地减少线间串扰,而且改进的遗传算法能显著地减少繁衍代数和运算时间。     

线外串扰与10G以太网的发展

近3年来，线外串扰已成为局域网布线领域的讨论热点，人们对这一话题在2大阵营中的观点截然不同。本文意在梳理争论双方论点，并帮读者得出如何处理线外串扰和10G以太网问题的方法。[第一段]     

防串扰的3D芯片TSV自动布局

为了防止3D芯片中的硅过孔(TSV)串扰,提出一种TSV自动排布算法.该算法结合TSV串扰的机理,利用Comsol证明了通过接地TSV解决屏蔽方法的有效性,完成了对接地TSV屏蔽效果的量化;提出电源/接地TSV和信号TSV自动排布算法,其中考虑了不同类型TSV比例和工艺最小间距对3D芯片性能的影响.最后利用IBM基准电路进行仿真,结果表明,文中算法可以防串扰的目的对电路中TSV进行自动布局.     

基于HyperLynx的电视跟踪系统信号完整性分析

在HyperLynx环境下,对反射和串扰这两种常见的信号完整性问题进行了仿真分析,提出了反射和串扰的抑制方案以及差分线的布线策略,在此基础上对以TS201为核心的电视跟踪系统的设计进行了改进。测试结果表明,在系统设计中进行有效的端接和合理的布局布线,可以提高信号的传输质量,避免和减小信号完整性问题。     

验证万兆以太网布线系统

布线验证过程概述万兆的验证过程包括两个阶段：（1）需要验证每个链路是否符合万兆的布线链路规格;（2）需要测量和评估布线安装的外部串扰性能。外部串扰是指不同的相邻布线链路中线对之间发生的耦合,请参见图1。该串扰是双绞线的一个亟待解决的难题,因为对于采用双绞线布线的1OGbE应用场合而言,它是最主要的干扰或噪音源。     

串扰时延故障的SAT-ATPG算法研究

随着芯片运行速度不断提高,对串扰时延的测试已成为一个迫切需要解决的问题;文中提出一种面向多条攻击线的受害线上最大串扰噪声的测试生成方法;此方法建立了串扰通路时延故障模型、分析了布尔可满足性问题、讨论了七值逻辑,研究了串扰时延故障测试转换为CNF的逻辑表达式,在非鲁棒测试条件下约简CNF范式,并提出了串扰时延故障的SAT-ATPG算法;最后通过实例分析,对本文算法进行验证;结果表明:该算法对串扰时延故障的测试矢量的生成是有效的。     

应用防护线抑制非平行微带线间串扰的研究

针对非平行微带线间的串扰问题,研究了防护线对抑制非平行微带线间串扰的效果,提出了根据非平行微带线间边缘场的主要耦合区域应用防护线的方法;理论分析与仿真结果表明,与铺设同干扰线等长的防护线相比,采用在非平行微带线间边缘场的主要耦合区域使用防护线的方法可以在起到同等抑制串扰效果的情况下,节约一部分防护线及其相应的接地过孔;该方法提高了应用防护线的效率,有助于预留出更多的可用布线空间,同时也有利于降低印制电路板生产成本。     

A parallel genetic algorithm for performance-driven VLSI routing

This paper presents a novel approach to solve the VLSI (very large scale integration) channel and switchbox routing problems. The approach is based on a parallel genetic algorithm (PGA) that runs on a distributed network of workstations. The algorithm optimizes both physical constraints (length of nets, number of vias) and crosstalk (delay due to coupled capacitance). The parallel approach is shown to consistently perform better than a sequential genetic algorithm when applied to these routing problems. An extensive investigation of the parameters of the algorithm yields routing results that are qualitatively better or as good as the best published results. In addition, the algorithm is able to significantly reduce the occurrence of crosstalk     

Priority-Based Routing Resource Assignment Considering Crosstalk

Crosstalk has become one of the most critical concerns in very deep sub-micron era. This paper deals with the problem of crosstalk mitigation at both methodological and algorithmic levels. Noting that intermediate operations between global routing and detailed routing are very effective in crosstalk estimation and reduction, the authors propose to incorporate several intermediate steps that are separated in traditional design flow into an integrated routing resource assignment stage, so that the operations could easily cooperate to fully exert their power on crosstalk reduction. An efficient priority-based heuristic algorithm is developed, which works slice by slice. Crosstalk avoidance, and many other aspects that are critical in routing practice including congestion, vias, layer preference, etc., are taken into account. A track reservation strategy is adopted in the algorithm framework to compensate the undesired effects caused by sequential routing. Experimental results on a series of ISPD98 and industrial benchmarks show that the proposed approach is able to reduce capacitive crosstalk by about 70% on average without compromising completion ratio compared with a previously reported graph based algorithm, demonstrating the advantages of the approach.     

A metaheuristic approach for optical network optimization problems

Two of the most complex optimization problems encountered in the design of third generation optical networks are the dynamic routing and wavelength assignment (DRWA) problem under the assumptions of ideal and non-ideal physical layers. Both these problems are NP-complete in nature. These are challenging due to the presence of multiple local optima in the search space. Even heuristics-based algorithms fail to solve these problems efficiently as the search space is non-convex. This paper reports the performance of a metaheuristic, that is, an evolutionary programming algorithm in solving different optical network optimization problems. The primary motivation behind adopting this approach is to reduce the algorithm execution time. It is demonstrated that the same basic approach can be used to solve different optimization problems by designing problem-specific fitness functions. Also, it is shown how the algorithm performance can be improved by integrating suitable soft constraints with the original constraints. Exhaustive simulation studies are carried out assuming the presence of different levels of linear impairments such as switch and demultiplexer crosstalk and non-linear impairments like four wave mixing to illustrate the superiority of the proposed algorithms.     

Crosstalk-Aware Routing Resource Assignment

Crosstalk noise is one of the emerging issues in deep sub-micrometer technology which causes many undesired effects on the circuit performance. In this paper, a Crosstalk-Aware Routing Resource Assignment (CARRA) algorithm is proposed, which integrates the routing layers and tracks to address the crosstalk noise issue during the track/layer assignment stage. The CARRA problem is formulated as a weighted bipartite matching problem and solved using the linear assignment algorithm. The crosstalk risks between nets are represented by an undirected graph and the maximum number of the concurrent crosstalk risking nets is computed as the max clique of the graph. Then the nets in each max clique are assigned to disadjacent tracks. Thus the crosstalk noise can be avoided based on the clique concept. The algorithm is tested on IBM benchmarks and the experimental results show that it can improve the final routing layout a lot with little loss of the completion rate.     

一种FPGA抗辐射布线算法设计

随着集成密度的增大以及工作电压的降低,基于SRAM的FPGA芯片更加容易受到单粒子翻转的影响。提出了一种基于通用布局布线工具VPR的抗辐射布线算法,通过改变相关布线资源节点的成本函数,来减少因单粒子翻转引起的桥接错误,并与VPR比较下板测试结果。实验结果表明,该布线算法可以使芯片的容错性能提升20%左右,并且不需要增加额外的硬件资源或引入电路冗余。     

High-performance MCM routing

The authors describe the multilayer MCM (multichip module) routing problem, and propose an approach for routing high-performance MCMs with the objective of minimizing interconnect delays and crosstalk. They first introduce an approach for rapidly estimating the time-domain response of lossy transmission line trees, and propose a realistic second-order delay model for MCM interconnects. The delay model is used to guide a performance-driven global routing algorithm. Given the 2-D global paths, the next stage is layer assignment. An effective algorithm for constrained layer assignment is developed. Based on the best-known maxcut approximation algorithm (which performs well in practice), a maximal k-color ordering is formulated for minimizing both interlayer and intralayer crosstalk as well as crossings in 3-D MCM substrates. The authors also propose a strategy that exhibits a good tradeoff between circuit performance and design cost, instead of concentrating exclusively on a single objective such as area minimization     

用PSO优化基于QoS的WSN路由协议

在过去的10年中,提供服务质量(QoS)保证的路由协议很好的用在了有线网络中,随着无线传感网络(WSN)的广泛使用,就需要考虑如何在无线传感网络中实现QoS的效率.很多QoS度量值都需要被考虑,如数据包时延、带宽效率、能量消耗等.同时QoS也受路由的影响,由于路由解空间随着网络的规模变大而呈指数级的增长,研究路由协议算法的效率就成为一个必然.在研究了智能粒子群最优算法(PSO)后,提出了一个基于PSO的路由算法,不仅考虑了QoS的需求同时也有一个不错的搜索能力.仿真结果表明,与一些典型QoS常规机制比较基于粒子群最优路由算法是有效的.