A direct-conversion receiver IC for WCDMA mobile systems

A prototype design of a 2.7-3.3-V 14.5-mA SiGe direct-conversion receiver IC for use in third-generation wide-band code-division multiple-access (3G WCDMA) mobile cellular systems has been completed and measured. The design includes a bypassable low-noise amplifier (LNA), a quadrature downconverter, a local-oscillator frequency divider and quadrature generator, and variable-gain baseband amplifiers integrated on chip. The design achieves a cascaded, LNA-referred noise figure (including an interstage surface acoustic wave filter) of 4.0 dB, an in-band IIP3 of -18.6 dBm, and local-oscillator leakage at the LNA input of -112 dBm. The static sensitivity performance of the receiver IC is characterized using a software baseband processor to compute link bit-error rate.     

A dual-band direct-conversion RF front-end for WiMedia UWB receiver

This paper describes a direct-conversion RF front-end designed for a dual-band WiMedia UWB receiver. The front-end operates in band group BG1 and BG3 frequencies. It includes multi-stage LNAs, down-conversion mixers, a polyphase filter for quadrature local oscillator (LO) signal generation, and LO buffers. The UWB receiver is targeted for a mobile handset, where several other radios can be simultaneously on. Therefore, special attention was paid on minimizing the interference from different wireless systems. The front-end achieves approximately 26-dB gain and 4.9–5.6-dB noise figure (NF) across three sub-bands of BG1. In BG3 mode it obtains 23–26-dB gain and 6.9–7.7-dB NF. The front-end consumes 48.1 and 42.7 mA from a 1.2-V supply voltage in BG1 and BG3 operation modes, respectively. The chip was implemented in a 0.13-μm CMOS.     

A direct-conversion receiver for the 3G WCDMA standard

A highly integrated direct-conversion receiver that satisfies requirements of the third-generation wide-band code-division multiple-access mobile phone standard is described. The receiver integrated circuit includes the front-end low-noise amplifier, downconversion mixers, baseband variable-gain amplifiers, channel-select filters, and the frequency synthesizer. External components are limited to matching elements required for the low-noise amplifier and the mixers and two passive band-select filters. The receiver is implemented in a SiGe BiCMOS process and consumes a total current of 46 mA from a 2.7-V supply.     

A CMOS passive mixer with low flicker noise for low-power direct-conversion receiver

A CMOS passive mixer is designed to mitigate the critical flicker noise problem that is frequently encountered in constituting direct-conversion receivers. With a unique single-balanced passive mixer design, the resulted direct-conversion receiver achieves an ultralow flicker-noise corner of 45 kHz, with 6 dB more gain and much lower power and area consumption than the double-balanced counterpart. CMOS switches with a unique bias-shifting network to track the LO DC offset are devised to reduce the second-order intermodulation. Consequently, the mixer's IIP2 has been greatly enhanced by almost 21 dB from a traditional single-balanced passive mixer. An insertion compensation method is also implemented for effective dc offset cancellation. Fabricated in 0.18 /spl mu/m CMOS and measured at 5 GHz, this passive mixer obtains 3 dB conversion gain, 39 dBm IIP2, and 5 dBm IIP3 with LO driving at 0 dBm. When the proposed mixer is integrated in a direct-conversion receiver, the receiver achieves 29 dB overall gain and 5.3 dB noise figure.     

Improved four-channel direct-conversion SiGe receiver IC for UMTS base stations

This work presents the design and measurement results of an improved four-channel, direct down conversion receiver (DCR) for the application in universal mobile telecommunications system base stations. The whole analog receiver functionality including low noise amplifier, variable gain amplifier, local oscillator frequency divider, in-phase and quadrature DCR mixers and seventh-order active lowpass filter is integrated using Atmel's 50-GHz f/sub t/, 50-GHz f/sub max/ SiGe foundry technology (Atmel, 1998). Important cascaded design parameters of the fully ESD-protected device are a noise figure 1.5 to 2 dB; IIP3 (third-order intercept point) -20.3 to -15.8 dBm and a voltage gain of 51 to 57 dB into a 1000-/spl Omega/ /spl par/ 2.5-pF differential load [analog to digital converter].     

A new CMOS channel select filter for dual mode bluetooth/WLAN direct-conversion receiver

Design of a CMOS 4th-order channel select filter for integrated dual mode Bluetooth/WLAN direct-conversion receiver is presented. The bandwidth of the filter can be programmed from 200 kHz to 8 MHz to accommodate both standards. The proposed filter provides low power, and small area design solution. Post-layout simulation results show that the filter satisfies the selectivity and dynamic range requirements of both applications while consuming total standby power of 1.88 mW.     

A micropower CMOS, direct-conversion, VLF receiver chip formagnetic-field wireless applications

A micropower CMOS, direct-conversion very low frequency (VLF) receiver is described for receiving low-level magnetic fields from resonant sensors. The single-chip, phase locked loop (PLL)-synthesized receiver covers a frequency range of 10-82 kHz and provides both analog and 9-b digital baseband I and Q outputs. Digital I and Q outputs are accumulated in a companion digital chip which provides baseband signal processing. Emphasis is plated on the receiver micropower RF preamplifier which uses a lateral bipolar input device because of the significant increase in flicker noise illustrated for PMOS devices in weak inversion. Lateral bipolar transistors are also utilized in the mixer and IF stages for low flicker noise and low dc offsets. Special attention is given to isolating the internal local oscillator signals from the low-level RF input (0.3 μV noise floor in 300 Hz BW), and local oscillator feedthrough is indiscernible in the RF preamplifier output noise spectrum. The 100% duty-cycle receiver, intended for miniature, battery-operated wireless applications, operates approximately four months at 80 μA from a 6-V, 220-mA-hr battery     

A single-chip 2.4-GHz direct-conversion CMOS receiver for wirelesslocal loop using multiphase reduced frequency conversion technique

A single-chip direct-conversion CMOS receiver for 2.4-GHz wide-band code-division multiple-access wireless local loop (WLL) is described. The chip includes a low noise amplifier, a 12-phase downconverter, a variable gain amplifier, a g_m-C channel selection filter, a programmable phase-locked loop for seven channel frequencies, and a 4-bit flash analog-to-digital converter. The proposed multiphase reduced frequency conversion scheme combined with a multiphase sampling fractional-N prescaler, a cascaded dc-offset canceler and distributed automatic gain control loops offers solutions to problems of a direct-conversion receiver. Experimental results show -115-dBm sensitivity, 4.4-dB noise figure, and 95-dB dynamic range, which sufficiently meet commercial WLL specification     

Modeling and analysis of nonlinearities and mismatches in AC-coupled direct-conversion receiver

This paper analyzes the effects of circuit nonlinearities and mismatches on the performance of an AC-coupled direct-conversion receiver (DCR). An analytical solution is necessary, since quantifying the DCR performance by simulation can be prohibitively slow. Our analysis approach first transforms the receiver front end to an equivalent baseband continuous-time receiver model with all of the noise sources referred to just before the sampler. Accurate approximations were made throughout this process to make the analysis tractable. The baseband continuous-time model can be further simplified and combined with the baseband equivalent propagation channel model. The resulting model allows the end-to-end performance of an ac-coupled DCR to be quickly and accurately quantified.     

A 17-mW 0.66-mm/sup 2/ direct-conversion receiver for 1-Mb/s cable replacement

A very-low-cost wireless personal area network (WPAN) receiver implemented in 0.25-/spl mu/m CMOS technology consumes 17mW of power and occupies an area of 0.66 mm/sup 2/. Simplicity in the physical layer, which still supports the 1-Mb/s requirement, allows for power savings in the receive front-end. A new coding scheme permits the integration of a high-pass filter to mitigate DC offset and 1/f noise. A linear front-end eliminates the external band-preselect filter. This die area is the smallest reported for Bluetooth-class front-ends.     

A CMOS channel-select filter for a direct-conversion wirelessreceiver

A highly selective and linear switched-capacitor channel-select filter is fabricated in 1-μm CMOS for a direct-conversion wireless receiver operating in the 902-928 MHz ISM band. The filter selects a 230-kHz wide channel and attenuates by at least 50 dB from 320 kHz to 57 MHz. The input IP3 is +30 dBm, the input-referred noise in the passband is 70 nV/√Hz, and the circuit takes 4.6 mA from a 3.3 V supply. Direct subsampling of the 915 MHz RF input signal by the filter front-end is also demonstrated with only a small degradation in linearity. The input noise voltage is halved in a redesign while keeping the current drain unchanged     

手持产品上实现DVB-H数字电视

简介 目前,很多公交车辆、出租车上都安装了数字电视,这种电视采用的技术就是DVB-T(数字视频广播-地面标准).DVB-T功耗比较大,不适合电池供电的移动终端使用.为此,在DVB-T的基础上引入新的技术,形成适合于移动终端接收地面数字电视节目的传输标准DVB-H(数字视频广播-手持).与DVB-T相比,DVB-H终端具有更低的功耗,移动接收和抗干扰性能更为优越.     

A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.     

A fully integrated CMOS direct-conversion transmitter front-end for WiMAX

A naturally commutated six-pulse cycloconverter working in the inverting mode is used to feed power to a single phase AC motor at 400 Hz. The motor is connected at the input side of the cycloconverter while the three-phase mains is connected at its output. Three-phase mains feeds power to the input side of the cycloconverter which is arranged as a tuned load at 400 Hz. The effect of the single-phase induction motor on system performance is discussed. The principle of voltage and frequency control for proper operation of the induction motor is presented. The results are experimentally verified.     

A 5-GHz direct-conversion CMOS transceiver

A CMOS transceiver fully compliant with IEEE 802.11a in the unlicensed national information infrastructure (UNII) band (5.15-5.35 GHz) achieves a receiver sensitivity of -5 dBm for 64-QAM (quadrature amplitude modulation) with an error vector magnitude (EVM) of -29.3 dB. A single-sideband mixing technique for local-oscillator signal generation avoids frequency pulling. Realized in 0.18-/spl mu/m CMOS and operating from 1.8-V power supply, the design consumes 171 mW in receive mode and 135 mW in transmit mode while occupying less than 13 mm/sup 2/.     

DVB-H技术专利分析

近年来,移动多媒体正日益深入人们的日常生活,“手机电视”成为谈论的热点.DVB-H是一种实现手机电视业务的国际标准,是建立在DVB和DVB-T之上的传输标准.对DVB-H技术相关的中国专利申请进行了统计分析,包括申请类型分析、申请时间分析、申请人国别/地区分析以及主要申请人分析,介绍了DVB-H在中国的专利申请现状.     

A W-band high-power predistorted direct-conversion digital modulator for transmitter applications

This letter presents a W-band high-power direct-conversion transmitter using digital predistortion techniques for digital modulation applications. The transmitter is a direct-conversion configuration that employs a reflection-type IQ modulator module and a power amplifier module. With the predistortion function in digital signal processing (DSP), this transmitter demonstrated an output channel power of greater than 19 dBm, and the adjacent channel power ratio (ACPR) was improved by 10 and 18 dB for QPSK and /spl pi//4-DQPSK modulation, respectively. To the best of our knowledge, this is the first demonstration of linearization techniques for W-band high-power digital modulation transmitters.     

DVB-H近况

1前言 自从上世纪90年代后期,欧洲的数字电视广播进入实验阶段以来,欧洲长期把重点放到数字SDTV的多频道广播,曾经认为数字HDTV是不必要的.但随着广播电视数字化的深入发展,从去年夏季以来,在欧洲广播业界产生了一个极大的变化,就是社会上不仅对HDTV表示了极大地兴趣,而且HDTV已形成现实的媒体形式.目前,欧洲部分业者已开始HDTV广播,一些国家也开始着手投入HDTV业务.     

A 1 GHz CMOS RF front-end IC for a direct-conversion wirelessreceiver

An integrated low-noise amplifier and downconversion mixer operating at 1 GHz has been fabricated for the first time in 1 μm CMOS. The overall conversion gain is almost 20 dB, the double-sideband noise figure is 3.2 dB, the IIP3 is +8 dBm, and the circuit takes 9 mA from a 3 V supply. Circuit design methods which exploit the features of CMOS well suited to these functions are in large part responsible for this performance. The front-end is also characterized in several other ways relevant to direct-conversion receivers