A theoretical and experimental analysis of the buried-source VMOS dynamic RAM cell

The buried-source dynamic RAM cell combines a VMOS transistor (VMOST) and a buried junction capacitor to make a one-transistor cell (1TC) providing large storage capacitance, long charge retention, and high density. The threshold voltage, breakdown voltage, and weak inversion current for the forward and reverse modes of operation of the VMOST and the junction capacitance are experimentally related to the nonuniform doping profile of the channel. Equations are developed for the VMOST short-channel threshold voltage and storage capacity of the cell. The charge capacity (per unit of cell area) of the buried-source cell is calculated to be 2.5 times that of the conventional 1TC cell. The cell charge retention time was measured at more than 1 s at 100°C, proving operation of the device as a dynamic memory element. The technology is capable of producing an 80-µm²cell using 4-µm minimum features, no cell contacts, and a single level of interconnect.     

A survey of high-density dynamic RAM cell concepts

The performance capabilities of a variety of dynamic RAM cell concepts proposed in recent years are compared to the industry standard one-transistor cell. The new concepts are divided into three categories. The lateral charge sensing cells such as the Charge-Coupled cell, Hi-C cell, Merged-Charge cell, and Stacked-Capacitor cell. Vertical cells such as VMOS, the Punchthrough Isolated, and the Buried-Bit-Line cell which make use of the third dimension to achieve higher density. The Stratified-Charge cell and Taper-Isolated cell use current sensing of a dynamic change in the threshold voltage of a buried-channel transistor. The various cells were fabricated and compared on the basis of signal size, leakage rates, packing density, and fabrication and operational complexity. An overall figure of merit for a dRAM cell is suggested which combines all three considerations. Based on the cell concepts reported to date and this figure of merit, the Stacked-Capacitor, VMOS, and Punchthrough-Isolated cells ate the most promising charge storage cells. The Taper-Isolated cell, however, is shown to have significant overall advantage compared to the charge storage cells.     

An 8K/spl times/8 dynamic RAM with self-refresh

The device uses a standard NMOS one-transistor cell and is fabricated with a double polysilicon HMOS technology using polysilicon word lines and folded metal bit lines. Self-refresh is implemented with an on-chip timer, arbiter, and refresh counter. A high-speed arbiter resolves conflicts between refresh cycles and memory accesses. A `ready' output is provided to the processor. A multiplexed bus is provided in the array to carry column addresses and also I/O data paths. Another multiplexed bus is used for data lines between the input buffers, write buffers, secondary sense amplifiers, and output buffers. Redundant rows and columns are used for increased manufacturing yield. Polysilicon fuses are electrically programmed to select redundant elements.     

A 16 384-bit dynamic RAM

A 16-kbit dynamic RAM is described which is TTL compatible on all pins, and fits a standard 16-pin package. A single-transistor storage cell is used which occupies 455 /spl mu/m/SUP 2/. The device is fabricated in n-channel two-layer polysilicon gate technology using conventional design rules. The chip size is 145 by 234 mils. A low-power sense amplifier is used for each 64 memory cells. A special refresh mode is possible in which all 256 sense amplifiers are active, and the entire memory can be refreshed in 64 address cycles.     

A 64-kbit dynamic MOS RAM

A 64-kbit dynamic MOS RAM is developed by using 2 /spl mu/m rule VLSI fabrication technology and low power circuit technology. The 2 /spl mu/m rule VLSI fabrication technology is achieved by improving various aspects of the ultraviolet photolithographic, thin-gate oxidation, arsenic ion implantation, and multilevel interconnection processes. Microminiaturization of the device structure has made the voltage requirements for its MOST threshold voltage and DC supply voltages low. A highly sensitive and low power dissipating sense circuit has been developed for the VLSI RAM. A new level-detecting circuit with a logic threshold which is independent of MOST threshold voltage is proposed. A dynamic address-buffer circuit is also shown. The fabricated 64K RAM has 200 ns of access time, 370 ns of minimum cycle time, and 150 mW of power dissipation under typical supply voltage conditions of V/SUB DD/=7 V and V/SUB BB/=-2 V.     

A dynamic RAM Cell in recrystallized polysilicon

A new, one-transistor, dynamic RAM cell has been fabricated in beam-recrystallized polysilicon. Placing thin oxides both above and below the storage region doubles the storage capacitance. Complete isolation of the storage region by oxides also reduces the susceptibility of the cell to soft errors from collection of charge injected into the substrate by the surrounding elements or by alpha particles. Long storage times are feasible, being limited only by the leakage of the access transistor. A thick oxide under the bit line reduces the bit-line capacitance, further increasing the ratio of storage capacitance to bit-line capacitance.     

New dynamic RAM Cell for VLSI memories

A novel high-alpha-particle-immunity and high-density dynamic RAM cell with readout signal gain is proposed. The cell is composed of a MOSFET for charge transfer, a MOS capacitor for charge storage and a junction FET (JFET) with buried channel under the MOS capacitor. The buried channel is dynamically switched according to whether there is charge-storage or not. The cell has extremely small collection efficiency for charges generated by alpha-particles, and allows a large amount of leakage charges due to its peculiar structure. Thus, it can achieve high packing density.     

The charge-coupled RAM cell concept

A new concept in MOS dynamic RAM cells is described and demonstrated. The charge-coupled RAM (CC RAM) cell combines the storage capacity and transfer gate of the one-transistor cell into a single gate. The resulting cell is simpler than the conventional one-transistor cell and possesses significant advantages in packing density and potentially higher yield. One of the variations of the CC RAM cell concept results in a cell whose operation is identical (voltage and timing) to that of the present one-transistor cell. In addition, the CC RAM cell fabrication is essentially the same as the present one-transistor cell process. The CC RAM is an attractive candidate for the next generation RAM's.     

The collector-coupled static RAM cell

The collector-coupled static RAM cell uses a schottky collector transistor switch with merged vertical n-p-n load. The cell is constructed with two dual Schottky collector transistors and one merged dual collector n-p-n transistor. It has been fabricated in an infant oxide isolated bipolar technology and bistability has been demonstrated over four orders of magnitude in cell current (10 nA相似文献   

The charge-coupled RAM cell concept

A new concept in MOS dynamic RAM cells is described and demonstrated. The charge-coupled RAM (CC RAM) cell combines the storage capacity and transfer gate of the one-transistor cell into a single gate. The resulting cell is simpler than the conventional one-transistor cell and possesses significant advantages in packing density and potentially higher yield. One of the variations of the CC RAM cell concept results in a cell whose operation is identical (voltage and timing) to that of the present one-transistor cell. In addition, the CC RAM cell fabrication is essentially the same as the present one-transistor cell process. The CC RAM is an attractive candidate for the next generation RAM's.     

The Hi-C RAM cell concept

This paper addresses a new MOS high-capacity dynamic RAM cell concept called the high capacity (Hi-C) RAM cell. This cell combines the charge-coupled RAM cell with the one-transistor (1-T) or double-level polysilicon (DP) structure, and its operation is identical to that of conventional dynamic RAM cells. A charge-capacity analysis was undertaken which indicates that the Hi-C cell has a charge storage capacity per unit area 50-100 percent greater than that of the regular 1-T or DP cells. It is also expected to have a leakage current lower than that of the 1-T and DP cells. Results of measurements on the first test structures show a 45-80-percent increase in charge capacity and up to 3× reduction in leakage current. In addition, the implant doses can be conveniently chosen so that the charge capacity of the Hi-C cell is maximized and independent of the n-type implant dose in the storage region. This is important regarding manufacturability. This new cell structure represents a significant breakthrough in increased charge capacity and decreased leakage current which should very favorably impact dynamic RAM packing density.     

Charge capacity analysis of the charge-coupled RAM cell

The charge (or storage) capacity of the dynamic charge-coupled (CC) random access memory (RAM) cell is analyzed. Theoretical expressions for the capacity are developed which provide excellent agreement between theory and experiment. Test devices were operated with typical dynamic metal-oxide-semiconductor (MOS) RAM voltages, and exhibited charge capacities (per unit area) up to 52 and 86 percent of that of the conventional one-transistor cell for substrate bias voltages of -5 and -1 V, respectively. A simplified model of the CC RAM cell is used to illustrate the dependence of the charge capacity on the device and operating parameters. This model is useful for defining the limitations on capacity and for comparing the capacities of the CC and the one-transistor cells for a variety of conditions. In general, the CC RAM cell charge capacity per unit area ranges from 50 to over 100 percent of that of the one-transistor cell for conventional device parameters. A somewhat higher range applies for projection to low-voltage and very high-density RAM's.     

A three-dimensional folded dynamic RAM in beam-recrystallized polysilicon

A three-dimensional folded one-transistor dynamic RAM circuit consisting of an access transistor in a beam-recrystallized polysilicon layer above a storage capacitor has been fabricated. Large cell capacitance and low transistor leakage are obtained by use of multiple polysilicon layers and by folding the storage capacitor beneath the access transistor. The resulting storage times are longer than 1 min, several orders of magnitude greater than storage times in a previously published nonfolded dynamic RAM in recrystallized polysilicon [1].     

A new architecture for the NVRAM-an EEPROM backed-up dynamic RAM

An architecture for a nonvolatile RAM (NVRAM) suitable for high-density applications is described. In the cell, a dynamic RAM cell is merged into an EEPROM cell. A capacitor is constructed between the control gate and the drain diffusion layer of the FLOTOX-type EEPROM memory cell. The equivalent circuit in the dynamic RAM mode consists of two transistors and a capacitor, which eliminates a dummy cell. A dynamic RAM sense amplifier is used in both modes, and it works as a data latch when data are transferred between the dynamic RAM and the EEPROM. The process of the NVRAM is compatible with ordinary EEPROMs     

A 256K dynamic RAM with page-nibble mode

A 5-V 256K /spl times/ 1 bit NMOS dynamic RAM with page-nibble mode is designed and fabricated using 2-/spl mu/m design rules and folded bit-line configuration. Molybdenum disilicided polysilicon is used as the second-level gate to reduce the word-line signal delay. A large 98 /spl mu/m/SUP 2/ cell with Hi-C structure stores the signal charge of 210 fC and provides this memory with wide operating margin. The device is immune to voltage bumping and uses laser programmable redundancy. Typical RAS/CAS access times are 80 ns/40 ns. An average operating current of 50 mA with 80 mA peak at 230 ns cycle time and standby current of 2 mA are achieved.     

An asynchronous GaAs MESFET static RAM using a new current mirrormemory cell

An experimental 1-kb GaAs MESFET static RAM using a new memory cell has been designed, fabricated and tested. The new memory cell is not subject to the destructive read problems that constrain the design of the conventional six-transistor memory cell. The biasing arrangement for this new cell minimizes the leakage currents associated with unselected bits attached to a column, maximizing the number of bits allowed per column. This new memory cell also provides a much larger access current for readout than is possible using a conventional memory cell of the same area and cell power. A write time of 1.0 ns and address access times of between 1.0 and 2.3 ns have been obtained from a 1-kb test circuit. A cell area of 350 μm² and cell current of 60 μA were achieved using a conventional E/D process     

Use of dynamic RAM in a portable data recorder

A portable ECG recorder using dynamic RAM as the recording medium has been developed. The dynamic RAM interface hardware which includes three types of communication mode, that is to a PC, a microcontroller (MCS-51) and an A/D subsystem (AD7821) with dynamic RAMs, is described. This technique opens a new path to the development of low cost, small size and large capacity long-term physiological data recorders.<>     

A vertically integrated GaAs bipolar dynamic RAM cell with storagetimes of 4.5 h at room temperature

The storage times of FET-accessed GaAs dynamic RAM cells are limited to less than 1 min at room temperature by gate leakage in the access transistor. These transistor leakage mechanisms have been eliminated by designing a vertically integrated DRAM cell in which an n-p-n bipolar access transistor is merged with a p-n-p storage capacitor. Storage times of 4.5 h are obtained at room temperature, a 1000-fold increase over the best FET-accessed cells     

Static RAM cell for ternary logic

A novel CMOS static RAM cell for ternary logic systems is described. This cell is based on the lambda diode. The operation of the cell has been simulated using the SPICE 2G program. The results of the simulation are given.