Optical phase division multiplexing for local communicationsapplications

A local fiber bus system is described wherein many users sequentially phase-modulate the output of a single light source. Since the modulated signal has a constant envelope, optical amplifiers can be used to boost the signal power along the bus to a level sufficient for reliable detection. Also, since a single laser source is used, a higher quality device (for example, with small linewidth) is more readily affordable. This system is analyzed to determine the limits of performance due to noise. The analysis indicates that many wideband signals could be accommodated if noise sources only, rather than signal distortions caused by nonideal optical devices, were the limiting factor. For example, with optical amplifiers distributed along the bus, this system can support 1000 10-MHz users     

浅析CAN总线双子网拓扑优化结构

文章从分析CAN 2.0B总线协议入手,通过计算CAN总线的总线负载率,得出单个CAN总线传输报文帧的上限值。针对单个CAN总线不能满足通信需求的问题,提出了将网络节点划分在两个子网中的优化方法,最后,介绍了将本方法应用于优化某模拟CAN总线节点的例子。     

低冗余并行总线容错技术

本文将从分析Ｍｕｌｔｉｂｕｓ总线功能入后，讨论多种总线容错技术及实时重构总线系统的方法，并具体分析各种容错技术对可靠性指标的影响程度。     

Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses

This paper purposes a bus architecture called skewed repeater bus (SRB) for reducing on-chip interconnect energy in microprocessors. By introducing a dynamic relative delay between neighboring bus lines, SRB reduces both average and worst-case coupling capacitance between those lines. SRB is compared to previously published techniques like delayed data bus (DDB) and delayed clock bus (DCB). Simulation results in 65-nm process show that bus energy reduction of 18% is achieved when SRB is applied to a real microprocessor example, versus 11% and 7% only for DDB and DCB, respectively.      

基于SJA1000的雷达信号处理机接口设计

SJA1000芯片是Philips公司的一种有效支持分布式控制或实时控制的CAN总线控制器芯片.介绍了采用SJA1000芯片的雷达信号处理机接口的硬件设计和软件设计,给出了发送节点的程序流程.     

Analysis of effective power budget in optical bus and star networksusing erbium-doped fiber amplifiers

The use of erbium-doped fiber optical amplifiers (EDFAs) in bus and star networks is studied. The number of stations that can be supported with and without amplifiers in a single folded bus, a double bus, and a star is determined. For a typical case, when only one station on the bus is allowed to transmit at a time, as is the case in a time-division multiplexed network, the number of stations that can be supported with amplifiers is on the order of several thousands. This number drops to less than a thousand when all stations are allowed to transmit simultaneously on different channels in a wavelength-division multiplexed network, because of amplifier gain saturation. In the former case, the bus has the potential to outperform the star, but in the latter case, the star topology is still better     

基于I2C总线进行单片机系统扩展的探讨

结合单片机的应用实践,阐述了I2C总线应用的分类,探讨了基于I2C总线如何进行单片机系统扩展的几点体会。     

Resource constrained scheduling of uniform algorithms

A method for optimizing the schedule and allocation of uniform algorithms onto processor arrays is derived. The main results described in the following paper are: (1) single (integer) linear programs are given for the optimal schedule of regular algorithms with and without resource constraints, (2) the class of algorithms is extended by allowing certain non-convex index domains, (3) efficient branch and bound techniques are used such that problems of relevant size can be solved. Moreover, additional constraints such as cache memory, bus bandwidths and access conflicts can be considered also. The results are applied to an example of relevant size.     

FlexRay总线在模块化通信导航识别系统中的应用

针对新型模块化通信导航识别( MCNI)系统对高质量数据通信的实际需求,从总线速率、实时性、可靠性、可扩展性等方面分析了现有几型总线存在的适配性问题,提出将新一代FlexRay总线技术应用到MCNI系统中,构建了基于双通道冗余拓扑构型的全新的MCNI系统总线架构,并给出了总线时隙分配和硬件框图。实验结果表明FlexRay总线传输速率可达10 Mb/s,能在重负荷情况下为MCNI系统提供实时可靠的信息交互,可为其他模块化传感器系统总线设计提供借鉴。     

Bus guardians: an effective solution for online detection andcorrection of faults affecting system-on-chip buses

This paper presents a methodology for designing system-on-chip (SOC) interconnection architectures providing a high level of protection from crosstalk effects. An event driven simulator enriched with fault injection capabilities is exploited to evaluate the dependability level of the system being designed. The simulation environment supports several bus coding protocols and, thus, designers can easily evaluate different design alternatives. To enhance the dependability level of the interconnection architecture, we propose a distributed bus guardian scheme, where dedicated hardware modules monitor the integrity of the information transmitted over the bus and provide error correction mechanisms     

基于DSl820的单总线多点测温技术

阐述了通过单总线测温元件DSl820来实现多点测温的技术,实现方法是利用DSl820和89C51单片机构建单线多点温度测控系统,通过软件对单片机进行控制,从而实现一根总线多点测温,达到理想的测温效果。实验结果表明,该测控技术具有测温系统简单,测温精度高,连接方便,占用口线少等优点。该技术的创新主要在于能够利用一个通信接口同时监测几个甚至几十个温度数据,从而达到节省带宽,简化硬件设施的目的。     

数据通信总线技术的现状与未来发展趋势

文章结合中兴通讯ZXR10数据产品中通信总线实际应用情况,阐述了各种数据通信总线的工作时钟频率范围、带宽范围以及它们各自的优势和缺陷.文章认为并行总线由于自身缺陷,已经不适合进行高速传输,高速串行点对点连接将代替传统的并行接口;数据交换也不再是简单地通过驱动电路和并行数据线进行,而是通过特殊的串行高速总线连接;传统的在一条总线上同时挂载多个设备的模式正逐渐消亡,总线功能已被一个集中式的交换模块取代,而交换模块和各个设备都是通过高速串行点对点的方式进行连接.     

Power Consumption of Fault Tolerant Busses

On-chip interconnects in very deep submicrometer technology are becoming more sensitive and prone to errors caused by power supply noise, crosstalk, delay variations and transient faults. Error-correcting codes (ECCs) can be employed in order to provide signal transmission with the necessary data integrity. In this paper, the impact of ECCs to encode the information on a very deep submicrometer bus on bus power consumption is analyzed. To fulfill this purpose, both the bus wires (with mutual capacitances, drivers, repeaters and receivers) and the encoding-decoding circuitry are accounted for. After a detailed analysis of power dissipation in deep submicrometer fault-tolerant busses using Hamming single ECCs, it is shown that no power saving is possible by choosing among different Hamming codes. A novel scheme, called dual rail, is then proposed. It is shown that dual rail, combined with a proper bus layout, can provide a reduction of energy consumption. In particular, it is shown how the passive elements of the bus (bottom and mutual wire capacitances), active elements of the bus (buffers) and error-correcting circuits contribute to power consumption, and how different tradeoffs can be achieved. The analysis presented in this paper has been performed considering a realistic bus structure, implemented in a standard 0.13-mum CMOS technology.     

SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips

A high performance communication architecture, SAMBA-bus, is proposed in this paper. In SAMBA-bus architecture, multiple compatible bus transactions can be performed simultaneously with only a single bus access grant from the bus arbiter. Experimental results show that, compared with a traditional bus architecture, the SAMBA-bus architecture can have up to 3.5 times improvement in the effective bandwidth, and up to 15 times reduction in the average communication latency. In addition, the performance of SAMBA-bus architecture is affected only slightly by arbitration latency, because bus transactions can be performed without waiting for the bus access grant from the arbiter. This feature is desirable in SoC designs with large numbers of modules and long communication delay between modules and the bus arbiter     

基于CH365芯片的PCI总线接口卡的设计与实现

PCI总线是先进的高性能32/64位局部总线,是应用最广泛的微机总线标准之一。讨论了以CH365作为接口芯片的PCI总线接口卡的设计方法,并给出了一个ISA总线接口卡快速改造为PCI总线接口卡的实例。在设计中使用了CH365芯片特有的本地硬件地址请求功能及双口RAM读写的仲裁技术。设计的PCI接口板实现了预定的功能,具有较强的实用性和较高的市场推广价值。     

Memory accesses reordering for interconnect power reduction in sum-of-products computations

Techniques for interconnect power consumption reduction in realizations of sum-of-products computations are presented. The proposed techniques reorder the sequence of accesses of the coefficient and data memories to minimize power-costly address and data bus bit switching. The reordering problem is systematically formulated by mapping into the traveling salesman's problem (TSP) for both single and multiple functional unit architectures. The cost function driving the memory accesses reordering procedure explicitly takes into consideration the static information related to algorithms' coefficients and storage addresses and data-related dynamic information. Experimental results from several typical digital signal-processing algorithms prove that the proposed techniques lead to significant bus switching activity savings. The power consumption in the data paths is reduced in most cases as well.     

A family of high power density unregulated bus converters

This paper begins by reviewing current bus converters and exploring their limitations. Next, a family of inductor-less bus converters is proposed to overcome the limitations. In the new bus converters, magnetizing current is used to achieve zero-voltage-switching (ZVS) turn-on for all switches. The resonant concept is used to achieve nearly zero-current-switching (ZCS) turn-off for the primary switches and no body diode loss for the synchronous rectifiers (SRs). Meanwhile, the self-driven method can be easily applied to save drive loss of SRs. Based on these concepts, a full-bridge bus converter is built in the quarter-brick size to verify the analysis. The experimental results indicate that it can achieve 95.5% efficiency at 500-W, 12-V/45-A output. Compared with industry products, this topology can dramatically increase the power density. These concepts are also applied to nonisolated dc/dc converters. As an example, a resonant Buck converter is proposed and experimentally demonstrated.     

基于PCA82C250与MCU间的直连通信网络设计

在分析了RS-485总线与CAN总线的异同点后,以PCA82C250型接口电路为例提出了用CAN总线通信物理层接口电路来替代RS-485总线接口电路与单片机直接连接进行通信网络设计,从而可形成一个高性能、低价格且数据通信安全、可靠的分布式测控系统.     

Reliability Analysis of Fault-Tolerant Bus-Based Interconnection Networks

Multi-processor systems need interconnection networks (INs) in order to make the connection among the processors, memory modules, and nodes. Bus interconnection network is the simplest and least expensive one among all the INs. Therefore, bus network is easily understood and preferred by manufactures for implementation. However, a bus network is inherently a non-fault tolerant and blocking network. To cope with these problems, a solution is to use several buses in parallel on a network. Based on this idea, various schemes can be designed for a bus network: (1) Multiple-bus with full bus-memory connection, (2) Multiple-bus with single bus-memory connection, (3) Multiple-bus with partial bus-memory connection, and (4) Multiple-bus with class-based memory connection. On the other hand, a metric for the efficiency of fault-tolerant systems is its reliability. Although, there is no detailed analysis of the reliability of bus-based networks, this paper presents accurate and complete reliability analysis of bus-based networks to achieve these aims: (1) Determining the most efficient design of bus-based networks in terms of reliability, cost-effectiveness, and blocking issues, (2) Providing new methods for evaluating the performance of bus-based networks.     

Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions

In this paper, a novel asynchronous layered interface for a high performance on-chip bus is designed in a Globally Asynchronous Locally Synchronous (GALS) style. The proposed asynchronous layered interface with distributed and modularized control units supports multiple outstanding in-order/out-of-order transactions to achieve high performance. In the layered architecture, extension of an asynchronous layered interface performing complex functions is readily achieved without repeating the implementation of the whole bus interface. Simulations are carried out to measure the performance and power consumption of implemented asynchronous on-chip bus with the proposed asynchronous layered interface. Simulation results demonstrate that throughput of the asynchronous on-chip bus with multiple outstanding out-of-order transactions is increased by 30.9%, while power consumption overhead is 16.1% and area overhead is 56.8%, as compared to the asynchronous on-chip bus with a single outstanding transaction.