3D NAND闪存数据保持力与初始状态依赖性研究

数据保持力是NAND闪存重要的可靠性指标,本文基于用户在使用模式下,通过设计测试方法,研究了电荷捕获型3D NAND闪存初始阈值电压-2V至3V的范围内数据保持力特性.结果表明初始状态为编程态时,可以有效降低NAND闪存高温数据保留后的误码率,特别是随着擦写次数的增加,不同初始状态下电荷捕获型3D NAND闪存数据保持力差异更加明显,结论表明闪存最适宜存放的状态为0-1V,电荷捕获型3D NAND闪存器件应避免长期处于深擦除状态.并基于不同初始状态闪存高温数据保留后的数据保持力特性不同的现象进行了建模和演示,通过设计实验验证,机理解释模型符合实验结果.该研究可为电荷捕获型3D NAND闪存器件的长期存放状态提供理论参考.     

Stacked-nanowire device with virtual source/drain (SD-VSD) for 3D NAND flash memory application

A new stacked-nanowire device is proposed for 3-dimensional (3D) NAND flash memory application. Two single-crystalline Si nanowires are stacked in vertical direction using epitaxially grown SiGe/Si/SiGe/Si/SiGe layers on a Si substrate. Damascene gate process is adopted to make the gate-all-around (GAA) cell structure. Next to the gate, side-gate is made and device characteristics are controlled by the side-gate operations. By forming the virtual source/drain using the fringing field from the side-gate, short channel effect is effectively suppressed. Array design is also investigated for 3D NAND flash memory application.     

3D NAND flash memory with laterally-recessed channel (LRC) and connection gate architecture

A three-dimensional (3D) stacked bit-line NAND flash memory is investigated. The fabrication process flow for the formation of a laterally-recessed bit-line stack is described. Program operation is simulated using a stacked bit-line structure. Inter-layer interference (ILI) is addressed and the minimum isolation oxide thickness between stacked bit-lines is extracted. Simple device and array with the laterally-recessed bit-line stack are fabricated and electrical characteristics are measured. A new array architecture having a connection gate is designed for the 3D stacked bit-line NAND flash memory application.     

A 70 nm 16 Gb 16-Level-Cell NAND flash Memory

A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed . This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash, and quadruple bit density comparing to single-bit (SLC) NAND flash memory with the same design rule. New programming method suppresses the floating gate coupling effect and enabled the narrow distribution for 16LC. The cache-program function can be achievable without any additional latches. Optimization of programming sequence achieves 0.62 MB/s programming throughput. This 16-level NAND flash memory technology reduces the cost per bit and improves the memory density even more.     

NAND flash memory technology utilizing fringing electric field

In this review article, basic properties of NAND flash memory cell strings which consist of cells with virtual source/drain (S/D) (or without S/D) were discussed. The virtual S/D concept has advantages of better scalability, less cell fluctuation due to effectively longer channel length at the same technology node, and less program disturbance. The fringing electric field from the control-gate and/or the floating-gate is essential to induce the virtual S/D (charges) in the space region of the body between control-gates and becomes effective as cell size shrinks. A cell string consisting of planar channel silicon-oxide-nitride-oxide-silicon (SONOS) cells formed in bulk Si substrate needs to have a bit-line body doping of ～5 × 10¹⁷ cm^?3 in the channel and a less doping in the space region to keep high bit-line read current. The floating gate (FG) flash memory cell string gives larger bit-line current compared to that of SONOS flash memory cell string at given similar body doping. Non-planar channel cells like arch and fin-type body structures were more effective to focus the fringing electric field on the space region. The virtual S/D concept is also useful in 3-dimensional (3-D) stacked NAND flash memory where thin film (or nanowire, nanotube) body is adopted.     

Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)

As the cell size of the NAND flash memory has been scaled down by 40%–50% per year and the memory capacity has been doubling every year, a solid-state drive (SSD) that uses NAND as mass storage for personal computers and enterprise servers is attracting much attention. To realize a low-power high-speed SSD, the co-design of NAND flash memory and NAND controller circuits is essential. In this paper, three new circuit technologies, the selective bit-line precharge scheme, the advanced source-line program, and the intelligent interleaving, are proposed. In the selective bit-line precharge scheme, an unnecessary bit-line precharge is removed during the verify-read and consequently the current consumption decreases by 23%. In the advanced source-line program scheme, a hierarchical source-line structure is adopted. The load capacitance during the program pulse is reduced by 90% without a die size overhead. As a result, the current consumption is reduced by 48%. Finally, with the intelligent interleaving, a current peak is suppressed and a high-speed parallel write operation of the NAND flash memories is achieved. By using these three technologies, both the NAND flash memory and the NAND controller circuits are best optimized. At the sub-30 nm generation, the current consumption of the NAND flash memory decreases by 60% and the SSD speed improves by 150% without a cost penalty or circuit noise.      

New structure with SiO2-gate-dielectric select gates in vertical-channel three-dimensional (3D) NAND flash memory

This paper presents a novel vertical-channel three-dimensional (3-D) NAND flash structure with robust reliability. By employing a more reliable selector, the proposed structure overcomes the key drawback of the conventional 3-D NAND flash which is caused by charge storage in global select gate (GSG) and string select gate (SSG). Based on TCAD simulation, the conventional structure shows a threshold voltage shift of more than 1.5V, while the proposed structure is immune to this issue completely. Key parameters were analyzed to offer guidance on design and fabrication. Thickness of gate dielectric and thickness of SiO₂ spacing layer beneath GSG are key parameters for the electrical property of select gate, and thus should be designed accurately.     

High‐Performance Top‐Gated Organic Field‐Effect Transistor Memory using Electrets for Monolithic Printed Flexible NAND Flash Memory

High‐performance top‐gated organic field‐effect transistor (OFET) memory devices using electrets and their applications to flexible printed organic NAND flash are reported. The OFETs based on an inkjet‐printed p‐type polymer semiconductor with efficiently chargeable dielectric poly(2‐vinylnaphthalene) (PVN) and high‐k blocking gate dielectric poly(vinylidenefluoride‐trifluoroethylene) (P(VDF‐TrFE)) shows excellent non‐volatile memory characteristics. The superior memory characteristics originate mainly from reversible charge trapping and detrapping in the PVN electret layer efficiently in low‐k/high‐k bilayered dielectrics. A strategy is devised for the successful development of monolithically inkjet‐printed flexible organic NAND flash memory through the proper selection of the polymer electrets (PVN or PS), where PVN/‐ and PS/P(VDF‐TrFE) devices are used as non‐volatile memory cells and ground‐ and bit‐line select transistors, respectively. Electrical simulations reveal that the flexible printed organic NAND flash can be possible to program, read, and erase all memory cells in the memory array repeatedly without affecting the non‐selected memory cells.     

Ultimate Accuracy for the nand Flash Program Algorithm Due to the Electron Injection Statistics

This paper investigates the ultimate accuracy of the NAND flash program algorithm that is determined by the statistical injection of electrons from the substrate to the floating gate. The granular nature of the electron flow during a constant-current Fowler-Nordheim program operation is shown to spread the programmed threshold-voltage distribution of the array cells. The electron injection statistics displays a Poissonian behavior for low amounts of transferred charge, but a sub-Poissonian character becomes clearly evident when large charge packets are stored. This effect is expected from the reduction of the tunnel oxide field that follows each electron storage event into the floating gate, establishing a correlation among such events. Finally, the impact of the electron injection statistical spread on the accuracy of the NAND flash program algorithm is investigated as a function of the technology node feature size, drawing projections on future NAND technologies.     

A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate

A 16 Gb 8-level NAND flash chip on 56 nm CMOS technology has been fabricated and is being reported for the first time. This is the first 3-bit per cell (X3) chip published with all-bitline (ABL) architecture, which doubles the write performance compared with conventional shielded bitline architecture. A new advanced cache program algorithm provides another 15% improvement in write performance. This paper also discusses a technique for resolving the sensing error resulting from cell source line noise, which usually varies with the data pattern. The new architecture and advanced algorithm enable an 8 MB/s write performance that is comparable to previously published 2-bit per cell (4-level) NAND performance. Considering the significant cost reduction compared to 4-level NAND flash based on the same technology, this chip is a strong candidate for many mainstream applications.     

多通道NAND闪存控制器的硬件实现

本文提出了在一款片上系统(SOC)芯片设计中的多通道NAND闪存控制器实现方案。在对NAND闪存控制器的结构和实现方法的研究上,闪存控制器利用带两个16K字节缓冲器的高效率缓冲管理控制器来管理4个通道,每个通道可以连接4片闪存芯片。控制器内嵌16比特BCH纠错模块,支持AMBAAHB总线与MLC闪存。文中还介绍了行地址计算与快闪存储器存储单元的初始化。结果分析里给出了控制器的仿真波形、功耗分析和综合结果。在一个存储组与一个通道的配置条件下,控制器的实现只需要71K逻辑门。     

Memory technology in the future

This article deals with future memory technologies in the next mobile era. First concern is about whether NAND flash memory and DRAM will succeed to evolve beyond 50 nm technologies. Now, technological needs in both memories play a driving engine in pushing further for scaling of a device dimension. Secondly, entirely different types of non-volatile memories can start to penetrate main memory markets as an alternative of NAND flash memory or DRAM in the not-too-distant future. Along with 3-D access transistors, it is widely accepted that 3-D MIM capacitors with ultra high-K dielectrics and noble electrodes will extend silicon technology down to a technology node between 20 to 30 nm. With charge-trap-flash technology, NAND flash memory will extend its technology node down to 20 - 30 nm. Among the candidates for the next generation, PRAM and FRAM begin to burgeon in mass-production. Beyond a 50 nm technology node, scaling of PRAM could be successful by the development of new material and new cell structure. 3-D ferroelectric-capacitor technology is critical for FRAM to enter a 90 nm technology node and beyond.     

Soft-Decision Error Correction of NAND Flash Memory with a Turbo Product Code

As NAND flash memory fabrication technology scales down to 20 nm and below, the raw bit error rate increases very rapidly and conventional hard-decision based error correction does not provide enough protection. The turbo product code (TPC) based error correction with multi-precision output from NAND flash memory is promising because of high error-correcting performance and flexibility in code construction. In this work, we construct a rate-0.907 (36116, 32768) extended TPC for 2-bit MLC NAND flash memory, and apply the Chase–Pyndiah decoding algorithm. An efficient complexity reduction scheme is also proposed to eliminate redundant computations in the Chase–Pyndiah decoding algorithm. The replica parallel decoding is also employed to lower the error floor. The experimental results that include the effects of flash memory output precision are presented for a simulated flash memory channel.     

针对固态硬盘应用的多通道闪存控制器实现

本文介绍一种基于MLC闪存和AHB总线的高速大容量数据控制系统的硬件实现方法,所提出的闪存控制器实现带8个8K字节缓冲器的高效率缓冲管理控制器来管理8个通道,每个通道可以连接8个闪存芯片。文中还介绍了快闪存储器存储单元的空白检查和交叉存取操作。实验结果证明该固态盘控制器的最高读速度为230．2MB／s,最高写速度为101．9MB／s．最后给出了控制器的综合结果和功耗分析,在24比特BCH纠错与一个通道的配置条件下,控制器的实现需要315K逻辑门。     

Program Cache Busy Time Control Method for Reducing Peak Current Consumption of NAND Flash Memory in SSD Applications

In current NAND flash design, one of the most challenging issues is reducing peak current consumption (peak ICC), as it leads to peak power drop, which can cause malfunctions in NAND flash memory. This paper presents an efficient approach for reducing the peak ICC of the cache program in NAND flash memory — namely, a program Cache Busy Time (tPCBSY) control method. The proposed tPCBSY control method is based on the interesting observation that the array program current (ICC2) is mainly decided by the bit‐line bias condition. In the proposed approach, when peak ICC2 becomes larger than a threshold value, which is determined by a cache loop number, cache data cannot be loaded to the cache buffer (CB). On the other hand, when peak ICC2 is smaller than the threshold level, cache data can be loaded to the CB. As a result, the peak ICC of the cache program is reduced by 32% at the least significant bit page and by 15% at the most significant bit page. In addition, the program throughput reaches 20 MB/s in multiplane cache program operation, without restrictions caused by a drop in peak power due to cache program operations in a solid‐state drive.     

一种用于NAND闪存的奇偶位线块编程补偿算法

为改善数据保持干扰和编程干扰对NAND闪存可靠性的影响,提出了一种新的奇偶位线块编程补偿算法。该算法利用编程干扰效应来补偿由数据保持引起的阈值漂移,修复NAND闪存因数据保持产生的误码,提高了NAND闪存的可靠性。将该算法应用于编程擦除次数为3k次的1x-nm MLC NAND闪存。实验结果表明,在数据保持时间为1年的条件下,与传统奇偶交叉编程算法相比,采用该补偿算法的NAND闪存的误码降低了93%;与读串扰恢复算法相比,采用该补偿算法的NAND闪存的误码下降了38%。     

A high efficiency all-PMOS charge pump for 3D NAND flash memory

For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3D V-NAND has been proposed. In this circuit, the Pelliconi structure is used to enhance the driving capability, two auxiliary substrate bias PMOS transistors are added to mitigate the body effect, and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop is eliminated by dynamic gate control structure. Simulated results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86% and power efficiency of 50%. The output voltage of the proposed 9 stages charge pump can exceed 2 V under 2 MHz clock frequency in 2X nm 3D V-NAND technology. Our results provide guidance for the peripheral circuit design of high density 3D V-NAND integration.     

A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure

A 3-dimensional double stacked 4 gigabit multilevel cell NAND flash memory device with shared bitline structure have successfully developed. The device is fabricated by 45 nm floating-gate CMOS and single-crystal Si layer stacking technologies. To support fully compatible device performance and characteristics with conventional planar device, shared bitline architecture including Si layer-dedicated decoder and Si layer-compensated control schemes are also developed. By using the architecture and the design techniques, a memory cell size of 0.0021 mum²/bit per unit feature area which is smallest cell size and 2.5 MB/s program throughput with 2 kB page size which is almost equivalent performance compared to conventional planar device are realized.     

适于空间图像闪存阵列的非与闪存控制器

提出一种适于空间应用的非与(NAND,not and)闪存控制器。首先,分析了空间相机存储图像的要求,说明了闪存控制器结构的特点。接着,分析了闪存数据存储差错的机理,针对闪存结构组织特点提出了一种基于BCH(Bose-Chaudhuri-Hocquenghem,2108,2048,5)码的闪存纠错算法。然后,对传统BCH编码器进行了改进,提出了一种8bit并行蝶形阵列处理机制。最后,使用地面检测设备对闪存控制器进行了试验验证。结果表明,闪存控制器能快速稳定、可靠地工作,在闪存单页2Kbt/page下可以纠正40bit错误,在相机正常工作行频为2.5kHz下拍摄图像时4级流水线闪存连续写入速度达到133Mbit/s,可以满足空间相机图像存储系统的应用。     

Novel ultrahigh-density flash memory with a stacked-surrounding gate transistor (S-SGT) structured cell

In order to overcome the limitation of cell area of 4F/sup 2/ per bit in conventional NAND flash memory cells, stacked-surrounding gate transistor (S-SGT) structured cell is proposed. This newly structured cell achieves a cell area of 4F/sup 2//N per bit, where N is the number of stacked memory cells in one silicon pillar, without using multibit per memory cell technology. The S-SGT structured cell consisting of two stacked memory cells in one silicon pillar achieves a cell area per bit of less than 50% of the smallest reported NAND structured cell. The novel S-SGT structured cells are fabricated by vertical self-aligned processes using a 0.2 /spl mu/m design rule. The S-SGT structured cell can be programmed and erased by uniform injection and uniform emission of Fowler-Nordheim (F-N) tunneling electrons over the whole channel area of the memory cell, respectively, which is the same program and erase mechanism as in conventional NAND structured cell. This high performance S-SGT structured cell is applicable to high-density nonvolatile memories for 16 G/64 G bit Flash memories and beyond.