A fully integrated SOI RF MEMS technology for system-on-a-chip applications

In this paper, a silicon-on-insulator (SOI) radio-frequency (RF) microelectromechanical systems (MEMS) technology compatible with CMOS and high-voltage devices for system-on-a-chip applications is experimentally demonstrated for the first time. This technology allows the integration of RF MEMS switches with driver and processing circuits for single-chip communication applications. The SOI high-voltage device (0.7-/spl mu/m channel length, 2-/spl mu/m drift length, and over 35-V breakdown voltage), CMOS devices (0.7-/spl mu/m channel length and 1.3/-1.2 V threshold voltage), and RF MEMS capacitive switch (insertion loss 0.14 dB at 5 GHz and isolation 9.5 dB at 5 GHz) are designed and fabricated to show the feasibility of building fully integrated RF systems. The performance of the fabricated RF MEMS capacitive switches on low-resistivity and high-resistivity SOI substrates will also be compared.     

The anatomy of integrated-circuit technology

One definition of integrated electronics can be given as ``the physical realization of a number of circuit elements inseparably associated on or within a continuous body to perform the function of a circuit.' This definition gives only an indirect clue to the reasons for the tremendous impact of integrated electronics upon the electronics field in particular, and upon technological aids to society in general. This article attempts to explore these reasons and to discuss some of the consequences of the growth of this advanced technology. It complements J. J. Suran's January article, ``A Perspective on Integrated Electronics,' which explores the problems in design theory that have resulted from the extreme complexity of IC fabrication.     

Self-heating effects in a BiCMOS on SOI technology for RFIC applications

Self-heating in a 0.25 /spl mu/m BiCMOS technology with different isolation structures, including shallow and deep trenches on bulk and silicon-on-insulator (SOI) substrates, is characterized experimentally. Thermal resistance values for single- and multifinger emitter devices are extracted and compared to results obtained from two-dimensional, fully coupled electrothermal simulations. The difference in thermal resistance between the investigated isolation structures becomes more important for transistors with a small aspect ratio, i.e., short emitter length. The influence of thermal boundary conditions, including the substrate thermal resistance, the thermal resistance of the first metallization/via layer, and the simulation structure width is investigated. In the device with full dielectric isolation-deep polysilicon-filled trenches on an SOI substrate-accurate modeling of the heat flow in the metallization is found to be crucial. Furthermore, the simulated structure must be made wide enough to account for the large heat flow in the lateral direction.     

Novel two-step SDB technology for high-performance thin-film SOI/MOSFET applications

A novel two-step oxided silicon wafer direct bonding process (TSDB) for fabricating high-quality SOI substrates is presented, which has no contamination, no complex thinning process and no subsurface damage. The fracture strength of the SOI/TSDB material is 180 kg/cm/sup 2/. SOI/TSDB NMOS and PMOS devices (0.8-3 mu m) have shown that the typical values of electron and hole surface channel mobility are 680 and 320 cm/sup 2//Vs, respectively. A high device transconductance and high on-off current ratio have also been obtained.<>     

Growth of high-purity semi-insulating bulk GaAs for integrated-circuit applications

Growth of high-purity bulk semi-insulating GaAs by the Liquid-Encapsulated Czochralski (LEC) method has produced thermally stable, high-resistivity crystals suitable for use in direct ion implantation. Large round substrates have become available for integrated-circuit processing. The implanted wafers have excellent electrical uniformity (±4 percent Vp) and have shown electron mobility as high as 4800cm²/V.s for Se implants with 1.7 × 10¹⁷cm^-3peak doping. Careful control of background doping through in situ synthesis has produced GaAs with Si concentrations as low as 6 × 10¹⁴cm^-3grown from SiO2crucibles. Detailed results of qualification tests for ion implantation in LEC GaAs will be discussed. Feasibility of successful high-speed GaAs large-scale integrated circuits using LEC substrates will be described.     

Fully-depleted SOI CMOS for analog applications

Fully-depleted (FD) SOI MOSFETs offer near-ideal properties for analog applications. In particular their high transconductance to drain current ratio allows one to obtain a higher gain than from bulk devices, and the reduced body effect permits one to fabricate more efficient pass gates. The excellent behavior of SOI MOSFETs at high temperature or at gigahertz frequencies is outlined as well     

Impact of the radiation environment on integrated-circuit technology

Techniques used to design and produce silicon monolithic integrated circuits for use in the radiation environment found near a nuclear detonation are reviewed. The procedures used to define an anticipated threat are given, and interactions between typical radiations and IC materials are discussed. Circuit selection and design with respect to these interactions are considered process developments needed to implement these designs reviewed. The electrical and radiation performance currently available in production from several sources is described.     

A three-terminal SOI gated varactor for RF applications

This paper presents a new CMOS compatible SOI gated varactor for use in RF ICs. With its additional third terminal, the device offers an exceptional large tuning range and a good quality factor. The result of the MEDICI simulation of the structure of the varactor has been confirmed with measured data. A VCO circuit that can potentially exploit the three-terminal property is also reported     

Sequential tests for integrated-circuit failures

We propose a sequential probability ratio test (SPRT) based on a 2-parameter Weibull distribution for integrated-circuit (IC) failure analysis. The shape parameter of the Weibull distribution characterizes the decreasing, constant, or increasing failure rate regions in the bath tub model for IC. The algorithm (SD) detects the operating region of the IC based on the observed failure times. Unlike the fixed-length tests, the SD, due to its sequential nature, uses the minimum average number of devices for the test for fixed error tolerances in the detection procedure. We find that SD is, on average, 96% more statistically efficient than the fixed-length test. SD is highly robust to the variations in the model parameters, unlike other existing sequential tests. Since the accuracy of the tests and the test length are conflicting requirements, we also propose a truncated SD which allows a better control of this tradeoff. It has both the sequential nature of examining measurements and the fixed-length property of guaranteeing that the tolerances be met approximately with a specified number of available measurements     

An SOI LDMOS/CMOS/BJT technology for integrated power amplifiersused in wireless transceiver applications

This paper describes a SOI LDMOS/CMOS/BJT technology that can be used in portable wireless communication applications. This technology allows the complete integration of the front-end circuits with the baseband circuits for low-cost/low-power/high-volume single-chip transceiver implementation. The LDMOS transistors (0.35 μm channel length, 3.8 μm drift length, 4.5 GHz f_T and 21 V breakdown voltage), CMOS transistors (1.5 μm channel length, 0.8/-1.2 V threshold voltage), lateral NPN transistor (18 V BV_CBO and h _FE of 20), and high Q-factor (up to 6.1 at 900 MHz and 7.2 at 1.8 GHz) on-chip inductors are fabricated. A fully-functional high performance integrated power amplifier for 900 MHz wireless transceiver application is also demonstrated     

Electro-thermal short pulsed simulation for SOI technology

This work investigates the determination of thermal boundary conditions for electro-thermal simulations in case of short duration stressing event for SOI devices. An analysis of the heat flow inside the structure is given showing an important thermal role of contacts in deep submicron SOI devices. These boundary conditions are applied to ISE simulations of a partially depleted 130nm SOI diode during an ESD event and a good matching with TLP experimental results has been obtained.     

Vertically integrated SOI circuits for low-power and high-performance applications

Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.     

Fully depleted SOI CMOS logic gates for low-voltage applications

Approaches are discussed to the design of low-voltage, low-power VLSI circuits based on SOI nanotransistors. Computer simulations are run to analyze the switching performance of NOT, 2NAND, and 2NOR gates implemented in CMOS technology with fully depleted SOI nanotransistors of different design parameters. The delay and switching power are investigated as functions of supply voltage over a range lying below 1 V, for different values of back-gate bias. The possibility is investigated of operating the transistors of a logic gate in subthreshold mode. This approach is shown to provide a significant reduction in switching power under the right conditions.     

SOI技术的新进展

综述了SOI技术的发展历程,SOI的主流技术,SOI技术发展的新动向,SOI技术的应用进展,并介绍了上海微系统与信息技术研究所和上海新傲科技有限公司的SOI研发和产业化情况。     

Thin silicide development for fully-depleted SOI CMOS technology

Ultrathin silicide with thickness less than 30 nm and specific contact resistivity to silicon less than mid-10^-7Ω-cm ² is necessary for achieving low contact resistance in a sub-0.25-μm fully-depleted (FD) silicon-on-insulator (SOI) CMOS technology. This contact problem becomes even more severe as one continues to scale down the device dimensions. We first studied the effects of source/drain series resistance and gate sheet resistance on the device speed performance and obtained a set of desired design criteria. These were used along with a transmission line model to yield a silicide design space, which was then used to evaluate the experimental results. Both cobalt and titanium silicide processes were implemented and found to satisfy the design criteria. Final device characteristics were also measured. Several process integration issues related to contact dielectric deposition and contact barrier integrity were found to greatly impact the final contact properties. These along with the detailed fabrication process are discussed     

Liquid-crystal technique for observing integrated-circuit operation

A nondestructive technique has been developed that enables both the electric fields and temperature distributions at the surface of an operating integrated circuit to be viewed with conventional optical microscopes. Packaged chips or unscribed wafers are coated with a nematic liquid-crystal layer and operated in their normal fashion. Practical preparation and observation procedures have been developed.     

Lateral high-speed bipolar transistors on SOI for RF SoC applications

This paper introduces a novel silicon-on-insulator (SOI) lateral radio-frequency (RF) bipolar transistor. The fabrication process relies on polysilicon side-wall-spacer (PSWS) to self-align the base contact to the intrinsic base. The self-aligned base and emitter regions greatly reduce the parasitic components. In this unique design, the critical dimensions are not limited by lithography resolution. With the control of the SOI film thickness or SWS width, the device can be optimized for higher speed, gain, breakdown, or current drive capability. Furthermore, with no additional mask, both common-emitter and common-collector layout configurations can be realized, providing more flexibility to the circuit design and more compact layout. The experimental f/sub T//f/sub max/ of the high-speed device are 17/28 GHz, the second fastest reported f/sub T/ for lateral bipolar junction transistors (LBJT) so far. As for the high-voltage device, the measured f/sub T//f/sub max/ of 12/30 GHz and BV/sub CEO/ of over 25 V produces a Johnsons product well above 300 GHz /spl middot/V. This figure is currently the closest reported data to the Johnsons limit for lateral BJTs. This technology can easily be integrated with CMOS on SOI. Therefore, it is feasible to build fully complimentary bipolar and MOS transistors on a single SOI substrate to form a true complementary-BiCMOS process. This silicon-based lateral SOI-BJT technology is a promising candidate for realizing future RF SoC applications.     

Silicon technology tradeoffs for radio-frequency/mixed-signal "systems-on-a-chip"

Silicon technology has progressed over the last several years from a digitally oriented technology to one well suited for microwave and RF applications at a high level of integration. Technology scaling, both at the transistor and back-end metallization level, has driven this progress. CMOS technology is ideally suited for low-noise amplification and receiver applications, but the fundamental breakdown voltage is lower than that of equivalent Si/SiGe HBTs. High-quality passive devices are equally important, and improvements in metallization technology are resulting in higher quality inductors. This paper summarizes the silicon technology issues associated with RF "system-on-a-chip" applications.     

Substrate crosstalk reduction using SOI technology

This work analyzes both by simulations and measurements the substrate crosstalk performances of various Silicon-On-Insulator (SOI) technologies, and compares them to those of normal bulk CMOS process. The influence of various parameters, such as substrate resistivity, buried oxide thickness and distance between devices, is investigated. The use of capacitive guard rings is proposed, and their effectiveness is demonstrated. A simple RC model has been developed to allow a deep understanding of these phenomena as well as to simplify future studies of more complex systems. The superiority of high-resistivity SIMOX substrates over standard SOI and bulk is finally demonstrated