A Very Efficient Redundancy Analysis Method Using Fault Grouping

To increase device memory yield, many manufacturers use incorporated redundancy to replace faulty cells. In this redundancy technology, the implementation of an effective redundancy analysis (RA) algorithm is essential. Various RA algorithms have been developed to repair faults in memory. However, nearly all of these RA algorithms have low analysis speeds. The more densely compacted the memory is, the more testing and repair time is needed. Even if the analysis speed is very high, the RA algorithm would be useless if it did not have a normalized repair rate of 100%. In addition, when the number of added spares is increased in the memory, then the memory space that must be searched with the RA algorithms can exceed the memory space within the automatic test equipment. A very efficient RA algorithm using simple calculations is proposed in this work so as to minimize both the repair time and memory consumption. In addition, the proposed algorithm generates an optimal solution using a tree‐based algorithm in each fault group. Our experiment results show that the proposed RA algorithm is very efficient in terms of speed and repair.     

一种基于存储器故障原语的March测试算法研究

研究高效率的系统故障测试算法,建立有效的嵌入式存储器测试方法,对提高芯片良品率、降低芯片生产成本,具有十分重要的意义.从存储器基本故障原语测试出发,在研究MarchLR算法的基础上,提出March LSC新算法.该算法可测试现实的连接性故障,对目前存储器的单一单元故障及耦合故障覆盖率提升到100%.采用March LSC算法,实现了内建自测试电路(MBIST).仿真实验表明,March LSC算法能很好地测试出嵌入式存储器故障,满足技术要求.研究结果具有重要的应用参考价值.     

一种Mbist新型算法March 3CL的设计

制造工艺的不断进步,嵌入式存储器在片上系统芯片中的集成度越来越大,同时存储器本身也变得愈加复杂,使得存储器出现了一系列新的故障类型,比如三单元耦合故障.存储器內建自测试技术是当今存储器测试的主流方法,研究高效率的Mbist算法,是提高芯片成品率的必要前提.以SRAM的7种三单元耦合故障为研究对象,通过分析故障行为得到三单元耦合的72种故障原语,并且分析了地址字内耦合故障的行为,进而提出新的测试算法March 3CL.以2048X32的SRAM为待测存储器,利用EDA工具进行了算法的仿真,仿真结果表明,该算法具有故障覆盖率高、时间复杂度低等优点.     

High-efficiency memory BISR with two serial RA stages using spare memories

As technology has become more advanced, the density of memory has increased greatly. This development has led to need for a high- efficiency redundancy analysis (RA) algorithm to improve yield rate. Presented is a new methodology that can achieve high-efficiency repair against faults in memory. Experimental results show that the proposed built-in self-repair (BISR) method performs well.     

An on-line BIST RAM architecture with self-repair capabilities

The emerging field of self-repair computing is expected to have a major impact on deployable systems for space missions and defense applications, where high reliability, availability, and serviceability are needed. In this context, RAM (random access memories) are among the most critical components. This paper proposes a built-in self-repair (BISR) approach for RAM cores. The proposed design, introducing minimal and technology-dependent overheads, can detect and repair a wide range of memory faults including: stuck-at, coupling, and address faults. The test and repair capabilities are used on-line, and are completely transparent to the external user, who can use the memory without any change in the memory-access protocol. Using a fault-injection environment that can emulate the occurrence of faults inside the module, the effectiveness of the proposed architecture in terms of both fault detection and repairing capability was verified. Memories of various sizes have been considered to evaluate the area-overhead introduced by this proposed architecture     

An Exact approach for Complete Test Set Generation of Toffoli-Fredkin-Peres based Reversible Circuits

Reversible logic has gained interest of researchers worldwide for its ultra-low power and high speed computing abilities in the future quantum information processing. Testing of these circuits is important for ensuring high reliability of their operation. In this work, we propose an ATPG algorithm for reversible circuits using an exact approach to generate CTS (Complete Test Set) which can detect single stuck-at faults, multiple stuck-at faults, repeated gate fault, partial and complete missing gate faults which are very useful logical fault models for reversible logic to model any physical defect. Proposed algorithm can be used to test a reversible circuit designed with k-CNOT, Peres and Fredkin gates. Through extensive experiments, we have validated our proposed algorithm for several benchmark circuits and other circuits with family of reversible gates. This algorithm produces a minimal and complete test set while reducing test generation time as compared to existing state-of-the-art algorithms. A testing tool is developed satisfying the purpose of generating all possible CTS’s indicating the simulation time, number of levels and gates in the circuit. This paper also contributes to the detection and removal of redundant faults for optimal test set generation.     

Performance evaluation of a reconfiguration-algorithm for memoryarrays containing clustered faults

Reconfiguration of memory arrays using spare rows and columns is useful for yield-enhancement of memories. This paper presents a reconfiguration algorithm (QRCF) for memories that contain clustered faults. QRCF operates in a branch and bound fashion similar to known optimal algorithms that require exponential time. However, QRCF repairs faults in clusters rather than individually. Since many faults are repaired simultaneously, the execution-time of QRCF does not become prohibitive even for large memories containing many faults. The performance of QRCF is evaluated under a probabilistic model for clustered faults in a memory array. For a special case of the fault model, QRCF solves the reconfiguration problem exactly in polynomial time. In the general case, QRCF produces an optimal solution with high probability. The algorithm is also evaluated through simulation. The performance and execution-time of QRCF on arrays containing clustered faults are compared with other approximation algorithms and with an optimal algorithm. The simulation results show that QRCF outperforms previous approximation algorithms by a wide margin and performs nearly as well as the optimal algorithm with an execution-time that is orders of magnitude less     

A heterogeneous built-in self-repair approach using system-level synthesis flexibility

Summary and Conclusions -A novel methodology is proposed for designing fault-tolerant real-time multi-processor systems-on-a-chip to achieve optimal productivity. The methodology employs the heterogeneous built-in-self-repair (BISR) based on graceful degradation and yield enhancement techniques as an embedded optimization engine. The technique exploits the flexibility provided in task-level scheduling and algorithm selection steps. A hardware fault model is developed for modern super-scalar processors and multi-processors which enables an efficient treatment of the synthesis and compilation goals. For the first time, heterogeneous BISR is used at the task level. The key idea is to adapt scheduling and algorithm selection to the available nonfaulty resources. If there is a fault in memory, the algorithms that use less memory are selected and the scheduler exploits the other abundant resource, viz, the processors, more vigorously to compensate for the loss of part of memory. Similarly, a fault in a processor is backed up by memory. The synthesis approach minimizes the degradation in performance for single or multiple faults using simulated annealing-based algorithm selection, scheduling, and assignment algorithms. On the large set of examples this adaptive algorithm selection and scheduling technique has achieved important improvement of throughput compared to conventional nonadaptive schemes. The experimental results also indicate that important improvement in productivity can be achieved by using the extra throughput gained from the technique.     

Test generation algorithm for analog systems based on support vector machine

In some methods for test generation, an analog device under test (DUT) is treated as a discrete-time digital system by placing it between a digital-to-analog converter and an analog-to-digital converter. Then the test patterns and responses can be performed and analyzed in the digital domain. We propose a novel test generation algorithm based on a support vector machine (SVM). This method uses test patterns derived from the test generation algorithm as input stimuli, and sampled output responses of the analog DUT for classification and fault detection. The SVM is used for classification of the response space. When the responses of normal circuits are similar to those of faulty circuits (i.e., the latter have only small parametric faults), the response space is mixed and traditional algorithms have difficulty in distinguishing the two groups. However, the SVM provides an effective result. This paper also proposes an algorithm to calculate the test sequence for input stimuli using the SVM results. Numerical experiments prove that this algorithm can enhance the precision of test generation.     

A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores

We have introduced a low-cost at-speed BIST architecture that enables conventional microprocessors and DSP cores to test their functional blocks and embedded SRAMs in system-on-a-chip architectures using their existing hardware and software resources. To accommodate our proposed new test methodology, minor modifications should be applied to base processor within its test phase. That is, we modify the controller to interpret some of the instructions differently only within the initial test mode. In this paper, we have proposed a fuctional self-test methodology that is deterministic in nature. In our proposed architecture, a self test program called BIST Program is stored in an embedded ROM as a vehicle for applying tests. We first start with testing processor core using our proposed architedture. Once the testing of the processor core is completed, this core is used to test the embedded SRAMs. A test algorithm which utilizes a mixture of existing memory testing techniques and covers all important memory faults is presented in this paper. The proposed memory test algorithm covers 100% of the faults under the fault model plus a data retention test. The hardware overhead in the proposed architecture is shown to be negligible. This architecture is implemented on UTS-DSP (University of Tehran and Iran Communicaton Industries (SAMA)) IC which has been designed in VLSI Circuits and Systems Laboratory.     

ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips

Complex system-on-a-chip (SOC) designs usually consist of many memory cores. Efficient yield-enhancement techniques thus are required for the memory cores in SOCs. This paper presents an infrastructure intelligent property (IIP) for testing, diagnosing, and repairing multiple memory cores in SOCs. The proposed IIP can perform parallel testing for multiple memories, and serial diagnosis or repair for one memory each time. In the repair mode, the proposed IIP can execute various redundancy analysis algorithms. Therefore, the user can select a better redundancy analysis algorithm for each memory core being tested according to its redundancy structure. Simulation results show that the proposed IIP needs less test time and redundancy analysis time than the processor-based built-in self-repair scheme. We also have realized the proposed IIP for four types of memories - two 8 K 64 bit SRAMs, one 4 K x 16 bit SRAM, and one 2 K x 32 bit SRAM - based on TSMC 0.18-mum standard cell technology. Simulation results show that the area overhead of the IIP is only about 4.6%.     

Testing complex couplings in multiport memories

In this paper, the effects of simultaneous write access on the fault modeling of multiport RAMs are investigated. New fault models representing more accurately the actual faults in such memories are then defined. Subsequently, a general algorithm that ensures the detection of all faults belonging to the new fault model is proposed. Unfortunately, the obtained algorithms are of O(n²) complexity which is not practical for real purposes. In order to reduce the complexity of the former test algorithm a topological approach has been developed. Finally, a BIST implementation of one of the proposed topological algorithms is presented     

Fault Diagnosis and Reconfiguration for Multilevel Inverter Drive Using AI-Based Techniques

A fault diagnostic and reconfiguration method for a cascaded H-bridge multilevel inverter drive (MLID) using artificial-intelligence-based techniques is proposed in this paper. Output phase voltages of the MLID are used as diagnostic signals to detect faults and their locations. It is difficult to diagnose an MLID system using a mathematical model because MLID systems consist of many switching devices and their system complexity has a nonlinear factor. Therefore, a neural network (NN) classification is applied to the fault diagnosis of an MLID system. Multilayer perceptron networks are used to identify the type and location of occurring faults. The principal component analysis is utilized in the feature extraction process to reduce the NN input size. A lower dimensional input space will also usually reduce the time necessary to train an NN, and the reduced noise can improve the mapping performance. The genetic algorithm is also applied to select the valuable principal components. The proposed network is evaluated with simulation test set and experimental test set. The overall classification performance of the proposed network is more than 95%. A reconfiguration technique is also proposed. The proposed fault diagnostic system requires about six cycles to clear an open-circuit or short-circuit fault. The experimental results show that the proposed system performs satisfactorily to detect the fault type, fault location, and reconfiguration.     

A Classical Parameter Identification Method and?a?Modern Test Generation Algorithm

Many methods have been presented for the testing and diagnosis of analog circuits. Each of these methods has its advantages and disadvantages. In this paper we propose a novel sensitivity analysis algorithm for the classical parameter identification method and a continuous fault model for the modern test generation algorithm, and we compare the characteristics of these methods. At present, parameter identification based on the component connection model (CCM) cannot ensure that the diagnostic equation is optimal. The sensitivity analysis algorithm proposed in this paper can choose the optimal set of trees to construct an optimal CCM diagnostic equation, and enhance the diagnostic precision. But nowadays increasing attention is being paid to test generation algorithms. Most test generation algorithms use a single value in the fault model. But the single values cannot substitute for the actual faults that may occur, because the possible faulty values vary over a continuous range. To solve this problem, this paper presents a continuous fault model for the test generation algorithm which has a continuous range of parameters. The test generation algorithm with this model can improve the treatment of the tolerance problem, including the tolerances of both normal and faulty parameters, and enhance the fault coverage rate. The two methods can be applied in different situations.     

一种基于故障特征分析的总线测试自适应算法

针对现有数字总线测试算法故障覆盖率低、效率不高、过程复杂等不足,建立了以区分主、从驱动器网络为特点的总线结构模型;在分析总线结构故障特征的基础上,定义了故障等价的概念,通过对故障模式的等价变换,得到了故障模式最简集合;最后提出了一种基于故障特征分析的自适应测试算法.结果表明,与同类算法相比,该算法在保证故障诊断最大化的前提下,简化了测试流程,降低了测试复杂性,缩减了测试序列长度;且设计简单,易于工程实现.     

Automatic generation and compaction of March tests for memoryarrays

Given a set of memory array faults, the problem of computing a compact March test that detects all specified memory array faults is addressed. In this paper, we propose a novel approach in which every memory array fault is modeled by a set of primitive memory faults. A primitive March test is defined for each primitive memory fault. We show that March tests that detect the specified memory array faults are composed of primitive March tests. A method to compact the March tests for the specified memory array faults is described. A set of examples to illustrate the approach is presented. Experimental results demonstrate the productivity gained using the proposed framework     

An efficient built-in self testing for random-access memory

The authors propose a test algorithm for pattern-sensitive faults in large-size RAM with high circuit density. The algorithm tests an n-bit RAM in 195√n time to detect both static and dynamic pattern-sensitive faults over the 9-neighbourhood of every memory cell. A 4 Mb RAM can be tested by the proposed algorithm several thousand times faster than the conventional sequential algorithms for detecting pattern-sensitive faults. The test speedup has been achieved by writing a test data simultaneously over many cells, and the stored data are tested simultaneously by a parallel comparator and error detector in a read operation. The existing RAM architecture has been modified very little so that the proposed technique can be implemented very easily even in switched-capacitor DRAM (dynamic random-access memory) with low intercell pitch width. The test procedure has also been applied to built-in self-testing (BIST) and is compared with other BIST implementations     

Efficient March Tests for a Reduced 3-Coupling and 4-Coupling Faults in Random-Access Memories

This paper presents two new march test algorithms, MT-R3CF and MT-R4CF, for detecting reduced 3-coupling and 4-coupling faults, respectively, in n × 1 random-access memories (RAMs). To reduce the length of the tests, only the coupling faults between physically adjacent memory cells have been considered. The tests assume that the storage cells are arranged in a rectangular grid and that the mapping from logical addresses to physical cell locations is known completely. The march tests need 30n and 41n operations, respectively. In this paper any memory fault is modelled by a set of primitive memory faults called simple faults. We prove, using an Eulerian graph model, the ability of the test algorithms to detect all simple coupling faults. This paper also includes a study regarding the ability of the test MT-R3CF to detect interacting linked 3-coupling faults. This work improves the results presented in [1] where a similar model of reduced 3-coupling faults has been considered and a march test with 38n operations has been proposed. To compare these new march tests with other published tests, simulation results are presented in this paper.     

High Repair Efficiency BIRA Algorithm with a Line Fault Scheme

With the rapid increase occurring in both the capacity and density of memory products, test and repair issues have become highly challenging. Memory repair is an effective and essential methodology for improving memory yield. An SoC utilizes built‐in redundancy analysis (BIRA) with built‐in self‐test for improving memory yield and reliability. This letter proposes a new heuristic algorithm and new hardware architecture for the BIRA scheme. Experimental results indicate that the proposed algorithm shows near‐optimal repair efficiency in combination with low area and time overheads.     

Generating test patterns for VLSI circuits using a geneticalgorithm

The authors present the development of a technique that uses genetic algorithms for the generation of rest patterns that detect single stuck-at faults in combinational VLSI circuits. As the genetic algorithm evolves, an efficient set of test patterns are produced, by searching the solution space for patterns that detect the highest number of remaining faults in the fault list