基于GaN HEMT的高线性星载Doherty功率放大器设计北大核心CSCD

在射频通信链路中,功率放大器决定了发射通道的线性、效率等关键指标。卫星通信由于是电池供电,对功率放大器的工作效率要求比较高。文章基于GaN HEMT晶体管采用对称设计完成了一款高效率的Doherty功率放大器。测试结果表明:该Doherty功放的功率增益大于29 dB;1 dB压缩点功率(P_(1 dB))大于35 dBm;在35 dBm输出时,其功率附加效率(PAE)大于47.5%,三阶交调失真(IMD3)大于35 dBc;在功率回退3 dB时,其PAE大于37%,IMD3大于32 dBc。     

Area-Efficient 60 GHz +18.9 dBm Power Amplifier with On-Chip Four-Way Parallel Power Combiner in 65-nm CMOS

This paper presents a compact 60-GHz power amplifier utilizing a four-way on-chip parallel power combiner and splitter. The proposed topology provides the capability of combining the output power of four individual power amplifier cores in a compact die area. Each power amplifier core consists of a three-stage common-source amplifier with transformer-coupled impedance matching networks. Fabricated in 65-nm CMOS process, the measured gain of the 0.19-mm² power amplifier at 60 GHz is 18.8 and 15 dB utilizing 1.4 and 1.0 V supply. Three-decibel band width of 4 GHz and P_1dB of 16.9 dBm is measured while consuming 424 mW from a 1.4-V supply. A maximum saturated output power of 18.3 dBm is measured with the 15.9% peak power added efficiency at 60 GHz. The measured insertion loss is 1.9 dB at 60 GHz. The proposed power amplifier achieves the highest power density (power/area) compared to the reported 60-GHz CMOS power amplifiers in 65 nm or older CMOS technologies.     

Design challenges of a fully integrated 65 nm CMOS half cascode SFDS PA

This paper presents the measurement results of a wideband multi-standards fully integrated 65 nm CMOS-power amplifier (PA). This PA is based on a half stacked folded pseudo-differential structure (HSFDS) cascoded. This demonstrator is composed by only one stage. It provides a maximal gain of 10 dB at 2.2 GHz with a bandwidth at −3 dB (B _w -3 dB) of 43%. At 1.95 GHz, the maximal output power (P _max ) is 23.3 dBm with a power added efficiency (PAE) of 12%. The output power at 1 dB compression (OCP ₁ ) is 21 dBm. At 2.4 GHz, Pmax is 23 dBm with a PAE of 11.3%. At this frequency, the OCP1 is 20 dBm.     

New fully-differential amplifier-less pipelined ADC with wide power scalability and ERBW

A 24 GHz power amplifier for direct-conversion transceiver using standard 0.18 μm CMOS technology is reported. The three-stage power amplifier comprises two cascaded cascode stages for high power gain, followed by a common-source stage for high power linearity. To increase the saturated output power (P_sat) and power-added efficiency (PAE), the output stage adopts a Wilkinson-power-divider- and combiner-based two-way power dividing and combining architecture. The power amplifier consumes 163.8 mW and achieves power gain (S₂₁) of 22.8 dB at 24 GHz. The corresponding 3-dB bandwidth of S₂₁ is 4.2 GHz, from 22.7 to 26.9 GHz. At 24 GHz, the power amplifier achieves P_sat of 15.9 dBm and maximum PAE of 14.6 %, an excellent result for a 24 GHz CMOS power amplifier. In addition, the measured output 1-dB compression point (OP_1dB) is 7 dBm at 24 GHz. These results demonstrate the proposed power amplifier architecture is very promising for 24 GHz short-range communication system applications.     

A fully integrated 23.2 dBm P1 dB CMOS power amplifier for the IEEE 802.11a with 29% PAE

A two-stage fully integrated power amplifier (PA) for the 802.11a standard is presented. The PA has been fabricated using UMC 0.18 μm CMOS technology. Measurement results show a power gain of 21.1 dB, a P_1 dB of 23.2 dBm and a P_SAT of 26.8 dBm. The PAE is 29% and it is kept high by means of several integrated inductors. These inductors present low-DC resistance and high Q characteristics. The inductors must include extra design considerations in order to withstand the high-current levels flowing through them, so that they have been called power inductors.     

Millimeter‐Wave High‐Linear CMOS Low‐Noise Amplifier Using Multiple‐Gate Transistors

A millimeter‐wave (mm‐wave) high‐linear low‐noise amplifier (LNA) is presented using a 0.18 µm standard CMOS process. To improve the linearity of mm‐wave LNAs, we adopted the multiple‐gate transistor (MGTR) topology used in the low frequency range. By using an MGTR having a different gate‐source bias at the last stage of LNAs, third‐order input intercept point (IIP3) and 1‐dB gain compression point (P_1dB) increase by 4.85 dBm and 4 dBm, respectively, without noise figure (NF) degradation. At 33 GHz, the proposed LNAs represent 9.5 dB gain, 7.13 dB NF, and 6.25 dBm IIP3.     

一种65 nm CMOS 60 GHz高增益功率放大器

设计了一种基于65 nm CMOS工艺的60 GHz功率放大器。采用共源共栅结构与电容中和共源级结构相结合的方式来提高功率放大器的增益,并采用两路差分结构来提高输出功率。采用片上变压器作为输入/输出匹配及级间匹配,以减小芯片的面积,从而降低成本。采用Cadence、ADS和Momentum等软件进行联合仿真。后仿真结果表明,在工作频段为60 GHz时,最大小信号增益为26 dB,最大功率附加效率为18.6%,饱和输出功率为15.2 dBm。该功率放大器具有高增益、高效率、低成本等优点。     

Design of power-controlled class1 Bluetooth CMOS power amplifier

In this paper, an RF power amplifier intended for class 1 Bluetooth application is designed using 0.35 µm CMOS technology. A layout-aware macromodel for the BSIM3v3 MOSFET transistor for RF applications including substrate effect is investigated and used in this design. The model is validated for a 0.35 μm CMOS process using a transistor with total width of 90 μm and 18 fingers and it shows excellent agreement with the f_t and S-parameter measurement data up to 6 GHz. The effects of pads and bond wires are also taken into consideration during the design process of the PA. After post-layout simulations, the amplifier delivers an output power of 19 dBm with 33.7% PAE under 3.3 V supply. This amplifier has a power control feature; its two stage circuit utilizes a cascode configuration in its first stage in order to use its bias pin as a power control input for the amplifier. Using this method, the power control range can be decreased down to 1.4 dBm which satisfies the Bluetooth standard. The chip is fabricated and is currently under testing.     

Current-mode design techniques in low-voltage 24-GHz RF CMOS receiver front-end

A new high frequency CMOS current-mode receiver front-end composed of a current-mode low noise amplifier (LNA) and a current-mode down-conversion mixer has been proposed in the frequency band of 24 GHz and fabricated in 0.13-μm 1P8M CMOS technology. The measurement of the current-mode receiver front-end exhibits a conversion gain of 11.3 dB, a noise figure (NF) of 14.2 dB, the input-referred 1-dB compression point (P_-1 dB)(P_{{-1}\,{\rm dB}}) of −13.5 dBm and the input-referred third-order intercept point (P _IIP3) of −1 dBm. The receiver dissipates 27.8 mW where the supply of LNA is 0.8 V and the supply of mixer is 1.2 V. The power consumption of output buffer is not included. The receiver front-end occupies the active area of 1.45 ×0.721.45 \times 0.72 mm² including testing pads. The measured results show that the proposed current-mode approach can be applied to a high-frequency receiver front-end and is capable of low-voltage applications in the advanced CMOS technologies.     

基于CMOS工艺的高效，高耐用性RF LDMOS器件

Two types of RF LDMOS devices, specified for application in the driver stage and output stage of a power amplifier, are designed based on a modified CMOS process. By optimizing the layout and process, the output capacitance per unit of gate width is as low as 225 fF/mm. The driver stage and output stage devices achieve an output power of 44 W with a PAE of 82% and 230 W with a PAE of 72.3%, respectively(P3dB compression) at 1 GHz. Both devices are capable of withstanding extremely severe ruggedness tests without any performance degradation. These tests are 3-5 dB overdrive, 10:1 voltage standing wave ratio mismatch load through all phase angles, and 40% drain overvoltage elevation at a working point of P3dB.     

A 900 MHz Zero‐IF RF Transceiver for IEEE 802.15.4g SUN OFDM Systems

This paper presents a 900 MHz zero‐IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ΔΣ fractional‐N frequency synthesizer. In the RF front end, re‐use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low‐noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current‐driven passive mixer in Rx and voltage‐mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty‐cycle in local oscillator clocks. The overall Rx‐baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a 0.18 μm CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of ?2 dBm, a sensitivity level of ?103 dBm at 100 Kbps with , an Rx input P_1dB of ?11 dBm, and an Rx input IP3 of ?2.3 dBm.     

一种输出匹配可调的、高线性度宽带功率放大器

采用自适应偏置技术和有源电感实现了一款输出匹配可调的、高线性度宽带功率放大器(PA)。自适应偏置技术抑制了功放管直流工作点的漂移,提高了PA的线性度。有源电感参与输出匹配,实现了输出匹配可调谐,该策略可调整因工艺偏差、封装寄生造成的输出匹配退化。利用软件ADS对电路进行验证,结果表明,在4 GHz频率下,输入1dB压缩点(Pin 1dB)为-7dBm,输出1dB压缩点(Pout 1dB)为11dBm,功率附加效率(PAE)为8.7%。在3.1GHz~4.8 GHz频段内,增益为(20.3±1.1)d B,输入、输出的回波损耗均小于-10dB。     

A High Gain 77 GHz Power Amplifier Operating at 0.7 V Based on 90 nm CMOS Technology

A 77 GHz 90 nm CMOS power amplifier (PA) demonstrates a gain of 17.4 dB and a saturated output power of 5.8 dBm at a low supply voltage of 0.7 V. To take care of hot-carrier injection degradation, the supply voltage is reduced from a standard voltage of 1.0 V. The saturated output power is increased to 9.4 dBm with a linear gain of 20.6 dB at 1.0 V operation. The amplifier consists of three-stage common-source nMOSFETs with gate widths of 40, 80, and 160 $mu{rm m}$. To our best knowledge, the developed PA shows the highest gain ever achieved for W-band CMOS amplifier. The measured temperature characteristics suggest that a simple compensation technique is possible by gate bias control.      

Implementation of a fully integrated 30-dBm RF CMOS linear power amplifier with power combiner

In this paper, a fully integrated 30-dBm UHF band differential power amplifier (PA) with transformer-type combiner is designed and fabricated in a 0.18-μm CMOS technology. For the high power PA design, proposed transformer network and the number of power cells is fully analyzed and optimized to find inductors dimensions. In order to improve both the linear operating range and the power efficiency simultaneously, a parallel combination of the class AB and the class C amplifier in power cells was employed. The PA delivers an output power of 29 dBm and a power-added efficiency of 24% with a power gain of 20 dB, including the losses of the bond-wires.     

Monolithic SiGe HBT Feedforward Variable Gain Amplifiers for 5 GHz Applications

Monolithic SiGe heterojunction bipolar transistor (HBT) variable gain amplifiers (VGAs) with a feedforward configuration have been newly developed for 5 GHz applications. Two types of the feedforward VGAs have been made: one using a coupled‐emitter resistor and the other using an HBT‐based current source. At 5.2 GHz, both of the VGAs achieve a dynamic gain‐control range of 23 dB with a control‐voltage range from 0.4 to 2.6 V. The gain‐tuning sensitivity is 90 mV/dB. At V_CTRL= 2.4 V, the 1 dB compression output power, P_1‐dB, and dc bias current are 0 dBm and 59 mA in a VGA with an emitter resistor and ‐1.8 dBm and 71mA in a VGA with a constant current source, respectively.     

A 5.8 GHz 1 V Linear Power Amplifier Using a Novel On-Chip Transformer Power Combiner in Standard 90 nm CMOS

A fully integrated 5.8 GHz Class AB linear power amplifier (PA) in a standard 90 nm CMOS process using thin oxide transistors utilizes a novel on-chip transformer power combining network. The transformer combines the power of four push-pull stages with low insertion loss over the bandwidth of interest and is compatible with standard CMOS process without any additional analog or RF enhancements. With a 1 V power supply, the PA achieves 24.3 dBm maximum output power at a peak drain efficiency of 27% and 20.5 dBm output power at the 1 dB compression point.     

2.4GHz CMOS高线性功率放大器

采用A类与B类并联的结构,设计了一种2.4GHz高线性功率放大器.输入信号较小时,A类放大器起主要作用;随着输入信号的增大,B类放大器起的作用越来越明显,来补偿A类的压缩,由此显著提高了放大器的线性度.电路主体为共栅管采用自偏置方法的共源共栅结构,提升了功放大信号工作时的可靠性.电路采用中芯国际0.13 μmCMOS工...     

2.4GHz 0.35-μm CMOS全集成线性功率放大器设计

片上系统射频功率放大器是射频前端的重要单元.通过分析和对比各类功率放大器的特点,电路采用SMIC0.35-μm CMOS工艺设计2.4 GHz WLAN全集成线性功率放大器.论文中设计的功率放大器采用不同结构的两级放大,驱动级采用共源共栅A类结构组成,输出级采用共源级大MOSFET管组成.电路采用SMIC 0.35-μ...     

A fully integrated 24-dBm CMOS power amplifier for 802.11a WLAN applications

A fully integrated 24-dBm complementary metal oxide semiconductor (CMOS) power amplifier (PA) for 5-GHz WLAN applications is implemented using 0.18-/spl mu/m CMOS foundry process. It consists of differential three-stage amplifiers and fully integrated input/output matching circuits. The amplifier shows a P/sub 1/ of 21.8 dBm, power added efficiency of 13%, and gain of 21 dB, respectively. The saturated output power is above 24.1 dBm. This shows the highest output power among the reported 5-GHz CMOS PAs as well as completely satisfying IEEE 802.11a transmitter back off requirement.     

带温度补偿的Ka波段CMOS堆叠功率放大器设计

介绍了一款基于55 nm CMOS工艺,带温度补偿电路的Ka波段堆叠高效功率放大器（power amplifier,PA）.采用了一种新型的针对晶体管堆叠结构的温度补偿电路,该补偿电路由两个二极管和四个电阻组成,结构简单,易于实现.通过调整堆叠放大器各个栅极偏置电路中的电压,使得PA随温度变化的增益和输出功率得到有效补偿,增强了电路的可靠性和热稳定性.基于Agilent ADS软件的版图仿真结果显示:电路的最大输出功率为20.1 dBm,频带内功率附加效率（power additional efficiency,PAE）为20%~30%,大信号功率-1 dB带宽为15 GHz（46%）.在-40℃到125℃的温度范围内,采用新型温补偏置电路与传统偏置电路相比,小信号增益的温度波动从2.2 dB改善到0.1 dB,显著提高了功放的热稳定性,证明了所提出的温度补偿电路对于在宽温度范围内校正功率放大器增益变化的有效性.