A Die‐Selection Method Using Search‐Space Conditions for Yield Enhancement in 3D Memory

Three‐dimensional (3D) memories using through‐silicon vias (TSVs) as vertical buses across memory layers will likely be the first commercial application of 3D integrated circuit technology. The memory dies to stack together in a 3D memory are selected by a die‐selection method. The conventional die‐selection methods do not result in a high‐enough yields of 3D memories because 3D memories are typically composed of known‐good‐dies (KGDs), which are repaired using self‐contained redundancies. In 3D memory, redundancy sharing between neighboring vertical memory dies using TSVs is an effective strategy for yield enhancement. With the redundancy sharing strategy, a known‐bad‐die (KBD) possibly becomes a KGD after bonding. In this paper, we propose a novel die‐selection method using KBDs as well as KGDs for yield enhancement in 3D memory. The proposed die‐selection method uses three search‐space conditions, which can reduce the search space for selecting memory dies to manufacture 3D memories. Simulation results show that the proposed die‐selection method can significantly improve the yield of 3D memories in various fault distributions.     

相邻层冗余共享的三维存储器成品率优化方法

存储裸片堆叠方案和冗余共享策略对提高三维存储器成品率有重要影响.为提高三维存储器的成品率并且减少行列冗余所需的TSVs数量,提出了一种相邻层冗余共享结构.该冗余共享结构使得每层存储裸片的行列冗余不仅能被本层使用,而且能被相邻层使用.并在此结构的基础上,提出了一种新的存储裸片堆叠方案.该方案通过构建存储裸片的选择限制条件,每次选中适合的存储裸片来堆叠三维存储器以充分利用行列冗余.实验结果表明,与国际上同类方法相比,所提方案有效地提高了三维存储器的成品率,并且减少了行列冗余所需的TSVs数量.     

Thermal‐Aware Floorplanning with Min‐cut Die Partition for 3D ICs

Three‐dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through‐silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal‐aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal‐aware floorplanning with min‐cut die partitioning for 3D ICs. The proposed min‐cut die partition methodology minimizes the number of connections between partitions based on the min‐cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal‐aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run‐time.     

A Fast Built-in Redundancy Analysis for Memories With Optimal Repair Rate Using a Line-Based Search Tree

With the growth of memory capacity and density, test cost and yield improvement are becoming more important. In the case of embedded memories for systems-on-a-chip (SOC), built-in redundancy analysis (BIRA) is widely used as a solution to solve quality and yield issues by replacing faulty cells with extra good cells. However, previous BIRA approaches focused mainly on embedded memories rather than commodity memories. Many BIRA approaches require extra hardware overhead to achieve the optimal repair rate, which means that 100% of solution detection is guaranteed for intrinsically repairable dies, or they suffer a loss of repair rate to minimize the hardware overhead. In order to achieve both low area overhead and optimal repair rate, a novel BIRA approach is proposed and it builds a line-based searching tree. The proposed BIRA minimizes the storage capacity requirements to store faulty address information by dropping all unnecessary faulty addresses for inherently repairable die. The proposed BIRA analyzes redundancies quickly and efficiently with optimal repair rate by using a selected fail count comparison algorithm. Experimental results show that the proposed BIRA achieves optimal repair rate, fast analysis speed, and nearly optimal repair solutions with a relatively small area overhead.      

Voltage Optimization of Power Delivery Networks through Power Bump and TSV Placement in 3D ICs

To reduce interconnect delay and power consumption while improving chip performance, a three‐dimensional integrated circuit (3D IC) has been developed with die‐stacking and through‐silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR‐drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR‐drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR‐drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.     

Yield enhancement techniques for 3-dimensional random access memories

As the advances of process technology keep growing, three-dimensional (3D) integration with through silicon vias is a new alternative solution to extend Moore’s law especially for random access memories (RAMs). In general, the reliability and fabrication yield of the traditional 2D memories can be improved by the incorporation of some form of redundancy. However, for 3D integration, the scenarios for the repair process are totally different. The redundancy exclusively added in a memory tier can also be reused to repair defects in the other memory tier after the bonding process. That is, the concept of inter-tier redundancy can be exploited to further increase the yield of 3D memories. Die-to-die and die-to-wafer bonding can be adopted. In this paper, we propose an efficient die-stacking flow and the corresponding built-in self-repair architectures for yield enhancement of 3D memories. The matching problem for die stacking can be converted into a bipartite graph maximal matching problem and the traditional algorithm can be used to solve this problem. Experimental results show that the proposed stacking flow, algorithm, and the corresponding BISR (built-in self-repair) architecture can improve fabrication yield significantly.     

基于云模型进化算法的硅通孔数量受约束的3D NoC测试规划研究

针对硅通孔(TSV)价格昂贵、占用芯片面积大等问题,该文采用基于云模型的进化算法对TSV数量受约束的3维片上网络(3D NoC)进行测试规划研究,以优化测试时间,并探讨TSV的分配对3D NoC测试的影响,进一步优化3D NoC在测试模式下的TSV数量。该方法将基于云模型的进化算法、小生境技术以及遗传算法的杂交技术结合起来,有效运用遗传、优胜劣汰以及保持群落的多样性等理念,以提高算法的寻优速度和寻优精度。研究结果表明,该算法既能有效避免陷入局部最优解,又能提高全局寻优能力和收敛速度,缩短了测试时间,并且优化了3D NoC的测试TSV数量,提高了TSV的利用率。     

Fine grain thermal modeling and experimental validation of 3D-ICs

3D die stacking is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si die or through the multilayer interconnections. The complexity of these structures combined with reduced thermal spreading in the thinned dies complicate the thermal analysis of a stacked die structure. In this paper a methodology is presented to perform a detailed thermal analysis of stacked die packages including the complete back end of line structure (BEOL), interconnection between the dies and the complete electrical design layout of all the stacked dies. The calculations are performed by 3D numerical techniques and the approach allows importing the full electrical design of all the dies in the stack. The methodology is demonstrated on a 2 stacked die structure in a BGA package. For this case the influence of through-Si vias (TSVs) on the temperature distribution is studied. The modeling results are experimentally validated with a dedicated test vehicle. A thermal test chip with integrated heaters and diodes as thermals sensors is used to successfully validate the detailed temperature profile of the hot spots in the top die of the die stack.     

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

Process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a 3D Design-for-Test (DfT) architecture for such 3D-SICs that allows pre-bond die testing as well as mid-bond and post-bond stack testing. The architecture enables a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units, which allows flexible optimization of the 3D-SIC test flow and provides yield monitoring and first-order fault diagnosis. The architecture builds on and reuses existing DfT hardware at the core, die, and product level. Its main new component is a die-level wrapper, which can be based on either IEEE Std 1149.1 or IEEE Std 1500. The paper presents a conceptual overview of the architecture, as well as implementation aspects. Experimental results show that the implementation costs are negligible for medium to large dies.     

A Review of Three‐Dimensional Resistive Switching Cross‐Bar Array Memories from the Integration and Materials Property Points of View

Issues in the circuitry, integration, and material properties of the two‐dimensional (2D) and three‐dimensional (3D) crossbar array (CBA)‐type resistance switching memories are described. Two important quantitative guidelines for the memory integration are provided with respect to the required numbers of signal wires and sneak current paths. The advantage of 3D CBAs over 2D CBAs (i.e., the decrease in effect memory cell size) can be exploited only under certain limited conditions due to the increased area and layout complexity of the periphery circuits. The sneak current problem can be mitigated by the adoption of different voltage application schemes and various selection devices. These have critical correlations, however, and depend on the involved types of resistance switching memory. The problem is quantitatively dealt with using the generalized equation for the overall resistance of the parasitic current paths. Atomic layer deposition is discussed in detail as the most feasible fabrication process of 3D CBAs because it can provide the device with the necessary conformality and atomic‐level accuracy in thickness control. Other subsidiary issues related to the line resistance, maximum available current, and fabrication technologies are also reviewed. Finally, a summary and outlook on various other applications of 3D CBAs are provided.     

基于哈希表的高效存储器内建自修复方法

 现有存储器内建自修复方法要么遍历式地址比较效率低,要么并行地址比较功耗高,都不适用于大故障数存储器.对此,本文提出一种高效的存储器内建自修复方法,该方法对占故障主体的单元故障地址以哈希表形式进行存储,以利用哈希表的快速搜索特性提升地址比较效率.本文方法修复后的存储器在1个时钟周期内即可完成地址比较,修复后存储器性能不受任何影响,与目前广泛采用的基于CAM的方法处于同一水平,但功耗方面却具有明显优势.计算机模拟实验表明,对于512×512×8bits的存储器在同等冗余开销的情况下本文方法修复率相对于ESP方法平均提高了32.25%.     

A Novel Built-In Self-Repair Approach for Embedded RAMs

In this paper, a novel built-in self-repair approach, block-level reconfiguration architecture, is proposed. Our approach is based on the concept of divided word line (DWL) for high-capacity memories, including SRAMs and DRAMs. This concept is widely used in low-power memory designs. However, the characteristics of divided word line memories have not been used for fault-tolerant applications. Therefore, we propose the block_repair fault-tolerant architecture based on the structure of DWL for high-capacity memories. The redundant rows of a memory array are divided into blocks and reconfiguration is performed at the block level instead of the traditional row level. Our fault-tolerant architecture can improve the yield for memory fabrication significantly. Moreover, the characteristics of low power and fast access time of DWL memories are also preserved. The reconfiguration mechanism of our block_repair architecture requires negligible hardware overhead. According to experimental results, the hardware overheads are less than 0.73% and 0.48% for 256-Kbit SRAMs and 8-Mbit DRAMs, respectively. The repair rate of our approach with previous memory repair algorithms is compared. It is found that block_repair approach improves repair rate significantly. The yield improvement over traditional row-based approaches is also analyzed. Simulated results show that the present approach can significantly improve fabrication yield.     

考虑温度因素的3D芯片TSV容错结构设计

相比于2D芯片,3D芯片具有更高的功率密度和更低的热导率。针对散热问题,多层3D芯片一般采用具有较高热导率的铜填充硅通孔(TSV)。为提高3D芯片的成品率,在温度条件限制下,对3D芯片进行TSV的容错结构设计非常重要。分析了带有TSV的3D芯片温度模型,提出了3D芯片温度模型的TSV修复方法。根据温度要求设计总的TSV数,将这些TSV分为若干个组,每组由m个信号TSV和n个冗余TSV组成,实现了组内和组间信号的TSV修复。实验结果表明,该TSV容错结构不仅有较高修复效率,而且具有较好散热效果。     

Combining replication and checkpointing redundancies for reducing resiliency overhead

We herein propose a heuristic redundancy selection algorithm that combines resubmission, replication, and checkpointing redundancies to reduce the resiliency overhead in fault‐tolerant workflow scheduling. The appropriate combination of these redundancies for workflow tasks is obtained in two consecutive phases. First, to compute the replication vector (number of task replicas), we apportion the set of provisioned resources among concurrently executing tasks according to their needs. Subsequently, we obtain the optimal checkpointing interval for each task as a function of the number of replicas and characteristics of tasks and computational environment. We formulate the problem of obtaining the optimal checkpointing interval for replicated tasks in situations where checkpoint files can be exchanged among computational resources. The results of our simulation experiments, on both randomly generated workflow graphs and real‐world applications, demonstrated that both the proposed replication vector computation algorithm and the proposed checkpointing scheme reduced the resiliency overhead.     

A cross layer approach for efficient thermal management in 3D stacked SoCs

3D stacking of silicon dies via Through Silicon Vias (TSVs) is an emerging technology to increase performance, energy efficiency and integration density of today's and future System-on-Chips (SoCs). Especially the stacking of Wide I/O DRAMs on top of a logic die is a very promising approach to tackle the memory wall and energy efficiency challenge. The potential of this type of stacking is currently under investigation by many research groups and companies in particular for mobile devices. There, for instance, the baseband processing and the application processor can be implemented on the same single logic die. On top of this die one or several Wide I/O DRAMs are stacked. An example of such a SoC is the WIOMING chip [15]. However, new challenges emerge, especially thermal management, which is already a very demanding challenge in current 2D SoCs. With 3D SoCs this problem exacerbates due to reliability issues such as the temperature sensitivity of DRAMs, i.e., the retention time of a DRAM cell largely decreases with increasing temperature.In this paper, we show a holistic cross layer reliability approach for efficient reliability management starting from measuring and modeling of DRAM retention errors, which finally leads to optimizations for specific applications. These optimizations exploit the data lifetime and the inherent error resilience of the application, which is for instance given in the probabilistic behavior of wireless communications.     

Mechanical and Electrical Reliability Assessment of Stacking of Ultrathin Chips on Si Interposer Using Back-to-Face Architecture

Chip-to-wafer stacking is a key enabling technology for two and half dimension (2.5D) as well as for three dimension (3D), with technological challenges driven by the increase of the die surface and the number of input/outputs (I/Os) and the reduction of the vertical dimensions. In our investigation, chips were assembled using a back-to-face approach on a silicon interposer containing copper through-silicon vias (TSVs). This technology is based on the realization of a high-topology redistribution layer passing over the dies bonded with the active face up on the interposer by using a polymer layer. This architecture is attractive because of the reduction of the chip thickness to an ultrathin dimension, and can offer substantial advantages in terms of design flexibility and technology cost. In this architecture, chip bonding strategies are compared: several bonding materials were tested either on the die side using die-attach film or on the bottom side of the interposer using wafer-level spin-coated polymers. Then, a novel brick (sequence) of processes consisting of high-topology encapsulation and metallization was fully developed to connect the top dies to the bottom wafer. The resulting structure has been modeled through the temperature cycles seen during fabrication using a thermomechanical finite element modeling (FEM) simulation for different geometries and materials. The results indicate a moderate level of stress in the stacked film layers with some concentration in localized regions of the topology. Electrical tests have also been completed at the wafer level, showing low resistances and high yield at front-side and at the back-side level after TSV exposure. Successful reliability tests have also been carried out and support the good mechanical behavior of this integration.     

Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

Recent enhancements in process development enable the fabrication of three dimensional stacked ICs (3D-SICs) such as memories based on Wafer-to-Wafer (W2W) stacking. One of the major challenges facing W2W stacking is the low compound yield. This paper investigates compound yield improvement for W2W stacked memories using layer redundancy and compares it to wafer matching. First, an analytical model is provided to prove the added value of layer redundancy. Second, the impact of such a scheme on the manufacturing cost is evaluated. Third, these two parts are integrated to analyze the trade-off between yield improvement and its associated cost; the realized yield improvement is also compared to yield gain obtained when using wafer matching. The simulation results show that for higher stack sizes layer redundancy realizes a significant yield improvement as compared to wafer matching, even at lower cost. For example, for a stack size of six stacked layers and a die yield of 85?%, a relative yield improvement of 118.79?% is obtained with two redundant layers, while this is 14.03?% only with wafer matching. The additional cost due to redundancy pays off; the cost of producing a good 3D stacked memory chip reduces with 37.68?% when using layer redundancy and only with 12.48?% when using wafer matching. Moreover, the results show that the benefits of layer redundancy become extremely significant for lower die yields. Finally, layer redundancy and wafer matching are integrated to obtain further cost reductions.     

Dynamic Self‐Repair Architectures for Defective Through‐silicon Vias

Three‐dimensional integration technology results in area savings, platform power savings, and an increase in performance. Through‐silicon via (TSV) assembly and manufacturing processes can potentially introduce defects. This may result in increases in manufacturing and test costs and will cause a yield problem. To improve the yield, spare TSVs can be included to repair defective TSVs. This paper proposes a new built‐in self‐test feature to identify defective TSV channels. For defective TSVs, this paper also introduces dynamic self‐repair architectures using code‐based and hardware‐mapping based repair.     

A delay‐centric parallel multi‐path routing protocol for cognitive radio ad hoc networks

In this paper, we develop a delay‐centric parallel multi‐path routing protocol for multi‐hop cognitive radio ad hoc networks. First, we analyze the end‐to‐end delay of multi‐path routing based on queueing theory and present a new dynamic traffic assignment scheme for multi‐path routing with the objective of minimizing end‐to‐end delay, considering both spectrum availability and link data rate. The problem is formulated as a convex problem and solved by a gradient‐based search method to obtain optimal traffic assignments. Furthermore, a heuristic decentralized traffic assignment scheme for multi‐path routing is presented. Then, based on the delay analysis and the 3D conflict graph that captures spectrum opportunity and interference among paths, we present a route discovery and selection scheme. Via extensive NS2‐based simulation, we show that the proposed protocol outperforms the benchmark protocols significantly and achieves the shortest end‐to‐end delay. Copyright © 2015 John Wiley & Sons, Ltd.     

A new accurate yield prediction method for system-LSI embedded memories

The authors propose a new accurate yield prediction method for system-LSI embedded memories to improve the productivity of chips. Their new method is based on the failure-related yield prediction method in which failure bits in memory are tested to see whether they are repairable or not by using built-in redundancies. The important concept of the new method is called "repairable matrix' (RM). In RM, rm/sub ij/=1 means that i row redundancy sets and j column redundancy sets are needed for repair, where rm/sub ij/ is an element of the matrix. Here, RM can indicate all the candidate combinations of the number of row and column redundancy sets for repair. The new yield prediction method using RM solves two problems, "asymmetric repair' and "link set.' These have a significant effect on accurate yield prediction but have not yet been approached by conventional analytical methods. The calculation of yield by the new method is demonstrated in two kinds of advanced memory devices that have different design rules, failure situations, and redundancy designs. The calculated results are consistent with the actual yield. On average, the difference in accuracy between the new method and conventional analytical methods is about 5%.