改进DICE结构的D触发器抗SEU设计

基于DICE结构主-从型D触发器的抗辐照加固方法的研究,在原有双立互锁存储单元(DICE)结构D触发器的基础上改进电路结构,其主锁存器采用抗静态、动态单粒子翻转(SEU)设计,从锁存器保留原有的DICE结构。主锁存器根据电阻加固与RC滤波的原理,将晶体管作电阻使用,使得电路中存在RC滤波,通过设置晶体管合理的宽长比,使其与晶体管间隔的节点的电平在SEU期间不变化,保持原电平状态,从而使电路具有抗动态SEU的能力。Spectre仿真结果表明,改进的D触发器既具有抗动态SEU能力,又保留了DICE抗静态SEU较好的优点,其抗单粒子翻转效果较好。     

动态阈值触发器

从阈值来谈,触发器通常可分为两类,一类为普通的触发器,其输入信号从小变大(下面简称正向)时触发触发器的电子即正向阈值V_(T+)与输入信号从大变小(下面简称反向)时触发触发器的电平即反向阈值V_(T-)相等,即V_     

基于神经元MOS器件的施密特触发器设计

为实现施密特触发器低功耗、回差可控,将神经元MOS器件的控阈技术用于施密特触发器的设计中,设计出基于神经元MOS器件的施密特触发器,并且进一步提出了外部可控回差的施密特触发器的设计.通过HSPICE对电路进行模拟,实验表明此设计仅需2个MOS管,功耗降低30%.并且这种通过改变外部电压值调整回差电压大小的方法比以往的方法更为方便实用.     

高速锁存器半稳态发生概率的分析及优化

提出了锁存器半稳态发生概率（MSS）的优化公式,引入半稳态发生概率相关因子γ,给出了锁存器PMOS与NMOS管宽长比之比及加速电容与γ的相互关系。同时,采用交流小信号频域分析法,对高速比较器中的锁存器的宽长比进行了优化,给出了锁存器的最佳宽长比,以使半稳态的产生机率达到最小。两种方法优化的结果相一致。     

两种环栅MOS管的等效宽长比分析研究

对抗总剂量辐射加固中常用的两种环栅MOS管的等效宽长比进行了研究。对b字形环栅管的宽长比计算模型进行验证,发现b字形环栅结构无法实现小宽长比。分别在0.35 μm和0.18 μm工艺下进行流片测试,发现该计算模型的准确性较低,测试样品的宽长比最大偏差超过30%。针对b字形环栅结构的缺点,设计了8字形环栅结构,可实现小宽长比管和倒比管,宽长比的值易于预估,且几何尺寸与直栅结构相近。在0.18 μm工艺下进行流片验证。测试结果表明,8字形环栅管的饱和电流偏差值均在6%以内,宽长比预估值的准确性较高,能够非常方便地被应用于实际设计中。     

扫描法可测性设计中扫描触发器的最优实现

提出了扫描法可测性设计中扫描触发器的最优实现方法，采用该方法每个触发器仅需增加２个ＭＯＳ管即可构成扫描触发器，比用传统方法减少１２个ＭＯＳ管，而增加的额外管脚数与传统方法一样。这样，即使采用全扫描设计，也仅需较小的芯片面积。     

CCD图像传感器输出节点电荷容量设计

从电荷耦合器件(CCD)的满阱电荷容量和片上放大器的工作电压范围两个方面对器件的节点电荷容量进行了设计,并推导出输出节点电荷容量设计的优化公式。从公式中可以看出,输出节点的电荷容量设计除了需要满足CCD信号电荷转移本身所需的容量值以外,还必须保证节点处的电压变化范围在输出放大器线性工作区域内,才能使信号电荷能够完整线性地被放大器输出,从而保证CCD器件整体的非线性和满阱容量性能。因此,输出节点电荷容量的设计除了需要考虑节点自身的电容外,还应综合考虑输出放大器相关MOS管的宽长比、阈值电压、工作电压等因素。     

钟控神经MOS管的改进及其在多值电路中的应用

首先对钟控神经MOS管进行研究,提出了相应的改进方法.然后采用此改进的钟控神经MOS管设计了一种新型多值触发器.与传统的触发器相比较,此多值触发器具有结构简单、速度快、功耗低等特点;而且无需改变电路结构就可实现不同基的多值触发器.PSPICE模拟证明了所设计的电路具有正确的逻辑功能.     

对《MOS管阈值电压的理论修正》一文的商榷

《半导体技术》1983年第3期中的《MOS管阈值电压的理论修正》(以下简称《理论修正》)一文,从实测的MOS管阈值电压与宽长比W/L有关并比理论值显著增大的现象出发,提出了一种主要发生在长沟道MOS管中的“沟道电阻效应”,并据此对传统的阈值电压公式作了理论修正.我们认为其中的一些概念需要加以澄清,问题的实质是对阈值电压的定义.此外,该文在计算沟道离子注入对阈值电压的调整时所用的公式也欠妥.     

毫米波段非谐振型低副瓣波导缝隙天线的改进型设计方法

在毫米波段,为了更精确、快速地设计出非谐振型低副瓣波导缝隙天线,提出了一种改进型解析方法,具体方法为在传统的斯蒂文生公式引入一个修正因子。该修正因子可大幅度提高波导宽边上的径向缝隙偏移量的解析计算精度。一般情况下,传统斯蒂文生公式仅适用于长宽比大于10∶1的窄缝设计。而此方法则可用于低副瓣、长宽比接近4∶1的宽缝波导缝隙天线的快速设计。对修正公式进行了理论分析,并使用改进型公式,设计加工出了一个工作频率为60 GHz的波导缝隙原型天线,实测增益和副瓣电平分别为14.8 dB和-25 dB。仿真结果以及测试数据吻合良好,证实了此改进型方法的有效性。     

RS trigger based relaxation oscillator for temperature measurement circuit

Resistance-to-time converter is always used for digital temperature measurement. An reset-set （RS） trigger based, relaxation oscillator based temperature measurement circuit, which is used to convert the change of thermistor sensor into a frequency signal for later processing, has been presented in this article. The RS trigger, which is composed of two inverters designed with distinct logical transition threshold voltages by changing the metal-oxide-semiconductor （MOS） transistor gains, has the same function as the Schmitt trigger in the relaxation oscillator. The advantage of the RS trigger based Schmitt trigger is that it reduces the dependence to supply voltage, chip temperature, and process variation. This temperature measurement circuit has been applied in a clinical thermometer chip that can measure temperature to an accuracy of better than 0.05 ℃ down to 1.1 V battery voltage. It is fabricated in 0.5 μm double metal single poly complementary MOS （CMOS） process.     

一种高速低耗全摆幅BiCMOS集成施密特触发器

通过分析国外流行的一种 Bi CMOS集成施密特触发门 ,提出了一种高速、低功耗、全摆幅输出的Bi CMOS施密特触发器。该器件中单、双极型电路优势互补 ,电源电压为 1 .5 V,实现了优于同类产品的全摆幅输出 ,且其开关速度高于同类 CMOS产品的 1 3倍以上 ,因此特别适用于高速数字通信系统中     

基于开关信号理论的电流型CMOS多值施密特电路设计

以开关信号理论为指导,建立了描述电流型CMOS多值施密特电路中阈值控制电路的电流传输开关运算.在此基础上,提出了新的电流型CMOS三值和四值施密特触发器设计.所设计的电路可提供多值电流和电压输出信号,回差电流的大小只需通过改变MOS管的尺寸比来调节.所提出的电路较之以往设计具有结构简单,回差值调整容易以及可在较低电压下工作等特点.采用TSMC 0.25 μ m CMOS工艺参数和1.5V电压的HSPICE模拟结果验证了所提出设计方案的有效性和电路所具有的理想回差特性.     

Estimation of high performance in Schmitt triggers with stacking power‐gating techniques in 45 nm CMOS technology

In the complementary metal oxide semiconductor (CMOS) nanoscale technology ground bounce noise and power consumption are becoming important metric. In presented paper, low leakage Schmitt trigger circuits are proposed for wave shaping or cleaning process with low ground bounce noise. Schmitt trigger play important role in communication electronics. Power‐gating and stacking power‐gating techniques have provided for maintaining the parameter of Schmitt trigger. An ideal approach has been investigated with stacking power‐gating technique. For further reduction in peak of ground bounce noise during sleep to active (power) mode transition, we have performed simulations using cadence specter 45 nm standard CMOS technology at nominal temperature (27°C) with supply voltage V_dd = 0.7 V and input voltage vary from 0.7 V to 1.5 V. The simulation results show that a proposed design provide efficient 6 T and 4 T Schmitt triggers in term of minimum leakage power (8.18 fW), active power (17.80 pW), ground bounce noise (1.65 μV) and propagation delay (1.98 ns), transconductance (4.51 × 10^?14 S), voltage gain (29.44 dB), hysteresis width (11.07 V) and efficiency (64.68%). Reported devices use for low‐power communication systems. Copyright © 2013 John Wiley & Sons, Ltd.     

A new Schmitt trigger circuit in a 0.13-/spl mu/m 1/2.5-V CMOS process to receive 3.3-V input signals

A new Schmitt trigger circuit, which is implemented by low-voltage devices to receive the high-voltage input signals without gate-oxide reliability problem, is proposed. The new proposed circuit, which can be operated in a 3.3-V signal environment without suffering high-voltage gate-oxide overstress, has been fabricated in a 0.13-/spl mu/m 1/2.5-V 1P8M CMOS process. The experimental results have confirmed that the measured transition threshold voltages of the new proposed Schmitt trigger circuit are about 1 and 2.5 V, respectively. The new proposed Schmitt trigger circuit is suitable for mixed-voltage input-output interfaces to receive input signals and reject input noise.     

一种基于0.18μm CMOS工艺的上电复位电路

介绍了一种采用0.18μm CMOS工艺制作的上电复位电路。为了满足低电源电压的设计要求,采用低阈值电压(约0V)NMOS管和设计的电路结构,获得了合适的复位电压点;利用反馈结构加速充电,提高了复位信号的陡峭度;利用施密特触发器,增加了电路的迟滞效果。电路全部采用MOS管设计,大大缩小了版图面积。该上电复位电路用于一种数模混合信号芯片,采用0.18μm CMOS工艺进行流片。芯片样品电路测试表明,该上电复位电路工作状态正常。     

三值电压型CMOS施密特电路研究

首先对二值ＣＭＯＳ施密特电路的设计思想进行了分析,指出设计施密特电路的关键为阈值控制电路。根据三值ＣＭＯＳ电路有两个信号检测阈的特点,提出了通过文字电路将两个检测阈分离后进行分别控制并由文字电路的输出去控制ＣＭＯＳ传输门的设计方法,由此设计了三值ＣＭＯＳ施密特反相器。ＰＳＰＩＣＥ模拟证明了所设计的电路具有理想的施密特电路功能     

A high-speed differential CMOS Schmitt trigger with regenerative current feedback and adjustable hysteresis

This paper presents a brief overview of Schmitt triggers and proposes a new differential current-feedback Schmitt trigger. The hysteresis of the proposed Schmitt trigger is generated using regenerative current feedback and can be adjusted by varying the current of the regenerative feedback network. The center of the hysteresis can also be adjusted by varying the common-mode input voltage. The proposed Schmitt trigger has the characteristics of current-mode circuits, making it particularly attractive for low-voltage high-speed applications. The proposed Schmitt trigger has been designed in TSMC-0.18 μm 1.8 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3V3 device models. Simulation results are presented.     

Design techniques for ASK demodulators of passive wireless microsystems: a state-of-the-art review

This paper presents a brief overview of Schmitt triggers and proposes a new differential current-feedback Schmitt trigger. The hysteresis of the proposed Schmitt trigger is generated using regenerative current feedback and can be adjusted by varying the current of the regenerative feedback network. The center of the hysteresis can also be adjusted by varying the common-mode input voltage. The proposed Schmitt trigger has the characteristics of current-mode circuits, making it particularly attractive for low-voltage high-speed applications. The proposed Schmitt trigger has been designed in TSMC-0.18 μm 1.8 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3V3 device models. Simulation results are presented.