基于In-Zn-Ti-O氧化物半导体材料的薄膜晶体管

在室温下制备了基于In-Zn-Ti-O氧化物半导体的薄膜晶体管,氧化物沟道层中In、Zn、Ti的摩尔比为49∶49∶2。所制备的器件场致迁移率达到9.8cm2/V.s,开关比大于105,亚阈值摆幅0.61V/dec。和未掺Ti器件的比较表明,掺Ti能使器件阈值正向变化,对场致迁移率也有提高作用。     

等离子体处理对非晶IGZO柔性薄膜晶体管性能的影响

本文研究了柔性基板上的薄膜晶体管,使用IGZO作为有源层,栅极绝缘层采用NH3等离子体和N2O等离子体分别进行处理,研究器件性能变化。结果表明等离子体类型及处理时间对阈值电压、场效应迁移率、开关比、亚阈值摆幅（SS）和偏压稳定性都有影响。TFT器件用NH3等离子体处理10秒显示出最佳的器件性能,阈值电压达到0.34 V,场效应迁移率为15.97 cm2/Vs,开关比为6.33×107,亚阈值摆幅为0.36 V /dec。本文提出的柔性IGZO-TFT是下一代柔性显示驱动装置较好选择。     

溅射法制备钇掺杂铟锌氧薄膜和器件特性研究王丹丹,王卿璞*,王汉斌,张锡健,武丽伟,李福杰,袁帅中国,济南,山东大学物理学院

室温下,采用射频磁控溅射法分别在钠钙玻璃和P型硅衬底上制备了不同厚度的钇掺杂铟锌氧薄膜。研究了薄膜的结构形貌和光学特性。以P型硅为栅极制备了底栅结构的YIZO薄膜晶体管,并研究了器件的输出和转移特性。研究发现,室温下制备的所有Y掺杂IZO薄膜均为非晶结构,YIZO薄膜晶体管均为n沟道耗尽型器件。有源层厚度为20nm的器件的开关电流比超过105,亚阈值摆幅为2.20 V/decade,阈值电压为-1.0V, 饱和迁移率为0.57 cm2/ V·s。     

溶液法制程对有机薄膜晶体管性能影响的研究

基于新型的聚合物绝缘材料和半导体材料,采用溶液法旋涂工艺制作有机薄膜晶体管,通过优化聚合物半导体材料的溶剂、旋涂速度、退火温度等条件,提高有机薄膜晶体管的器件性能。结果表明,不同溶剂溶解半导体对制成的有机薄膜晶体管的迁移率影响明显;半导体层旋涂速度过慢和退火温度过低都会降低有机薄膜晶体管的性能。当采用1,2,4-三氯苯(TCB)作为半导体溶剂,旋涂速度为3 000r/min,后烘温度为190℃时,有机薄膜晶体管的迁移率可以达到约0.5cm2·V-1·s-1,亚阈值摆幅降至约0.6V/dec,开关比大于106。     

高性能ZnSnO∶Li/ZnSnO双有源层TFT电学性能的研究

双有源层以迁移率高、开关比高、大面积均匀性好等优点成为近年研究热点。采用射频磁控溅射方法，制备了ZnSnO∶Li/ZnSnO薄膜晶体管(TFT),对其电学特性进行了测试，并研究了器件迁移率提高的原因及其内在的微观机制。研究发现，ZTO∶Li/ZTO TFT表现出了良好的电学特性，其场效应迁移为率为13.98 cm²/(V·s),亚阈值摆幅为0.84 V/dec,开关比为1.13×10⁹。通过XPS对其薄膜进行分析发现，Li的引入导致薄膜中氧和金属结合键的浓度增加，氧空位浓度减少，从而使得TFT的迁移率增大，开关比增大，亚阈值摆幅减小。     

基片温度对基于Bi1.5Zn1.0Nb1.5O7栅绝缘层的ZnO基TFT性能的影响

在不同基片温度(RT、300、400、500和600℃)下,采用射频磁控溅射法制备了ZnO薄膜和BZN薄膜.研究表明,所制备的BZN薄膜拥有非晶态结构,ZnO薄膜具有c轴择优取向,在基片温度为500℃时,获得低的漏电流(10-7 A/cm2),比RT时的漏电流(10-4 A/cm2)低三个数量级.将所制备的ZnO薄膜和BZN薄膜分别作为ZnO-TFT的有源层和栅绝缘层,研究表明,在基片温度为500℃时,提高了器件性能,所取得的亚阈值摆幅(470 mV/dec.)是RT时的亚阈值摆幅(1 271 mV/dec.)的三分之一;界面态密度(3.21×1012 cm-2)是RT时的界面态密度(1.48×1013 cm-2)的五分之一.     

准分子激光诱导非晶硅晶化制备多晶硅薄膜晶体管

讨论了用准分子激光诱导非晶硅晶化法制备多晶硅薄膜晶体管的结构与工艺优化问题。用 Xe Cl准分子激光器对 PECVD法生长的非晶硅薄膜进行了诱导晶化处理 ,成功制备了多晶硅薄膜晶体管 ,获得最大场效应迁移率为 1 4.5cm2 /V· s,亚阈值斜率为 1 .9V/dec,开关电流比为 1 .0× 1 0 6的器件性能。     

浸渍提拉法制备有机介质层铝铟锌氧薄膜晶体管

利用溶液法的浸渍提拉工艺制备了以有机聚甲基丙烯酸甲酯(PMMA)为介质层、非晶铝铟锌氧化物(a-AIZO)为沟道层的顶栅共面结构薄膜晶体管(TFT),研究了沟道层退火温度对TFT性能的影响机理。结果表明:较低退火温度(如300和350℃)下处理的沟道层中存在未彻底分解的金属氢氧化物,其以缺陷态形式存在于TFT沟道层内或沟道层/介质层界面处,对导电沟道中电子进行捕获或散射,劣化TFT的迁移率、电流开关比以及亚阈值摆幅。综合来看,退火温度高于400℃下制备的a-AIZO适用于TFT器件的沟道层,相应的器件呈现出较高的迁移率(大于20cm2/(V·s))、较低的亚阈值摆幅(小于0.5V/decade)以及高于104的电流开关比。     

MILC超薄沟道多晶硅薄膜晶体管

金属诱导横向结晶技术制备的多晶硅薄膜具有晶粒尺寸大且不随薄膜厚度而减小的特点,本文根据这一特点提出利用超薄沟道结构提高薄膜晶体管性能.采用超薄结构后,成功地将金属诱导结晶薄膜晶体管的漏电降到10-13A/μm以下;开关比提高了近100倍达到3×107以上;场效应迁移率从普通结构晶体管的80cm2/Vs(NMOS)与51cm2/Vs(PMOS)分别提高到110cm2/Vs与68cm2/Vs;阈值及亚阈摆幅也有很大改善.文中还将金属诱导结晶与传统固相结晶所得薄膜晶体管的性能进行了比较,并对这些结果进行了讨论.     

面向有机薄膜晶体管的紫外/红外光退火的溶液法氧化锆薄膜性能研究

首先引入新型油酸配位剂,解决已有溶液法成膜较差的问题,接着引入紫外/红外双光源退火工艺,制备了氧化锆薄膜。与传统的热退火工艺相比,双光源退火能够在较低温度下实现锆盐的分解、还原、氧化,形成高质量氧化锆薄膜。采用紫外分光光度计、原子力显微镜和X射线光电子能谱仪等对制备的氧化锆薄膜进行了表征对比,进而分析了成膜的物理机理。结果表明:所用方法成功实现了低温条件下(<120℃)高质量氧化锆薄膜的制备,薄膜的光学带隙约为5.66 e V,相对介电常数约为22.6,漏电流密度小于10-9 A/cm2@4 MV/cm,表面粗糙度为0.28 nm。最后,基于该氧化锆薄膜绝缘层制备出了低驱动电压的稠合噻吩-吡咯并吡咯二酮聚合物薄膜晶体管,其迁移率为0.50 cm2/(V·s),阈值电压为-0.47 V,电流开关比3.6×107,亚阈值摆幅为0.16 V/dec。     

Influence of substrate temperature on the performance of zinc oxide thin film transistor

Top-contact thin film transistors（TFTs） using radio frequency（RP） magnetron sputtering zinc oxide （ZnO） and silicon dioxide（SiO₂） films as the active channel layer and gate insulator layer,respectively,were fabricated.The performances of ZnO TFTs with different ZnO film deposition temperatures（room temperature, 100℃and 200℃） were investigated.Compared with the transistor with room-temperature deposited ZnO films, the mobility of the device fabricated at 200℃is improved by 94%and the threshold voltage shift is reduced from 18 to 3 V（after 1 h positive gate voltage stress）.Experimental results indicate that substrate temperature plays an important role in enhancing the field effect mobility,sharping the subthreshold swing and improving the bias stability of the devices.Atomic force microscopy was used to investigate the ZnO film properties.The reasons for the device performance improvement are discussed.     

ZnO Thin Film, Device, and Circuit Fabrication using Low-Temperature PECVD Processes

We report undoped ZnO films deposited at low temperature (200°C) using plasma-enhanced chemical vapor deposition (PECVD). ZnO thin-film transistors (TFTs) fabricated using ZnO and Al₂O₃ deposited in situ by PECVD with moderate gate leakage show a field-effect mobility of 10 cm²/V s, threshold voltage of 7.5 V, subthreshold slope <1 V/dec, and current on/off ratios >10⁴. Inverter circuits fabricated using these ZnO TFTs show peak gain magnitude (dV _out/dV _in) ~5. These devices appear to be strongly limited by interface states and reducing the gate leakage results in TFTs with lower mobility. For example, ZnO TFTs fabricated with low-leakage Al₂O₃ have mobility near 0.05 cm²/V s, and five-stage ring-oscillator integrated circuits fabricated using these TFTs have a 1.2 kHz oscillation frequency at 60 V, likely limited by interface states.     

Gate Capacitance‐Dependent Field‐Effect Mobility in Solution‐Processed Oxide Semiconductor Thin‐Film Transistors

Solution‐processed oxide semiconductors (OSs) used as channel layer have been presented as a solution to the demand for flexible, cheap, and transparent thin‐film transistors (TFTs). In order to produce high‐performance and long‐sustainable portable devices with the solution‐processed OS TFTs, the low‐operational voltage driving current is a key issue. Experimentally, increasing the gate‐insulator capacitances by high‐k dielectrics in the OS TFTs has significantly improved the field‐effect mobility of the OS TFTs. But, methodical examinations of how the field‐effect mobility depends on gate capacitance have not been presented yet. Here, a systematic analysis of the field‐effect mobility on the gate capacitances in the solution‐processed OS TFTs is presented, where the multiple‐trapping‐and‐release and hopping percolation mechanism are used to describe the electrical conductivity of the nanocrystalline and amorphous OSs, respectively. An intuitive single‐piece expression showing how the field‐effect mobility depends on gate capacitance is developed based on the aforementioned mechanisms. The field‐effect mobility, depending on the gate capacitances, of the fabricated ZnO and ZnSnO TFTs clearly follows the theoretical prediction. In addition, the way in which the gate insulator properties (e.g., gate capacitance or dielectric constant) affect the field‐effect mobility maximum in the nanocrystalline ZnO and amorphous ZnSnO TFTs are investigated.     

磁控溅射法制备高性能ZnO薄膜晶体管

研究了磁控溅射法制备的ZnO薄膜晶体管(TFT)。以NH3处理的热生长SiO2作为绝缘层,控制好Ar-O2比等条件溅射合适厚度的ZnO作为器件的有源层。实验表明,与普通条件下热生长的SiO2绝缘层硅片相比,NH3处理的高性能SiO2绝缘层Si片器件的载流子迁移率至少要高1个数量级以上;溅射条件在Ar-O2比25∶1情况下制作的器件性能最好;ZnO薄膜厚度也对ZnO-TFT性能有很大的影响。实验中,采用了4种膜厚,测试表明,其中25nm厚的ZnO薄膜迁移率最大。     

Channel Protection Layer Effect on the Performance of Oxide TFTs

We have investigated the channel protection layer (PL) effect on the performance of an oxide thin film transistor (TFT) with a staggered top gate ZnO TFT and Al‐doped zinc tin oxide (AZTO) TFT. Deposition of an ultra‐thin PL on oxide semiconductor films enables TFTs to behave well by protecting the channel from a photo‐resist (PR) stripper which removes the depleted surface of the active layer and increases the carrier amount in the channel. In addition, adopting a PL prevents channel contamination from the organic PR and results in high mobility and small subthreshold swings. The PL process plays a critical role in the performance of oxide TFTs. When a plasma process is introduced on the surface of an active layer during the PL process, and as the plasma power is increased, the TFT characteristics degrade, resulting in lower mobility and higher threshold voltage. Therefore, it is very important to form an interface using a minimized plasma process.     

Low-Temperature Pulsed-PECVD ZnO Thin-Film Transistors

We report high-quality ZnO thin films deposited at low temperature (200°C) by pulsed plasma-enhanced chemical vapor deposition (pulsed PECVD). Process byproducts are purged by weak oxidants N₂O or CO₂ to minimize parasitic CVD deposition, resulting in high-refractive-index thin films. Pulsed-PECVD-deposited ZnO thin-film transistors were fabricated on plasma-enhanced atomic layer deposition (PEALD) Al₂O₃ dielectric and have a field-effect mobility of 15 cm²/V s, subthreshold slope of 370 mV/dec, threshold voltage of 6.6 V, and current on/off ratio of 10⁸. Thin-film transistors (TFTs) on thermal SiO₂ dielectric have a field-effect mobility of 7.5 cm²/V s and threshold voltage of 14 V. For these devices, performance may be limited by the interface between the ZnO and the dielectric.     

Active Layer Thickness Effects on the On-State Current and Pulse Measurement at Room Temperature on Deposited Zinc Oxide Thin-Film Transistors

This study reports on the fabrication of thin-film transistors (TFTs) with transparent zinc oxide (ZnO) semiconductors serving as the active channel and silicon dioxide (SiO₂) serving as the gate insulator. The ZnO films were deposited by radiofrequency magnetron sputtering at room temperature. Moreover, the effects of channel thickness on the structural and pulse current?Cvoltage characteristics of ZnO TFTs using a bottom gate configuration were investigated. As the channel thickness increased, the crystalline quality and the channel conductance were enhanced. The electrical characteristics of TFTs exhibited field-effect mobilities of 8.36?cm²/Vs to 16.40?cm²/Vs and on-to-off current ratios of 10⁸ to 10⁷ for ZnO layer thickness of 45?nm and 70?nm, respectively. The threshold voltage was in the range of 10?V to 31?V for ZnO layer thicknesses from 35?nm to 70?nm, respectively. The low deposition and processing temperatures make these TFTs suitable for fabrication on flexible substrates.     

Phosphorus Doping Effect in a Zinc Oxide Channel Layer to Improve the Performance of Oxide Thin-Film Transistors

In this study, we fabricated phosphorus-doped zinc oxide-based thin-film transistors (TFTs) using direct current (DC) magnetron sputtering at a relatively low temperature of 100°C. To improve the TFT device performance, including field-effect mobility and bias stress stability, phosphorus dopants were employed to suppress the generation of intrinsic defects in the ZnO-based semiconductor. The positive and negative bias stress stabilities were dramatically improved by introducing the phosphorus dopants, which could prevent turn-on voltage (V _ON) shift in the TFTs caused by charge trapping within the active channel layer. The study showed that phosphorus doping in ZnO was an effective method to control the electrical properties of the active channel layers and improve the bias stress stability of oxide-based TFTs.     

基于高迁移率微晶硅的薄膜晶体管

近年来,微晶硅(μc-Si:H)被认为是一种制作 TFT 的有前景的材料.采用PECVD法,在低于200℃时制作了微晶硅TFTs,其制作条件类似于非晶态 TFTs.微晶硅 TFTs 器件的迁移率超过了 30 cm2/Vs,而阈值电压是 2.5 V.在长沟道器件(50～200 μm)中观测到了这种高迁移率.但对于短沟道器件(2 μm),迁移率就降低到了7 cm2/Vs.此外,该 TFTs 的阈值电压随着沟道长度的减少而增大.文章采用了一种简单模型解释了迁移率、阈值电压随着沟道长度的缩短而分别减少、增加的原因在于源漏接触电阻的影响.     

Proton-induced displacement damage in ZnO thin film transistors: Impact of damage location

We have investigated the displacement damage (DD) effect on the electrical characteristics of ZnO thin film transistors (TFTs) based on its location of origin in the device structure. The area subjected to the maximum proton dose induces a maximum DD effect in that particular location. ZnO TFTs with two different passivation layer thicknesses were prepared to obtain maximum proton dose distribution in either the ZnO channel layer or ZnO/SiO₂ interface. The devices were irradiated by a proton beam with an energy 200 keV and 1 × 10¹⁴ protons/cm² fluence. Transport of Ions in Matter (TRIM) simulation, followed by calculation of depth distribution of the nonionizing energy loss (NIEL), illustrated different proton dose distribution profiles and NIEL profiles along the depth of the device for these two types of samples. The sample with the maximum proton dose peaks at the ZnO/SiO₂ interface exhibited a significant degradation in device electrical characteristics as compared to the negligible degradation of the sample when the maximum proton dose was absorbed in the ZnO layer. Therefore, the investigation into the radiation hardness of proton-irradiated ZnO TFTs is non-trivial since the displacement damage induces drastic changes on the device characteristics based on the damage location.