具有快速瞬态响应和低静态电流的CMOS低漏失稳压器设计

 设计了一种具有快速瞬态响应能力的低漏失稳压器,利用提出的一种瞬态响应加速(Transient Response Enhancement,TRE)电路,有效地提高了稳压器的瞬态响应速度,而且瞬态响应速度的提高并不增加静态电流.设计的LDO电路采用0.5μm标准CMOS工艺投片验证,芯片面积为0.49mm².该LDO空载下的静态电流仅23μA,最大带载200mA.在1μF输出电容、200mA/100ns负载阶跃变化时的最大瞬态输出电压变化量小于3.5％.     

一种快速瞬态响应的低压差线性稳压器设计

设计了一种应用于片外大电容场景下的具有快速瞬态响应特性的LDO。电路通过采用负载电流采样负反馈的结构构成了一个高带宽的电压缓冲器。该LDO使用具有电容倍增功能的共栅共源补偿结构,在外挂1μF负载电容的条件下,仅需500 fF的片上补偿电容即可保证在全负载范围内的稳定性。此外,通过使用自适应偏置技术,在减小轻载功耗的同时进一步提升了瞬态响应速度。电路采用0.18μm CMOS工艺进行设计与仿真验证。仿真结果表明,在LDO的输入电压为1.2 V、输出电压为1 V时,当负载电流以0.1μs的速度在150 mA和100μA之间切换时,最大电压变化仅为10.7 mV,输出电压恢复时间小于0.7μs。     

一种低压快速瞬态响应的片上LDO

提出了一种低输入电压的快速瞬态响应片上低压差线性稳压器(LDO)。采用基于反相器的轨-轨输入运放作为误差放大器(EA)的输入级。EA后级采用大抽灌电流能力的STCB结构。LDO加入了高通耦合结构,实现了低输入电压和全负载范围下的快速瞬态响应。该LDO无需外加偏置网络就能实现自启动。在Dongbu 0.5 μm CMOS工艺下,LDO的输入电压为2.2~2.7 V,输出电压为2 V。仿真结果表明,在负载电容为100 pF、压差为200 mV的条件下,该LDO可稳定输出0.1~100 mA的负载电流,负载在0.5 μs范围内切换时的电压尖峰在310 mV以内。     

一种提高大电流LDO瞬态响应的技术

提出了一种有效提升大电流输出的低压差线性稳压器(LDO)瞬态响应的技术.该技术采用新颖的电压双反馈环路,实现了带宽延展;采用摆率增强电路提高了功率管栅极节点的压摆率;采用输出电流泄放电路,加快了负载电流突降后的恢复.基于0.6μm BiCMOS工艺完成设计、流片.结果表明:在1 mA～5 A,斜率为1.25 A/μs的负载突变情况下,输出电压下冲仅30.8 mV,过冲仅20.7 mV.     

一种超快速响应的片上线性稳压器

设计了一种片上超高速低压差(LDO,low dropout)线性稳压器。在仅利用100pF输出电容情况下,采用一种新颖的快速响应回路,使LDO可以响应20ns内负载电流由空载到满载的瞬态变化,大大提高了系统的瞬态响应性能。快速响应回路同时具有补偿作用,保证LDO的稳定性。芯片设计基于SMIC公司的0.35μm CMOS工艺信号模型。测试结果表明,LDO在工作模式下的静态电流约为120μA,在等待模式下的静态电流约为9μA,对上升、下降时间均小于60ns的脉冲信号具有良好的瞬态响应。     

一种快速响应无片外电容低压差线性稳压器

为了改善负载跳变对低压差线性稳压器(LDO)的影响,该文提出一种用于无片外电容LDO(CL-LDO)的新型快速响应技术。通过增加一条额外的快速通路,实现CL-LDO的快速瞬态响应,并且能够减小LDO输出过冲和下冲的幅度。该文电路基于0.18 μm CMOS工艺设计实现,面积为0.00529 mm²。流片测试结果表明,当输入电压范围为1.5～2.5 V时,输出电压为1.194 V;当负载电流以 1 μs的上升时间和下降时间在 100 μA～10 mA之间变化时,CL-LDO的过冲恢复时间为489.537 ns,下冲恢复为960.918 ns;相比未采用该技术的传统CL-LDO,响应速度能够提高7.41倍,输出过冲和下冲的电压幅值能够分别下降35.3%和78.1%。     

一种快速瞬态响应无片外电容LDO

针对无片外电容LDO,在误差放大器与功率管之间添加缓冲器,采用频率补偿的方法,提高了环路稳定性。通过检测负载瞬态变化引起的误差放大器输出电压变化,增加对功率管栅极电容的充放电电流,提升了系统的快速瞬态响应能力。基于TSMC 0.18 μm标准CMOS工艺,设计了一种输入电压范围为1.92~3.60 V、输出电压为1.8 V的LDO。结果表明,负载在1 μs内从0变化到100 mA时,输出最大下冲电压为37.2 mV,响应时间为1.12 μs;负载在1 μs内从100 mA变化到0时,输出最大过冲电压为40.1 mV,响应时间为1.1 μs。     

低压差双电容补偿高瞬态响应线性稳压器设计

为适应现代电子产品对电源性能的较高要求,基于教学中应用的Spectre平台,采用源随器补偿方法设计了一种无片外电容的LDO稳压器。小补偿电容和大驱动能力的两级运放误差放大器,加快了电路的响应速度,提高了瞬态响应性能,并降低了输出电压波纹,从而增强了系统的稳定性。测试结果表明,电路的静态电流为30μA,工作输出电压为1.2 V,最大输出电流为100 mA,Vdrop为200 mV,相位裕度大于60°,在相应条件下的线性调整率SL、负载调整率So分别为0.05%(V/V),0.23%(V/A)。源随器补偿方法既可保证电路稳定工作,又能有效降低输出波纹和加快瞬态响应速度,已达到系统预期设计指标。     

一种具有快速瞬态响应的片上LDO

提出了一种全负载范围内具有较高增益和带宽的片上快速瞬态响应的低压差线性稳压器(LDO)。误差放大器采用带瞬态增强的高跨导、高摆率、高输出阻抗STCB结构。推挽式微分器兼具频率补偿和快速瞬态响应功能,在大幅提升LDO瞬态响应速度的同时,节省了补偿电容面积。增加了自适应偏置,缓解了重载下增益和带宽下降的问题。该LDO基于0.5 μm标准CMOS工艺进行设计,芯片面积为0.077 mm²。结果表明,在负载电容为100 pF、压差为100 mV的条件下,该LDO可稳定输出50 μA ~100 mA的负载电流。负载在0.5 μs内以最大电流范围切换时,输出电压变化峰值在300 mV以内。     

一种快速瞬态响应LDO的设计与实现

设计了一种快速瞬态响应LDO。采用缓冲级结构的增强电路,使功率器件在负载瞬态变化时,栅极能够及时响应,从而避免了较大的电压上冲与下冲。加入缓冲级电路以后,系统的稳定性变差,采用密勒补偿和前馈补偿对其进行频率补偿,增加系统的相位裕度,使系统稳定。采用CSMC 0.5 μm工艺,利用Cadence工具完成了整体电路的设计、前仿真、物理版图设计和后仿真,并进行了流片。测试结果表明,设计的LDO输出电压为2.5 V,负载电流在10 mA和300 mA之间变化时,电压最大变化48 mV,响应时间为12.4 μs。     

A 3 A sink/source current fast transient response low-dropout Gm driven linear regulator

A 3 A sink/source G_m-driven CMOS low-dropout regulator(LDO),specially designed for low input voltage and low cost,is presented by utilizing the structure of a current mirror G_m(transconductance)driving technique,which provides high stability as well as a fast load transient response.The proposed LDO was fabricated by a 0.5μm standard CMOS process,and the die size is as small as 1.0 mm~2.The proposed LDO dissipates 220μA of quiescent current in no-load conditions and is able to deliver up to 3 A of load current.The measured results show that the output voltage can be resumed within 2μs with a less than 1mV overshoot and undershoot in the output current step from-1.8 to 1.8 A with a 0.1μs rising and falling time at three 10μF ceramic capacitors.     

A 200 mA CMOS low-dropout regulator with double frequency compensation techniques for SoC applications

This paper presents a 200mA low-dropout (LDO) linear regulator using two modified techniques for frequency compensation. One technique is that the error amplifier using common source stage with variable load, which is controlled by output current, is served as the second stage for stable frequency responses. Another technique is the LDO uses pole-zero tracking compensation technique at error amplifier to achieve good frequency response. The proposed circuit was fabricated and tested in HJTC 0.18μm CMOS technology. The designed LDO linear regulator works under the input voltage of 2.8V-5V and provides up to 200mA load current for an output voltage of 1.8V. The total error of the output voltage due to line and load variation is less than 0.015%. The LDO die area is 630*550μm² and the quiescent current is 130μA.     

A 200 mA CMOS low-dropout regulator with double frequency compensation techniques for SoC applications

This paper presents a 200 mA low-dropout(LDO) linear regulator using two modified techniques for frequency compensation.One technique is that the error amplifier uses a common source stage with variable load, which is controlled by the output current,is served as the second stage for a stable frequency response.The other technique is that the LDO uses a pole-zero tracking compensation technique at the error amplifier to achieve a good frequency response.The proposed circuit was fabricated and tested in HJTC 0.18μm CMOS technology. The designed LDO linear regulator works under the input voltage of 2.8-5 V and provides up to 200 mA load current for an output voltage of 1.8 V.The total error of the output voltage due to line and load variation is less than 0.015%.The LDO die area is 630×550μm~2 and the quiescent current is 130μA.     

A CMOS fast transient response low-dropout regulator with a compact NMOS output driver

We present a CMOS low-dropout voltage regulator with a high-speed NMOS compact driver suitable for supplying on-chip voltages for the digital core of a SoC. The LDO is part of a power management controller hardblock integrated within a microcontroller. The die area of the circuit implemented in a 90 nm CMOS process is only 0.054 mm². Experimental results show that the developed LDO can supply up to 15 mA and it presents a very fast transient response, with a settling time of approximately 30 ns and a voltage drop of 200 mV when the load current changes from 100 nA to 9 mA.     

A hybrid NMOS/PMOS capacitor-less low-dropout regulator with fast transient response for SoC applications

In this paper, a new architecture of a fully integrated low-dropout voltage regulator (LDO) is presented. It is composed of hybrid architecture of NMOS/PMOS power transistors to relax stability requirements and enhance the transient response of the system. The LDO is capable of producing a stable output voltage of 1.1 V from 1.3 V single supply with recovery settling time about 680 nsec. It can supply current from 10 µA to 100 mA consuming quiescent current of 20.5 µA and 95 µA, respectively. It supports load capacitance from 0 to 50 pF with phase margin that increases from 43° at low load (10 µA) to 74° at high load (100 mA) and power supply rejection ratio (PSRR) less than −20 dB up to 100 kHz. The proposed LDO is designed in 130 nm CMOS technology and occupies an area of 0.11 mm². Post layout simulations show better performance compared with other reported techniques.     

应用动态偏置和双环反馈技术的CMOS快速瞬态响应低压差线性稳压器设计

This paper presents a low-dropout regulator （LDO） for portable applications with dual-loop feedback and a dynamic bias circuit. The dual-loop feedback structure is adopted to reduce the output voltage spike and the response time of the LDO. The dynamic bias circuit enhances the slew rate at the gate of the power transistor. In addition, an adaptive miller compensation technique is employed, from which a single pole system is realized and over a 59~ phase margin is achieved under the full range of the load current. The proposed LDO has been implemented in a 0.6μm CMOS process. From the experimental results, the regulator can operate with a minimum dropout voltage of 200 mV at a maximum 300 mA load and IQ of 113μA. The line regulation and load regulation are improved to 0. l mV/V and 3.4 μV/mA due to the sufficient loop gain provided by the dual feedback loops. Under a full range load current step, the voltage spikes and the recovery time of the proposed LDO is reduced to 97 mV and 0.142 μs respectively.     

A high-PSR transient-enhanced output-capacitorless CMOS low-dropout regulator for SoC applications

A transient-enhanced output-capacitorless CMOS low-dropout voltage regulator (LDO) with high power supply rejection (PSR) is introduced for system-on-chip applications. In order to reduce external pin count and device area and be amenable to full integration, the large external capacitor used in the classical LDO design is eliminated and replaced with a much smaller 5.7?pF on-chip capacitor. High-gain folded-cascode stage, wideband common source stage, voltage subtractor stage and transient-enhanced circuit are designed altogether to realise circuit compensation and achieve good frequency and transient performances. A current-sensing and transient-enhanced circuit is utilised to reduce transient voltage dips effectively and efficiently drive different kinds of load capacitances. The active chip area of the proposed regulator is only 200?×?280?µm². The simulation results under mixed-signal 0.18?µm 1P6M process show that this novel LDO's output voltage can recover within 1.7?µs (rising) and 2.41?µs (falling) under full load-current changes. The input voltage is ranged from 2 to 5?V for a load current 50?mA and an output voltage of 1.8?V. This novel LDO has wide unity-gain frequency stability and is stable for estimated equivalent parasitic capacitive loads from 0 to 100?pF. Moreover, it can achieve a PSR of ?78.5 and ?73?dB at 1 and 10?kHz, respectively.     

一种用于总线终端的3A源-汇式线性稳压器的设计与实现

针对总线终端稳压器的设计要求,提出一种具有3A源-汇（source and sink）电流能力的快速响应线性稳压器。采用NMOS调整管结构和负载电流反馈技术,提高了系统的电流能力和响应速度。使用自适应零点补偿实现了全负载范围内source和sink环路的稳定性。此外,采用跨导匹配技术使得输出级的直通电流降低到3μA以下。该电路采用0.6-μm 5V/30V工艺投片验证,面积为1mm2。在20μF输出电容、?2A/1μs负载阶跃变化时的最大瞬态输出电压变化量小于3.5％,在?3A的负载范围内,输出电压变化小于?15mV。     

基于电流环路控制方法的快速响应LDO

LDO电路的瞬态响应能力是评价LDO性能的一个重要指标。本文借鉴电荷泵式锁相环的环路控制方法,提出了一种基于电流控制环路的LDO结构,将典型LDO电路中的电压比较改为电流比较,利用跨导放大器和环路滤波器产生功率管的控制栅压,使得环路具有优化的阻尼因子ζ和固有频率ωn,有效提高了LDO环路的瞬态响应能力,并且输出电压可以低至1V以下,且不受基准电压的限制。基于0.13μm CMOS工艺的实现结果表明,在使用1μF去耦电容,LDO输出1.0V的情况下,负载100μA→100mA瞬态变化时,输出超调5.11mV,稳定输出的压降4.25mV,稳定时间8.2μs,而负载100mA→100μA时,输出超调6.21mV,稳定输出的压降4.25mV,稳定时间23.3μs。结果表明,该电路各项性能指标均有明显的提高,FOM指数达到0.0097。     

A fast transient response low dropout regulator with current control methodology

A transient performance optimized CCL-LDO regulator is proposed.In the CCL-LDO,the control method of the charge pump phase-locked loop is adopted.A current control loop has the feedback signal and reference current to be compared,and then a loop filter generates the gate voltage of the power MOSFET by integrating the error current.The CCL-LDO has the optimized damping coefficient and natural resonant frequency, while its output voltage can be sub-l-V and is not restricted by the reference voltage.With a 1μF decoupling capacitor,the experimental results based on a 0.13μm CMOS process show that the output voltage is 1.0 V;when the workload changes from 100μA to 100 mA transiently,the stable dropout is 4.25 mV,the settling time is 8.2μs and the undershoot is 5.11 mV;when the workload changes from 100 mA to 100μA transiently,the stable dropout is 4.25 mV,the settling time is 23.3μs and the overshoot is 6.21 mV.The PSRR value is more than -95 dB.Most of the attributes of the CCL-LDO are improved rapidly with a FOM value of 0.0097.