Correlation of stress-induced leakage current in thin oxides withtrap generation inside the oxides

Increases in pre-tunneling leakage currents in thin oxides after the oxides are subjected to high voltage stresses are correlated with the number of traps generated inside of the oxides by the high-voltage stresses. The densities of the traps are calculated using the tunneling front model and analyzing the transient currents that flowed through the oxide after removal of the stress voltage pulses. It is found that the trap distributions are relatively uniform throughout the small portion of the oxide sampled by the transient currents. The trap densities increase as the cube root of the fluence of electrons that passes through the oxide during the stress, independent of the stress polarity. The voltage dependence of the low-level pretunneling current is dependent on the sequence in which the stress voltage polarities and the low-level current measurement polarities are applied. The portion of the low-level pre-tunneling current that is not dependent on the polarity sequence is best fitted by a voltage dependence consistent with Schottky emission     

Thickness dependence of stress-induced leakage currents in siliconoxide

The thickness dependence of high-voltage stress-induced leakage currents (SILC's) has been measured in oxides with thicknesses between 5 and 11 nm. The SILC's were shown to be composed of two components: a transient component and a DC component. Both components were due to trap-assisted tunneling processes. The transient component was caused by the tunnel charging and discharging of the stress-generated traps near the two interfaces. The DC component was caused by trap-assisted tunneling completely through the oxide. The thickness, voltage, and trap density dependences of both of these components were measured. The SILC's will affect data retention in electrically erasable programmable read-only memories (EEPROM's) and the DC component was used to estimate to fundamental limitations on oxide thicknesses     

Characterizing wearout, breakdown and trap generation in thin silicon oxide

A model describing how wearout leads to breakdown in thin silicon oxides has been developed. During wearout defects or traps are generated inside the oxide and at the oxide interfaces. The signature of the trap generation is the permanent change in the transient current, in response to a voltage pulse, from an exponential decay to a 1/time decay. In oxides thinner than approximately 20 nm the dominant trap generation mechanism appears to be determined by the high fields across the oxides and not electron flow through the oxides. Locally higher current densities, flowing through the traps generated during wearout, lead to local breakdown. This model is critically dependent on the measurement of the properties of the traps generated inside the oxides during the wearout phase. The techniques for measurement of these traps and some of their properties have been described. The ability of this model to describe oxide charging, low-level leakages, transient currents, the role of asperities, polarity dependences, and the fluence, time, thickness, voltage and temperature dependences of oxide breakdown distributions has been discussed.     

A model relating wearout to breakdown in thin oxides

A model has been developed relating wearout to breakdown in thin oxides. Wearout has been described in terms of trap generation inside of the oxide during high voltage stressing prior to breakdown. Breakdown occurred locally when the local density of traps exceeded a critical value and the product of the electric field and the higher leakage currents through the traps exceeded a critical energy density. The measurement techniques needed for determining the density of high-voltage stress generated traps have been described along with the method for coupling the wearout measurements to breakdown distributions. The average trap density immediately prior to breakdown was measured to be of the order of low-10¹⁹/cm³ in 10 nm thick oxides fabricated on p-type substrates stressed with negative gate voltages. The model has been used to describe several effects observed during measurements of time-dependent-dielectric-breakdown distributions. The area dependence of breakdown distributions, the differences in the breakdown distributions during constant current and constant voltage stressing, and the multi-modal distributions often observed were simulated using the model. The model contained the provision for incorporation of weak spots in the oxide     

Properties of high-voltage stress generated traps in thin siliconoxide

It has previously been shown that trap generation inside thin oxides during high voltage stressing can be coupled to time-dependent-dielectric-breakdown distributions through the statistics linking wearout to breakdown. Since the stress-generated traps play a crucial role in the wearout/breakdown process, it is important to understand the properties of these traps. The properties of the traps in oxides with thicknesses between 2.5 nm and 22 nm have been studied, with emphasis on oxides in the 8.5-nm to 13-nm thickness range. The Coulombic scattering cross section of the traps responsible for the reduction in the tunneling current, an estimate of the spatial and energy distribution of the traps, and the charging/discharging properties of the traps have been measured. It will be shown that the measured properties of the high-voltage, stress-generated traps can be adequately described by the tunneling of electrons into and out of traps     

低电场应力下闪速存储器的退化特性

基于负栅源边擦除的闪速存储器存储单元,研究了形成应力诱生漏电流的三种导电机制,同时采用新的实验方法对引起瞬态和稳态电流的电压漂移量进行了测量.并利用电容耦合效应模型对闪速存储器存储单元的可靠性进行了研究,结果表明,在低电场应力下,其可靠性问题主要由载流子在氧化层里充放电引起.     

Memory traps in MNOS diodes measured by thermally stimulated current

Thermally stimulated current was measured to determine trap distribution and charging and discharging mechanisms in a Metal-Nitride-Oxide-Semiconductor (MNOS) diode with 16 Å oxide thickness. By changing gate voltage, heating rate and the initial flat-band voltage, the memory traps near the nitride-oxide interface were separated from the others. The general formula was derived for the thermally stimulated current in an MNOS diode and was applied to obtain the trap distribution as well as effective emission time constants. The results indicate that the memory traps are distributed 50 Å deep into the nitride film from the nitride-oxide interface. The energy level lies at around 2·55 eV from the bottom of the nitride conduction band. The charging and discharging mechanism is the cascade connection of tunneling and thermal excitation or trapping. The obtained trap distribution and the charge transfer mechanism are successful for interpreting the write-in and retention characteristics.     

关态应力下P-MOSFETs的退化

研究了沟长从0.525μm到1.025μm 9nm厚的P-MOSFETs在关态应力(Vgs＝0,Vds＜0)下的热载流子效应．讨论了开态和关态应力．结果发现由于在漏端附近存在电荷注入,关态漏电流在较高的应力后会减小．但是低场应力后关态漏电流会增加,这是由于新生界面态的作用．结果还发现开态饱和电流和阈值电压在关态应力后变化很明显,这是由于栅漏交叠处的电荷注入和应力产生的界面态的影响．Idsat的退化可以用函数栅电流（Iｇ）乘以注入的栅氧化层电荷数（Qinj）的幂函数表达．最后给出了基于Idsat退化的寿命预测模型．     

Transient Charging and Discharging Behaviors of Border Traps in the Dual-Layer HfO2/SiO2 High- κ Gate Stack Observed by Using Low-Frequency Charge Pumping Method

Transient charging and discharging of border traps in the dual-layer HfO₂/SiO₂ high-kappa gate stack have been extensively studied by the low-frequency charge pumping method with various input pulse waveforms. It has been demonstrated that the exchange of charge carriers mainly occurs through the direct tunneling between the Si conduction band states and border traps in the HfO₂ high-kappa dielectric within the transient charging and discharging stages in one pulse cycle. Moreover, the transient charging and discharging behaviors could be observed in the time scale of 10^-8- 10^-4 s and well described by the charge trapping/detrapping model with dispersive capture/emission time constants used in static positive bias stress. Finally, the frequency and voltage dependencies of the border trap area density could also be transformed into the spatial and energetic distribution of border traps as a smoothed 3-D mesh profiling     

Hole trap generation in the gate oxide due to plasma-inducedcharging

The paper presents results of hole trapping studies in-thin gate oxide of plasma damaged MOS transistors. Process-induced damage was investigated with antenna test structures to enhance the effect of plasma charging. In addition to neutral electron traps and passivated interface damage, which are commonly observed plasma charging latent damage, we observed and identified hole traps, generated by plasma stress. The amount of hole traps increases with increasing antenna ratio, indicating that the mechanism of hole trap generation is based on electrical stress and current flow, forced through the oxide during plasma etching. The density of hole traps in the most damaged devices was found to be larger than that in reference, undamaged devices by about 100%     

Characterization of hot-hole injection induced SILC and relateddisturbs in flash memories

In this paper, we have proposed a new method for the study of disturb failure mechanisms caused by stress induced leakage current (SILC) in source-side erased flash memories. This method is able to directly separate the individual components of SILC due to either carrier charging/discharging in the oxide or the positive charge/trap assisted electron tunneling into the floating gate. In addition, the present method is very sensitive with capability of measuring ultralow current (<10^-19 A). Results show that, at low oxide field, the disturb is mainly contributed by the so-called charging/discharging of carriers into/from the oxide due to the capacitance coupling effect. While at high oxide field, the positive charge/trap assisted electron tunneling induced floating-gate charge variation is the major cause of disturb failure     

SILC dynamics in MOS structures subject to periodic stress

This work investigates stress-induced leakage current (SILC) in thin-oxide MOS capacitors subject to (quasiperiodic) ac voltage stress, under the condition of fixed charge fluence through the oxide. It shows that both trap creation and spontaneous trap annealing play a significant role when the duration of, and the time between, high-voltage pulses are comparable with characteristic times of trap dynamics. A phenomenological model is introduced that is able to accurately represent the main physical phenomena due to pulsed voltage stress under conditions of interest for unconventional programming schemes for fast programming nonvolatile memories (NVMs) with acceptable oxide degradation.     

Numerical Simulation of Bottom Oxide Thickness Effect on Charge Retention in SONOS Flash Memory Cells

In this paper, bottom-oxide thickness (T_bo) and program/erase stress effects on charge retention in SONOS Flash memory cells with FN programming are investigated. Utilizing a numerical analysis based on a multiple electron-trapping model to solve the Shockley-Read-Hall rate equations in nitride, we simulate the electron-retention behavior in a SONOS cell with T_bo from 1.8 to 5.0 nm. In our model, the nitride traps have a continuous energy distribution. A series of Frenkel-Poole (FP) excitation of trapped electrons to the conduction band and electron recapture into nitride traps feature the transitions between the conduction band and trap states. Conduction band electron tunneling via oxide traps created by high-voltage stress and trapped electron direct tunneling through the bottom oxide are included to describe various charge leakage paths. We measure the nitride-charge leakage current directly in a large-area device for comparison. This paper reveals that the charge-retention loss in a high-voltage stressed cell, with a thicker bottom oxide (5 nm), exhibits two stages. The charge-leakage current is limited by oxide trap-assisted tunneling in the first stage and, then, follows a 1/t time dependence due to the FP emission in the second stage. The transition time from the first stage to the second stage is related to oxide trap-assisted tunneling time but is prolonged by a factor     

Investigation of the energy distribution of stress-induced oxide traps by numerical analysis of the TAT of HEs

This paper investigates by numerical modeling the results of substrate hot electron (SHE) injection experiments in virgin and stressed devices and the corresponding increase of the contribution of HEs to the gate current due to the stress-induced oxide traps. Experimental evidence of HE trap-assisted tunneling (HE TAT) is found after Fowler-Nordheim (FN) stress and SHE stress. An accurate physically based model developed to interpret the experimental results allowed us to study the energy distribution of generated oxide traps in the two different stress regimes. It is found that degradation in HE stress conditions and FN stress conditions cannot be explained by the same trap distribution. For a given stress-induced low field leakage current, a larger concentration of traps in the top part of the oxide band gap is needed to explain HE TAT after SHE stress than after FN stress. The range of trap energy where each technique is sensitive is also identified.     

Hole traps in silicon dioxides. Part I. Properties

As the downscaling of gate oxides continues, trap density in the oxide bulk will reduce, but positive charges formed near to the SiO/sub 2//Si interface become relatively important. For gate oxides used in industry, hole trapping is the most important process for positive charge formation. Apart from as-grown hole traps, we recently reported that new hole traps were generated by electrical stresses. Information on these hole traps, however, is still limited. In part I of this work, properties of both generated and as-grown hole traps are investigated. For the first time, it will be clearly shown that generated hole traps consist of two components; cyclic positive charges (CPC) and antineutralization positive charges (ANPC). The charging and discharging rates of CPC are similar, while the neutralization of ANPC is much more difficult than its charging. Differences between them are also observed in generation kinetics and dependence on measurement temperature. Efforts will be made to explain their differences in terms of energy levels and to link them with positive charges reported in earlier works. We will also show that as-grown traps, regardless their distance from the interface, are not responsible for either ANPC or CPC. This is to say that generated hole traps are not the same as as-grown traps and their differences will be highlighted. In part II, hole trap generation mechanisms will be investigated.     

Investigation of the threshold voltage turn-around effect in long-channel n-MOSFETs due to hot-carrier stress

In this paper, we have investigated the turn-around effect of the threshold voltage (V_th) shift in the case of an n-type long channel MOSFET during hot-carrier stress. This effect is explained by the interplay between interface states and oxide traps, i.e. by the partial compensation of the rapidly created oxide charges by the more slowly created interface states. Significant hole trapping is observed from the negative shift of the threshold voltage during the first seconds of stress. Afterwards, V_th has switched to the positive voltage direction due to the negative charging of interface traps after relatively long stress time. To analyze this phenomenon in detail, a refined extraction technique for the defect distribution from charge-pumping measurements has been employed. Additionally, the obtained results have been explained by our physics-based model of hot-carrier degradation which considers not only channel electrons but also secondary holes generated by impact ionization. In spite of the small hole contribution (compared to that of electrons) to the total defect creation, its impact on the threshold voltage shift is comparable with the electronic one. The reason behind this trend is that hole-induced traps are shifted towards the source, thereby more severely affecting the device behavior.     

Monitoring plasma-process induced damage in thin oxide

Plasma etching and resist ashing processes cause current to flow through the thin oxide and the resultant plasma-induced damage can be simulated and modeled as damage produced by constant current electrical stress. The oxide charging current produced by plasma processing increases with the `antenna' size of the device structure. Oxide charge measurement such as CV or threshold voltage is a more sensitive technique for characterizing plasma-processing induced damage than oxide breakdown. The oxide charging current is collected only through the aluminum surfaces not covered by the photoresist during plasma processes. Although forming gas anneal can passivate the traps generated during plasma etching, subsequent Fowler-Nordheim stressing causes more traps to be generated in these devices than in devices that have not been through plasma etching. Using the measured charging current, the breakdown voltage distribution of oxides after plasma processes can be predicted accurately. Oxide shorts density of a single large test capacitor is found to be higher than that in a multiple of separated small capacitors having the same total oxide area. This would lead to overly pessimistic oxide defect data unless care is taken     

Two types of neutral electron traps generated in the gate silicon dioxide

Electron trap generation in the gate oxide is a severe problem for the reliability of MOS devices, since it can cause stress-induced leakage current (SILC) and eventually lead to oxide breakdown. Although much effort has recently been made to understand the mechanism for the trap generation, the properties of the generated traps have received relatively less attention. The objective of this paper is to present unambiguous results, showing that two different types of neutral electron traps can be created by the same stress and to compare the properties of these two types of traps. Differences have been found in terms of their generation kinetics, trap filling, detrapping, and refilling after detrapping. The results also indicate that the energy levels of these two types of traps are different.     

Gate oxide leakage due to temperature accelerated degradation under plasma charging conditions

Plasma-induced gate charging and resulting damage to the gate oxide during fabrication of submicron devices becomes a serious yield and reliability concern, especially when oxide thickness and device dimensions shrink to the nanoscale region. In this paper experimental results from plasma damaged submicron MOS transistors, namely low-level gate leakage and degraded charge-to-breakdown characteristics, are analyzed with respect to conditions of electrical stress. It is demonstrated that wafer temperature is a crucial parameter for charging-induced oxide degradation due to plasma processing. Laboratory experiments simulating plasma charging showed that low-level oxide leakage is the result of oxide breakdown after electrical wear-out under low-level injection conditions. High field stress, performed at 150°C, confirmed that elevated temperature during plasma processing strongly accelerates oxide degradation and even at low-level stress leads to the effects observed in plasma damaged devices.     

Extrapolation of high-voltage stress measurements to low-voltageoperation for thin silicon-oxide films

Breakdown and wearout in MOS capacitors fabricated with 10 nm-thick silicon oxide films on p-type silicon are discussed. They have been stressed at high voltages. The high-voltage-stress-induced changes in the oxide properties are extrapolated to low operating voltages. The stress voltages ranged from -7.5 V to -14.5 V. The fluence during the stress was systematically varied front 2×10^-5 C/cm² to 6 C/cm² by varying the stress time at each voltage. The number of interface traps generated by the stress increased as the stress voltage and fluence increased. However, the interface trap generation rate decreased as the fluence increased. The trap generation rate at low operating voltages was very high, but because the current through the oxide was small, the total number of traps generated was low. The trap generation rate was proportional to the inverse square root of the fluence with a voltage dependence that decreased as the fluence increased. Extrapolation of the high-voltage-stress measurements to 5 V shows that easily detectable changes in the oxide properties would only occur after several years of 5 V operation. Extrapolation of charge-to-breakdown and time-to-breakdown data to 5 V operation indicates that breakdown would occur after hundreds of years of device operation