电流返回路径分解的信号完整性分析方法

提出了一种适用于高速互连电路的信号完整性快速仿真方法。根据电流返回路径 不同,该方法将有过孔的三维互连结构分解为电源平面对阻抗模型和微带线模型,先单独分 析两种模型特性,再级联以求解整个互连结构特性。与全波仿真方法相比,本方法在保证准 确度的前提下可将仿真时间从95 min降低至1 min以内。分析了电路板参数、去耦电容和短 路孔对信号完整性的影响,结果表明插入损耗由电源平面结构在过孔位置处的自阻抗决定。 在工程设计中,可采用减小电源平面对结构厚度、添加去耦电容和选择适当的过孔位置等方 法提高信号完整性     

过孔转换信号完整性分析的区域分解有限元法

提出了一种基于区域分解的二维有限元法分析多层印制电路板电源/地平面中过孔转换结构的信号完整性.过孔电流产生的电磁场呈三维结构,其中,一部分电磁波沿过孔轴向传输,另一部分电磁波在电源/地平面间沿径向传播.采用一虚拟柱面将求解区域分割为过孔区和电源/地平面区.将过孔区建模为以周向磁场为主分量的二维轴对称问题,而将电源/地平面区建为以垂直电场为主分量的二维模型.首先求解电源/地平面区的二维边值问题获得分割边界上节点的波阻抗,然后将该波阻抗代入过孔区模型中分割边界节点的边界条件,从而计算出过孔信号传输的S参数.所提方法通过模型缩减可实现对微细过孔结构信号完整性的精确快速计算,且采用全波电磁场分析软件对算法的有效性和准确性进行了验证.     

空心硅通孔的设计及其传输性能

硅通孔(TSV)能够实现信号的垂直传输,是微系统三维集成中的关键技术,在微波毫米波领域,硅通孔的高频传输特性成为研究的重点。针对微系统三维集成中,无源集成的硅基转接板的空心TSV垂直传输结构低损耗的传输要求,进行硅通孔的互连设计和传输性能分析。采用传输线校准方式,首先在硅基转接板上设计TSV阵列接地的共面波导(CPW)传输线和带TSV过孔的传输结构,并分别进行仿真分析,计算得出带TSV过孔的传输结构的插入损耗;然后通过后道TSV工艺,在硅基转接板上制作传输线和带TSV过孔的传输结构,用矢量网络分析仪法测试传输线和带TSV过孔的传输结构的插入损耗;最后计算得到单个TSV过孔的插入损耗,结果显示在0.1～30 GHz频段内其插入损耗S21≤0.1 dB,实现了基于TSV的低损耗信号传输。     

一种基于倒装芯片的超宽带BGA封装差分传输结构

随着高速数字电路和射频微波电路对时钟频率和带宽的要求越来越高，差分传输结构因其优良的噪声抑制和抗干扰性能而受到越来越多的重视。提出了一种基于倒装芯片的超宽带球栅阵列(BGA)封装差分传输结构。整体传输结构包括采用陶瓷材料制作的倒装芯片用基板、BGA封装焊球和印制电路板(PCB)。主要分析了差分垂直传输结构的尺寸参数对阻抗和截止频率的影响，并利用阶梯过孔减小阻抗不连续性。整体结构的传输性能通过矢量网络分析仪测试的散射参数来表征。测试与仿真结果具有较好的一致性，在DC～60 GHz频段，差分传输结构的回波损耗≤-15 dB,插入损耗优于-1 dB,为超宽带倒装芯片的封装设计提供参考。     

多层PCB 电源地平面返回路径阻抗的边界元分析

研究了多层印制电路板(PCB)中含有一个信号过孔的电源/地平面返回路径阻抗的频域特性,并分析采用添加短路过孔的方法减小多层PCB的输入阻抗.电源/地平面形成了径向传输线结构,反焊盘处的输入阻抗即为信号电流在电源/地平面间的返回路径阻抗.在电源/地平面外部边界施加PMC(完全导磁体)边界条件,在反焊盘处施加电流激励源,短路过孔轴向电场为零,采用高效的二维边界元法求解.计算了10GHz内电源/地平面返回路径的输入阻抗.结果表明:在两特性相同的平面之间添加短路孔可以降低输入阻抗,同时,电源、地平面的输入阻抗随频率变化交替呈现容性或感性,在反谐振频率处输入阻抗值可达几百欧姆,此外,在频率较低时输入阻抗可用静态电容或静态电感表示.采用基于全波分析的有限元软件验证了计算结果和计算方法的正确性.     

过孔结构对电源分配系统性能的影响研究

针对某基于FPGA的高速高密度控制板,研究了过孔结构对电源纹波的影响。分析过孔内径、焊盘和反焊盘对目标阻抗的影响,仿真计算电源分配系统中不同过孔结构下的电源纹波,实现控制板电源完整性优化,给出最佳的过孔结构设计方案。研究结果表明:过孔结构的不同将引起电源分配系统性能的变化,在走线安全距离的范围内,孔内径和焊盘直径越大,电源纹波越小,电源纹波从–10.0%~2.4%优化为–8.85%~1.14%。     

基于硅基集成工艺的基板堆叠传输结构设计

随着电子产品向小型化、轻量化方向发展,堆叠基板的垂直互连成为高密度电路集成的关键技术。垂直互连结构会影响跨层传输的信号质量,进而影响电路的射频性能。基于该互连结构的主要传输原理,采用多层硅基板进行堆叠,通过焊球实现上下层的信号传输,利用HFSS仿真软件建立垂直互连结构模型,分析了关键结构参数对传输性能的影响。仿真结果表明优化后的垂直互连结构在DC～20 GHz的频段内回波损耗优于15 dB,传输损耗优于0.5 dB,能够实现良好的微波传输性能。     

新型三维立体集成接收模块设计与实现

讨论了不同种三维集成技术设计方法,利用LGA结构方式设计上下基板间垂直互连,通过垂直过孔与地平面之间寄生参数的优化,达到高频宽带匹配。设计两通道X波段接收模块,将上述垂直互连结构运用到该模块结构设计中,减小模块体积。该接收模块接收增益大于31dB,噪声系数小于3.5dB,移相精度小于4°,体积仅为24mm×15mm×8mm,封装效率达到100%。     

电源完整性分析及应用

由于同步开关所产生的噪声电流,电源完整性问题如今已成为制约整个高速数字系统性能的一个关键因素。电源分配网络构成了高速数字系统最庞大最复杂的互连,约占全部互连空间的30%~40%。系统中所有的器件都直接或间接地连接到电源分配网络上,因此电源分配网络设计与电源完整性分析是数字系统中最复杂的部分。电源分配网络是高速数字设计的核心,直接影响电源完整性、信号完整性和电磁完整性等系统的性能。着重阐述了电源分配网络及频域目标阻抗法,并结合实际设计进行电源完整性的仿真分析。     

键合类陶瓷外壳结构对高频信号传输性能的影响

针对陶瓷外壳中影响高频信号传输性能的键合指、传输线、过孔和返回路径平面等结构进行仿真研究,得到了在0～ 20 GHz频带内的最优参数模型.将其应用于某CLGA49陶瓷外壳产品,高频信号传输性能实测结果与仿真结果符合较好,验证了仿真结果的准确性.结果 表明,增大键合指与键合丝连接处的宽度为与之相连接微带传输线宽2～2.3倍时,传输性能显著提高;单端阻抗为50 Ω,线宽更窄的互连线更有利于传输高频信号;过孔直径增大,接地过孔长度增长会改善传输性能;减少陶瓷外壳中返回路径平面的层数会改善高频信号的传输性能.     

基于LTCC技术的多层垂直转换电路设计

低温共烧陶瓷(LTCC)是实现小型化、高可靠性多芯片组件的一种理想技术方式。多层转换电路实现了微波信号在基板内部传输。文章研究了微带线到带状线背靠背式多层转换电路,优化设计了通孔之间距离以及通孔到带状线之间的距离,仿真结果与实测较为吻合。     

Broadband Via-Free Microstrip Balun Using Metamaterial Transmission Lines

A novel metamaterial broadband microstrip balun design is proposed. The broadband balun consists of a pair of identical metamaterial transmission lines. In the odd mode, a virtual ground is formed between the symmetric plane. The odd mode is allowed while the even mode is rejected. No vias are required to realize the shunt inductors of the metamaterial lines, and no power divider is used. Baluns with good performance can be achieved. In this letter, two baluns are fabricated and measured. For the balun with seven units, the output amplitude difference is less than 0.7 dB, and the differential phase is 181deg plusmn 3deg from 1.6 to 3.6 GHz, while the input return loss is greater than 10 dB.     

一种X 波段磁场耦合式波导-微带转换结构

波导-微带转换器是微波集成电路和天馈线系统中的重要器件。结合具体应用,设计了一款新型、宽带磁耦合式波导-微带转换器。和传统结构相比,本设计用双层的贴片结构代替金属块状阶梯脊,通过在贴片上加载金属过孔来展宽转换的带宽;将阶梯状金属贴片和微带探针一体化设计,从而避免了焊接带来的损耗和结构不稳定,并且减小了加工难度,降低了重量和成本。测试结果表明,波导-微带转换器的两个端口在8.85～11.52GHz 的频带内回波损耗小于-15 dB,插入损耗约为0.8dB,均满足应用需求。     

基片集成非辐射介质波导激励电路研究

随着直接在印刷电路板(PCB)或金属化的介质板上制作基片集成非辐射介质(SINRD)波导的概念提出,如何用平面电路的方式激励此种SINRD波导是今后广泛应用SINRD波导电路的要解决的关键技术之一,这是因为这一技术的解决可以为平面多层化毫米波系统在更高频率上的使用打下基础.本文提出了一种利用微带线到槽线过渡结构,然后利用槽线准TEM波主模和SINRD波导LSM11主模的场型相似性,用槽线去激励PCB型SINRD波导的新型馈电结构.通过使用多层结构,电路由两层的ArlonTC600的PCB组成,从微带结构到槽线的过渡电路可以直接焊接在稍薄的板子上.接下来可在接近SINRD波导介质条带的中心位置激励所需的工作模式LSM11模,这种槽线到SINRD波导的配置可以获得更宽的带宽和高度的集成.仿真和实验结果证实了上述观点的正确性.     

A compact and high performance dual-band bandpass filter based on unbalanced composite right/left-handed transmission lines for WLANs applications

In this paper, a novel compact microstrip dual-band (DB) bandpass filter with high selectivity for wireless local area networks applications is proposed. The design procedure is based on unbalanced composite right/left-handed (UCRLH) transmission lines (TLs). The DB features can be achieved by unbalancing the CRLH transmission line. The necessary conditions to obtain a discontinuous transition between the left- and right-handed bands, intended to provide UCRLLH TL, are investigated. The application of this technique to design of compact DB filters is illustrated. The structure of the proposed DB filter is implemented by a series interdigital capacitor located between two microstrip lines that shorted to the ground plane by vias. The vias with microstrip lines acting as a shunt connected inductor while the series capacitor is realized by interdigital capacitor. The design procedure based on a simple equivalent circuit is also introduced. The proposed filter has advantages such as compact size, easy fabrication, high selectivity, low insertion loss, high return loss and, design flexibility. To validate the proposed technique, the proposed DB filter has been fabricated and tested. Good agreement has been found between simulation and measurement results. The total size of the proposed UCRLH DB filter is 0.17 λ_g × 0.048 λ_g, where λ_g is the guided wavelength of the lower pass-band. The size of the proposed DB filter is more compact in comparison with known similar filters.     

Development of a Broadband Coplanar Waveguide-to-Microstrip Transition With Vias

A transition from coplanar waveguide (CPW)-to- microstrip with vias is often used in wafer-probe measurements. This paper shows how field and impedance matching are used to develop a wideband transition. This paper demonstrates how the presence and placement of the vias affect the bandwidth and alters the impedance of the transition. The measured results on a transition show that a wideband transition with return loss better than 10 dB and an insertion loss less than 1.5 dB up to 36.64 GHz is obtained. The measurements show excellent agreement with simulation. The work presented in this paper provides a better understanding about a CPW-to-microstrip transition with vias as well as design procedures and principles that can be utilized to facilitate the realization of a broadband CPW-to-microstrip transition with vias.      

Improving power analysis attack resistance using intrinsic noise in 3D ICs

Three-dimensional (3D) integration is envisioned as a natural defense to thwart side-channel analysis (SCA) attacks on the hardware implementation of cryptographic algorithms. However, neither physical experiments nor quantitative analysis is available in existing works to study the impact of power distribution network (PDN) on the SCA attacks. Through quantitative analyses and experiments with realistic 3D models, this work demonstrates the impact of noise in PDN on the 3D chip's resilience against correlation power analysis (CPA) attack, which is one of SCA attacks. The characteristic of PDN noise is extracted from our experiments. To expand the natural defense originated from the 3D integration, this work proposes to exploit the PDN noise inherently existing in 3D chips to thwart CPA attacks. Instead of introducing external noise or flattening the power profile, the proposed method utilizes the spatially and temporally varied supply voltages from other 3D planes to blur the power correlation of the crypto unit. Both theoretical analysis and experimental validation prove that the proposed method can effectively enhance the resilience of a crypto unit embedded in the 3D chip against CPA attacks. Simulation results show the proposed method improves the average guessing entropy by 9× over the baseline. Emulation on an FPGA platform demonstrates that the proposed method successfully slows down the key retrieval speed of CPA attack, with significantly less power overhead than representable power equalization techniques. Test vector leakage assessment (TVLA) shows that the proposed method improves the confidence to accept null hypothesis 201× over the baseline.     

基于介质集成悬置槽线的差分至单端功分器北大核心CSCD

设计了一种基于介质集成悬置槽线的宽带差分至单端功分器。采用槽线与微带线耦合的差分过渡结构,实现了差分电路与单端电路的互连。在较宽的工作频率范围内实现了较好的共模噪声抑制。在10.52~15.58 GHz的频率范围内,测得差分端口处的回波损耗优于10 dB。输出端口在10.1~15 GHz的频率范围内保持15 dB以上的隔离度。差分工作模式下,功分器输出的两路信号具有幅值相等、相位相反的特点。所设计的电路基于多层板结构,将槽线及其核心电路悬置于多层板内置的腔体中,具有自封装、低辐射损耗等优势。     

Dual-band bandpass filter based on dual-plane microstrip/interdigital DGS slot structure

A novel dual-band bandpass filter based on a dual-plane structure consisting of both a microstrip and a defected ground structure (DGS) slot with an interdigital shape is proposed. The microstrip structure is connected to the ground plane by grounding vias to obtain tight coupling. By tuning the length of the fingers in the DGS, it is convenient to change the first passband operating frequency. The equivalent-circuit model is derived for the filter. A filter with two passbands centring at 2.44 and 3.28 GHz is shown with stopband attenuation of greater than 30 dB over the frequency range 3.7- 9 GHz.     

一种新型毫米波集成波导微带转换的分析与设计

提出一种新型集成于单层微带基片的毫米波集成波导微带转换 ,由一圆形微带谐振器、微带共面波导探针组成。利用全波分析软件对该转换器进行了分析计算、优化设计。测试了波导微带转换实物 ,结果表明 ,在Ka波段在 1 GHz频带内 ,该波导微带转换具有较低的插入损耗 ( <0 .4d B)和反射损耗 ( <-1 4d B)。可满足相关毫米波微带集成电路系统的应用要求。