基于事务断言验证及SDH芯片验证平台

提出了基于事务断言验证技术,用属性说明语言(Property Specification Language,PSL)描述系统的属性,用事务进行系统的验证,通过编程语言接口机理和工具控制语言来控制验证中PSL断言的状态,使得基于PSL的断言验证可以事务的形式灵活地应用。采用该技术建立了同步数字体系(Synchronous Digitial Hierarchy,SDH)验证平台,验证了超过100万门交换芯片的功能,实践表明,该方法极大的提高了验证覆盖率和验证效率。     

断言语言支持自定义谓词的程序验证器原型

基于逻辑推理的方法进行程序验证是形式化程序验证的研究热点.目前的自动验证工具为了保证自动性,对描述程序性质的断言语言都有较多限制,导致程序的某些递归性质难以用断言语言表述.本文在一个面向指针程序、基于先前自行设计的形状图逻辑、依赖于自动定理证明工具Z3的自动程序验证原型系统上,通过在断言语言中引入自定义谓词来增强断言语言的表达能力,使得该原型系统不仅能自动验证含操作易变数据结构的程序的性质,也能自动验证一些不含指针的程序的性质.     

基于PSL断言的宽带电路交换芯片验证

利用基于PSL断言的验证方法验证了宽带电路交换芯片XYDXC160的设计。该芯片单片支持64路2.488Gb/s STM-16帧结构的SDH码流的输入/输出，实现1 024×1 024 STM-1流的无阻塞电路交换。断言技术的引入，降低了验证工作的复杂度，提高了验证的速度和效率，确保了验证工作的质量。     

通用SPI Flash控制器的设计与验证

为提高X处理器的可靠性、节省其芯片管脚及功耗,以串行外设接口(SPI)Flash作为程序加载存储器,设计一款通用的SPI Flash控制器,给出其组成结构及具体实现方法。采用基于属性描述语言(PSL)的断言检查对该控制器进行功能验证,以降低验证复杂度、提高验证速度和质量。实验结果证明,其功能覆盖率达到了100%。     

覆盖率驱动的芯片功能验证设计与实现

随着芯片集成度的发展,芯片性能越来越高,而上市时间越来越短,芯片验证在芯片设计中非常关键并贯穿于整个设计过程,验证的效率和质量直接决定着芯片的成败。提出了基于覆盖率驱动的芯片功能验证方法,定义了基于功能点覆盖率驱动的验证流程,利用PSL语言描述断言检查很有效,通过模拟工具检查断言是否成功,从而判断设计是否满足系统的功能要求。在网络接口芯片实际应用中,有效地降低了验证工作的复杂度,同时提高了验证的速度和质量。利用功能覆盖率数据判断测试激励的正确性和完整性,同时用覆盖率数据定量评价验证进程,提高了整个设计的效率。     

SV DPI技术在FPGA仿真验证的应用探讨

SystemVerilog作为近年来逐渐流行的FPGA验证语言,包含了丰富的验证特性：DPI、断言技术、功能覆盖率等,其中DPI接口技术可以帮助验证工程师在验证平台中实现对C或C++的调用,验证工程师可以通过编写C函数来实现复杂激励模型设计,同时也为进行复杂算法的FPGA设计的仿真验证提供了新的验证思路。本文提出一种基于DPI接口的FPGA仿真验证方法,实验表明：利用该方法搭建的仿真验证平台相对于传统的纯verilog验证平台,具有更高的仿真效率和验证的灵活性。该验证方法为算法级FPGA设计的确认测试提供了新的验证思路。     

VLSI设计仿真系统分析编译器的研制

仿真在国内外都是关键攻关项目，而研究仿真的办法基本上都是用某种语言对问题进行描述，然后编译，根据需要产生仿真结果。但问题的描述语言品种很多，如果针对每种语言都研制其编译器，那么花费许多的人力、财力、不划算。因此，本文介绍一种用于ＶＬＳＩ设计仿真中的硬件描述语言（ＨＤＬ）到Ｃ语言的转换实例，其设计思想及实现办法适于各类问题描述语言分析编译器的研制     

基于XML的信息物理融合系统组件建模与仿真

信息物理融合系统（CPS）涉及多种计算模型的集成和协同工作，针对CPS设计方法不统一、重塑性差、复杂度高、难以协同建模验证等问题，提出一种结构化、可描述行为的异元组件模型。首先，用统一组件建模方法进行建模，解决模型不开放问题；然后，用可扩展标记语言（XML）规范描述各类组件，解决不同计算模型描述语言不一致和不可扩展问题；最后，用多级开放组件模型的协同仿真验证方式进行仿真验证，解决验证的不可协同问题。通过通用组件建模方法、XML组件规范描述语言以及验证工具平台XModel对医用恒温箱进行了建模、描述和仿真。医用恒温箱的案例表明，这种模型驱动建立可重塑异元组件并确认其设计正确性的过程，支持信息物理协同设计和边构建边纠正，可避免在系统实现过程中发现问题时再进行反复修改。     

基于VHDL语言的交通控制器设计

该文介绍了一种基于VHDL语言的交通控制器设计,以QuartusII为软件开发平台,文中重点介绍该交通控制器的设计原理、设计步骤。在此基础上给出了基于VHDL硬件描述语言的系统实现源代码以及仿真结果,通过仿真结果进一步验证了该交通控制器方案的正确性,从而展示VHDL语言的强大结构和优秀特性。     

基于VHDL语言的交通控制器设计

该文介绍了一种基于VHDL语言的交通控制器设计,以QuartusII为软件开发平台,文中重点介绍该交通控制器的设计原理、设计步骤。在此基础上给出了基于VHDL硬件描述语言的系统实现源代码以及仿真结果,通过仿真结果进一步验证了该交通控制器方案的正确性,从而展示VHDL语言的强大结构和优秀特性。     

System-level design language standard needed

The combination of SystemVerilog, SystemC, and the property specification language (PSL) promises a powerful and flexible foundation for design. Together, these standards address clear needs for emerging software-rich designs; critical capabilities for these standards include advanced verification features such as solvers and constrained random testing. This combination of standards brings powerful assertion capabilities that, with PSL, provide a bridge to formal verification and the ability to apply assertions across multiple design languages.     

Symbolic model checking APSL

Property specification language (PSL) is a specification language which has been accepted as an industrial standard. In PSL, SEREs are used as additional formula constructs. In this paper, we present a variant of PSL, namely APSL, which replaces SEREs with finite automata. APSL and PSL are of the exactly same expressiveness. Then, we extend the LTL symbolic model checking algorithm to that of APSL, and then present a tableau based APSL verification technique, which can be easily implemented via the BDD based symbolic approach. Moreover, we implement an extension of NuSMV, and this adapted version supports symbolic model checking of APSL. Experimental results show that this variant of PSL can be efficiently verified. Henceforth, symbolic model checking PSL can be carried out by a transformation from PSL to APSL and symbolic model checking APSL.     

Symbolic model checking APSL

Property specification language (PSL) is a specification language which has been accepted as an industrial standard. In PSL, SEREs are used as additional formula constructs. In this paper, we present a variant of PSL, namely APSL, which replaces SEREs with finite automata. APSL and PSL are of the exactly same expressiveness. Then, we extend the LTL symbolic model checking algorithm to that of APSL, and then present a tableau based APSL verification technique, which can be easily implemented via the BDD based symbolic approach. Moreover, we implement an extension of NuSMV, and this adapted version supports symbolic model checking of APSL. Experimental results show that this variant of PSL can be efficiently verified. Henceforth, symbolic model checking PSL can be carried out by a transformation from PSL to APSL and symbolic model checking APSL.     

An automatic ABV methodology enabling PSL assertions across SLD flow for SOCs modeled in SystemC

Property specification languages and ABV (assertion-based verification) driven by simulation are being recognized by many as essential for verification of today’s increasingly complex designs. In addition, there are few mature approaches that concentrate on improving assertion integration with high-level designs modeled in SystemC. This paper discusses the issues faced within SystemC environments to incorporate PSL (property specification language) assertions. It also proposes an automatic solution that enhances SOC (system on chip) SLD (system level design) flow with PSL assertions embedded into SystemC designs.     

On regular temporal logics with past

The IEEE standardized Property Specification Language, PSL for short, extends the well-known linear-time temporal logic LTL with so-called semi-extended regular expressions. PSL and the closely related SystemVerilog Assertions, SVA for short, are increasingly used in many phases of the hardware design cycle, from specification to verification. In this article, we extend the common core of these specification languages with past operators. We name this extension PPSL. Although all ω-regular properties are expressible in PSL, SVA, and PPSL, past operators often allow one to specify properties more naturally and concisely. In fact, we show that PPSL is exponentially more succinct than the cores of PSL and SVA. On the star-free properties, PPSL is double exponentially more succinct than LTL. Furthermore, we present a translation of PPSL into language-equivalent nondeterministic Büchi automata, which is based on novel constructions for 2-way alternating automata. The upper bound on the size of the resulting nondeterministic Büchi automata obtained by our translation is almost the same as the upper bound for the nondeterministic Büchi automata obtained from existing translations for PSL and SVA. Consequently, the satisfiability problem and the model-checking problem for PPSL fall into the same complexity classes as the corresponding problems for PSL and SVA.     

基于混合自动机的PSL模型研究

基于SPICE的计算机仿真方法在混合信号电路验证应用中具有较大的计算开销,讨论基于属性描述的建模方法减小计算开销的问题。通过分析PSL(property specification language)对系统属性的形式化描述方法,并分析混合自动机理论对混合信号系统抽象能力,提出了适合于混合信号电路系统快速验证的PSL模型。结合混合自动机对PSL进行了基于混合自动机语义特点的扩展,使用巴克斯—诺尔范式对其拓展后语法进行规范,提出具有描述混合信号电路行为特性的HAPSL(hybrid automata-base     

Optimized temporal monitors for SystemC

SystemC is a modeling language built as an extension of C++. Its growing popularity and the increasing complexity of designs have motivated research efforts aimed at the verification of SystemC models using assertion-based verification (ABV), where the designer asserts properties that capture the design intent in a formal language such as PSL or SVA. The model then can be verified against the properties using runtime or formal verification techniques. In this paper we focus on automated generation of runtime monitors from temporal properties. Our focus is on minimizing runtime overhead, rather than monitor size or monitor-generation time. We identify four issues in monitor generation: state minimization, alphabet representation, alphabet minimization, and monitor encoding. We conduct extensive experimentation and identify a combination of settings that offers the best performance in terms of runtime overhead.