A compact model for multiterminal bipolar devices used in smartpower applications

Complex technologies merging low-voltage bipolar devices and vertical current-flow power transistor allow more smart functions at low chip cost but pose problems during the design phase because there is no way to predict the influence of the high-voltage transistor over the control components by using standard bipolar junction transistor (BJT) models. In fact the large inductive load usually present in high-voltage power transistors applications forces both negative substrate voltage and spurious currents that can induce positive feedback among parasitic devices, downgrading the performance of a single device and so of the whole circuit. In this work we introduce a model for the five-terminal bipolar devices used in smart power applications. The model accounts for all main static and dynamic parasitic effects and gives results in very good agreement with experimental data on both simple devices and complex integrated circuits currently implemented in commercial products for microprocessor based engine management systems (EMS's)     

Optimized design of a merged bipolar MOSFET device

Numerical techniques have been applied to predict the steady-state characteristics of lateral bipolar-MOSFET (BIMOS) power switching devices. The BIMOS has the same structure as a lateral double-diffused MOSFET (LDMOS), with the p-type channel region acting as the base of an n-p-n transistor. By merging MOSFET and bipolar transistors in a lateral configuration, a monolithic power-integrated circuit is realized which retains some of the desirable features of both types of transistors for switching applications. Specifically, the structure of a switching device with low on-resistance high voltage capability, fast switching speed, and high input impedance is derived which does not require significantly increased device fabrication complexity. A special junction isolation design was used to limit the parasitic effects involving the substrate. These parasitic effects can degrade the performance of the BIMOS by reducing the gain of the n-p-n transistor and introducing a large substrate current. An off-state model has been developed in order to study the field shaping effects which occur with the inclusion of the junction isolation. The design is optimized to obtain a high-breakdown-voltage low-on-resistance parasitic-free monolithic-power integrated circuit.     

高压BCD集成电路中高压功率器件的设计研究

高压功率集成电路的设计与制造因其具有的高技术难度而极具挑战性。所谓高压功率集成电路 (HV-PIC) ,是指将需承受高电压 (需达数百伏 )的特定功率晶体管和其它低压的控制电路部分兼容 ,制作在同一块 IC芯片上。文中以器件模拟软件 Medici为工具 ,用计算机仿真的方法 ,研究了高压 BCD电路中高压功率器件的设计问题 ,其中包括器件结构、掺杂浓度、结深等主要参数及其它一些技术因素对器件耐压的影响 ,并给出了相应物理意义上的分析。根据这一设计 ,在国内进行了一块高压功率 BCD集成电路的试制 ,经测试 ,耐压超过 660伏 ,输出功率 40 W,且电路的其它器件参数达到设计值 ,IC电路整体功能正常 ,所有参数达标     

Steady state and transient analysis of SFIIL

Steady state and transient analyses of substrate fed integrated injection logic (SFIIL) have been carried out using an injection model simply by merging all parallel diodes into a single composite diode. The upward gain of the NPN transistor, vertical PNP transistor gain and extrinsic delay of SFIIL devices have been computed for various device areas, junction depths and doping concentrations.     

The effects of interconnect process and snapback voltage on the ESDfailure threshold of NMOS transistors

The electrostatic discharge (ESD) failure threshold of NMOS transistors in a shelf-aligned TiSi₂ process has been identified to be sensitive to both interconnect processes and device structures. For a consistently good ESD protection level, there is a maximum limit of TiSi₂ thickness formed on a shallow junction. The thickness is less than that required to ensure a low junction leakage current. The effect of contact processes on ESD is also studied. Both the size and quantity of contacts on the source-drain area of NMOS transistors have important effects on the ESD failure threshold of the NMOS transistor. The ESD failure threshold voltage an NMOS transistor is strongly correlated with the snapback voltage of its lateral parasitic bipolar transistor. The ESD pass voltage or the highest current that an NMOS transistor can withstand is a decreasing function of its parasitic bipolar snapback voltage. This finding explains why an abrupt junction device has a higher ESD failure threshold voltage than a graded-junction device. The gate potential of an NMOS transistor also has important effects on its failure threshold voltage     

高压功率集成电路中LDMOS的设计研究

高压功率集成电路(HVPIC),是指将需要承受高电压(达数百伏)的特定功率晶体管和其它低压的控制电路部分兼容,制作在同一块IC芯片上。本文以器件模拟软件MEDICI为工具,用计算机仿真的方法,研究了一种适用于高压功率集成电路的单晶结构的LDMOS的设计问题,其中包括器件的N阱掺杂浓度、衬底浓度、P反型层浓度和结深等主要参数对击穿电压的影响,重点分析了N阱中P型反型层与漏极N^ 区距离Lp对器件耐压的影响,并分析了相应的物理意义。仿真结果表明,Lp对器件耐压有明显的影响。通过优化设计对应于各个参数器件的击穿电压变高,并且受工艺参数波动影响较小,达到了功率集成电路耐压的要求。     

A silicon/indium arsenide source structure to suppress the parasitic bipolar-induced breakdown effect in SOI MOSFETs

We introduce Silicon/indium arsenide (Si/InAs) source submicron-device structure in order to minimize the impact of floating body effect on both the drain breakdown voltage and single transistor latch in ultra thin SOI MOSFETs. The potential barrier of valence band between source and body reduces by applying the Indium Arsenide (InAs) layer at the source region. Therefore, we can improve the drain breakdown by suppressing the parasitic NPN bipolar device and the hole accumulation in the body. As confirmed by 2D simulation results, the proposed structure provides the excellent performance compared with a conventional SOI MOSFET thus improving the reliability of this structure in VLSI applications.     

Non-linear thermal modeling of DMOS transistor and validation using electrical measurements and FEM simulations

The relevance of thermally non-linear silicon material models for transient thermal FEM simulations of smart power switches (SPS) is proved by a power silicon test device consisting of two power transistors and eleven integrated temperature sensors distributed over the silicon die. The test device is heated up by turning on an integrated power transistor in short-circuit for several milliseconds at two different initial temperatures. These thermal events correspond to a real situation that can occur in the application. The power dissipation in the power transistor is calculated from the measured source current and drain-source voltage, and subsequently used as an input to the FEM simulation. The temperature change on the test chip is measured by the integrated temperature sensors. An FEM model of the test chip encapsulated in a plastic package has been built in the FlexPDE simulator. The emphasis is put on the macroscopic modeling of the power transistor where an electro-thermal approach is reduced to a purely thermal one. Finally, the thermal events are simulated using FEM and compared to the temperature measurements. The results have shown that our modeling approach including non-linear properties of silicon can be used to investigate the thermal transients in SPS devices with high accuracy.     

MOS器件中寄生双极型晶体管模型参数的提取

在晶体管GP模型基础上,采用Silvoca公司的UTMOST模型参数提取程序,得到一种双极型晶体管模型参数的提取方法.用此方法对PCM测试芯片的寄生三极管进行参数提取和模拟,模拟结果与测试结果符合得较好.     

Bipolar design considerations for the automotive environment

In view of the detrimental voltage transients associated with the automotive environment, and the advantages and limitations of the present bipolar integrated circuits with respect to this environment, new bipolar circuit and device innovations have been specifically developed to economically protect the IC from these destructive transients and improve the IC's functional performance. Many of these techniques prevent the negative voltage transients from injecting electrons into the P-type substrate, insuring that a newly defined parasitic lateral n-p-n transistor cannot degrade the performance of the IC. New and effective high-frequency input filtering techniques were also devised on the chip to prevent the high-frequency voltage transients from gaining access to the IC circuitry, especially at the logic inputs.     

New device structure using array transistors and flexible U-grooves suitable for 18-V, high-performance SOI complementary bipolar LSIs

We have developed a new device structure suitable for high-performance and high-power mixed signal large scale integrations (LSIs) using 0.35-/spl mu/m SOI complementary bipolar transistors. The new structure is composed of array transistors for various operating currents and flexible U-groove (trench) layout for high-power transistors. Thermal simulation results showed that the thermal resistance could be reduced by 40% by using the flexible U-groove layout. Test structure measurements showed that the maximum operating currents of a double polysilicon self-aligned NPN transistor were improved by 2 and 3.5 times by using ballasting resistors and ballasting resistors with flexible U-groove layout, respectively. The effects of the transistor structure on the thermal resistance and the maximum operating current were discussed.     

Beating the heat [CMOS hot-carrier reliability]

CMOS hot-carrier reliability at both transistor and circuit levels has been examined. Accurate reliability assessment requires defining suitable criteria for acceptable performance for both circuit and individual transistors. As device designers meet demands for greater speed and more complex circuitry accompanied by shrinking the size of transistor into the deep-submicron regime, they have to contend with increase in current densities and higher electric fields. Though in general a MOSFET's driving capability increases as the channel length decreases, the resulting high field will eventually limit the driving capability of the device. The authors discuss improving CMOS hot-carrier reliability through analysis, modelling and simulation     

Model for DMOST threshold voltage

An analytical model for the channel region in MOS-gated power transistors has been developed. The model takes into account the effect of substrate doping gradient on the threshold voltage of the transistor and it can be applied to lateral and vertical DMOS and IGBT transistor structures. The model has been tested by comparing the calculated I-V characteristics for an MOS structure having various doping gradients to the results from a 2-D device simulator.<>     

Oxygen implantation to suppress parasitic bipolar action in CMOS

Oxygen implantation and subsequent epitaxial silicon deposition have been developed to improve CMOS latchup prevention through reducing the current gains of parasitic bipolar transistors. The buried oxygen implanted layer is well confined, and defects do not extend into the epitaxial silicon layer. The device characteristics of the n- and p-MOSFETs fabricated on a wafer with the oxygen implantation are therefore not affected by the buried implanted layer. The oxygen implanted layer can reduce the minority-carrier lifetime and hence decrease the current gain of the lateral parasitic bipolar transistor. In addition, it introduces a potential barrier which decreases the current collected at the frontside contact of the vertical parasitic bipolar transistor. The common base current gain is reduced by 50% and 80% for the lateral and the vertical parasitic bipolar transistors, respectively. As a consequence, the CMOS latchup immunity is significantly improved     

Transistor design and thermal stability

A model has been developed for the computation of forward second breakdown due to lateral thermal instability in power transistors. The method of analysis is to derive the steady-state current density and temperature distribution of a given transistor design under specified operating conditions, and then to calculate the response of the device to a temperature impulse suddenly applied internally. The current flow calculations have been carried out by using a distributed transistor model, and for the time-dependent heat flow problem the finite difference approach was used. The effect of device design parameters such as chip thickness, base width, emitter width, base impurity concentration, etc., on the thermal stability has been calculated. Also, the effect on transistor stability of the current and voltage operating point, as well as the heat sink temperature, has been analyzed. Information on the stability of a power transistor under pulsed condition is derived by calculating the time constant for thermal runaway. The results of this analysis indicate that the delay time is of the order of 1 ms.     

Microwave-Rectification RFI Response in Field-Effect Transistors

This paper discusses the rectification of microwave energy in low-medium frequency feld-effect transistors (FET's) and develops a small-signal model for RHI noise analysis in low-frequency linear circuitry. The modeling procedure centers on a Taylor series expansion of the gate voltage-drain current characteristic which shows a small increase in drain current due to a nicrowave voltage at the gate. The increase in drain current is proportional to the variation in transconductance with gate voltage, and the square of the microwave voltage. Analysis of the microwave power in the transistor shows that critical parameters in determnination of the sensitivity are the gate capacitance and the real part ofthe device input impedance, which ultimately is limited by the parasitic resistance between the active channel and contacts.     

Green biomass bistable transistor multivibrator

For the first time a biomass bistable transistor multivibrator using an NPN Philips transistor as the active device and freshly plucked green Champo (Plumaria rubra) leaf cuttings as electrical components (resistance R and capacitance C) has been realized. The frequency and other parameters of the generated pulses, along with the circuit configuration, are presented. The development envisages a novel march towards a green revolution in electronic circuitry.     

A coaxially packaged MADT for microwave applications

A coaxially packaged transistor capable of delivering greater than 11 db of power gain at 1000 Mc, with a resultant maximum frequency of oscillation of 3500 Mc, has been developed. This device is a p-n-p micro-alloy diffused-base transistor (MADT). The principal difference between this device and a standard high-frequency MADT amplifier is the reduction of electrode size and use of a coaxial construction. The parasitic elements, rb', and emitter and collector transition capacities, have very striking effects. Also, the excess phase of alpha at alpha cutoff, as described by Thomas and Moll, can be very large (150° on this device); for this reason, fTrather than fcαshould be used as the figure of merit for graded-base transistors. Because of this excess phase, the value of K(0.85 for homogeneous-base transistors), which is used to relate fTto fcα, can be as low as 0.43 in graded-base transistors of this type.     

Use of zone-melting recrystallization to fabricate a three-dimensional structure incorporating power bipolar and field-effect transistors

Three-dimensional (3-D) structures have been fabricated incorporating power bipolar transistors in a Si substrate and metal-oxide-semiconductor field-effect transistors (MOSFET's) in an overlying silicon-on-insulator (SOI) film that was zone-melting recrystallized with a graphite strip heater. Both N-P-N and P-N-P bipolar transistors were used. The N-P-N devices exhibited no significant change in transistor characteristics after zone-melting recrystallization (ZMR), while the P-N-P devices showed a substantial reduction in breakdown voltage. The MOSFET's exhibited electron mobilities comparable to those in similar devices fabricated in single-crystal Si wafers. The bipolar transistor yield is approximately 90 percent. The unusually high device quality and yield for 3-D structures obtained by the ZMR technique demonstrates the feasibility of fabricating monolithic structures incorporating both logic functions and relatively high-current high-voltage power switches.     

Tunable high-frequency Gm-C filters

We consider known, modified, and new transistor circuits for transconductors and some theory on their application in integrated tunable Gm-C or transconductor-eapacitor filters for high frequencies. The circuits are balanced and mostly complementary. They use bipolar (NPN and VPNP) and/or CMOS transistors. The low delay and low input capacitance of the newer circuits makes them particularly suitable for very high frequencies, in the hundreds of megahertz. The relatively high power efficiency and low noise lead to a low power consumption in combination with a high signal-to-noise ratio. Their simplicity results in a small chip area and hence in low cost. The partly new theory is on noise, sensitivities, quality factors, linearization, power and power efficiencies