A logic nanotechnology featuring strained-silicon

Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si/sub 1-x/Ge/sub x/ in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSFET. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work: 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.     

Implementation of both high-hole and electron mobility in strained Si/strained Si/sub 1-y/Ge/sub y/ on relaxed Si/sub 1-x/Ge/sub x/ (x

Jongwan Jung Lee  M.L. Shaofeng Yu Fitzgerald  E.A. Antoniadis  D.A. 《Electron Device Letters, IEEE》2003,24(7):460-462

BC high-/spl kappa//metal gate Ge/C alloy pMOSFETs fabricated directly on Si (100) substrates

Buried-channel (BC) high-/spl kappa//metal gate pMOSFETs were fabricated on Ge/sub 1-x/C/sub x/ layers for the first time. Ge/sub 1-x/C/sub x/ was grown directly on Si (100) by ultrahigh-vacuum chemical vapor deposition using methylgermane (CH/sub 3/GeH/sub 3/) and germane (GeH/sub 4/) precursors at 450/spl deg/C and 5 mtorr. High-quality films were achieved with a very low root-mean-square roughness of 3 /spl Aring/ measured by atomic force microscopy. The carbon (C) content in the Ge/sub 1-x/C/sub x/ layer was approximately 1 at.% as measured by secondary ion mass spectrometry. Ge/sub 1-x/C/sub x/ BC pMOSFETs with an effective oxide thickness of 1.9 nm and a gate length of 10 /spl mu/m exhibited high saturation drain current of 10.8 /spl mu/A//spl mu/m for a gate voltage overdrive of -1.0 V. Compared to Si control devices, the BC pMOSFETs showed 2/spl times/ enhancement in the saturation drain current and 1.6/spl times/ enhancement in the transconductance. The I/sub on//I/sub off/ ratio was greater than 5/spl times/10/sup 4/. The improved drain current represented an effective hole mobility enhancement of 1.5/spl times/ over the universal mobility curve for Si.     

A novel germanium doping method for fabrication of high-performance p-channel poly-Si/sub 1-x/Ge/sub x/ TFT by excimer laser crystallization

In this letter, a novel process for fabricating p-channel poly-Si/sub 1-x/Ge/sub x/ thin-film transistors (TFTs) with high-hole mobility was demonstrated. Germanium (Ge) atoms were incorporated into poly-Si by excimer laser irradiation of a-Si/sub 1-x/Ge/sub x//poly-Si double layer. For small size TFTs, especially when channel width/length (W/L) was less than 2 /spl mu/m/2 /spl mu/m, the hole mobility of poly-Si/sub 1-x/Ge/sub x/ TFTs was superior to that of poly-Si TFTs. It was inferred that the degree of mobility enhancement by Ge incorporation was beyond that of mobility degradation by defect trap generation when TFT size was shrunk to 2 /spl mu/m/2 /spl mu/m. The poly-Si/sub 0.91/Ge/sub 0.09/ TFT exhibited a high-hole mobility of 112 cm/sup 2//V-s, while the hole mobility of the poly-Si counterpart was 73 cm/sup 2//V-s.     

Fabrication and mobility characteristics of SiGe surface channel pMOSFETs with a HfO/sub 2//TiN gate stack

This paper describes an extensive experimental study of TiN/HfO/sub 2//SiGe and TiN/HfO/sub 2//Si cap/SiGe gate stacked-transistors. Through a careful analysis of the interface quality (interface states and roughness), we demonstrate that an ultrathin silicon cap is mandatory to obtain high hole mobility enhancement. Based on quantum mechanical simulations and capacitance-voltage characterization, we show that this silicon cap is not contributing any silicon parasitic channel conduction and degrades by only 1 /spl Aring/ the electrical oxide thickness in inversion. Due to this interface optimization, Si/sub 0.72/Ge/sub 0.28/ pMOSFETs exhibit a 58% higher mobility at high effective field (1 MV/cm) than the universal SiO/sub 2//Si reference and a 90% higher mobility than the HfO/sub 2//Si reference. This represents one of the best hole mobility results at 1 MV/cm ever reported with a high-/spl kappa//metal gate stack. We thus validate a possible solution to drastically improve the hole mobility in Si MOSFETs with high-/spl kappa/ gate dielectrics.     

Uniaxial-process-induced strained-Si: extending the CMOS roadmap

This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date. A more complete data set of n- and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement. Strained-Si hole mobility data are analyzed using six band k/spl middot/p calculations for stresses of technological importance: uniaxial longitudinal compressive and biaxial stress on [001] and [110] wafers. The calculations and experimental data show that low in-plane and large out-of-plane conductivity effective masses and a high density of states in the top band are all important for large hole mobility enhancement. This work suggests longitudinal compressive stress on [001] or [110] wafers and <110> channel direction offers the most favorable band structure for holes. The maximum Si inversion-layer hole mobility enhancement is estimated to be /spl sim/ 4 times higher for uniaxial stress on (100) wafer and /spl sim/ 2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a [110] wafer.     

Electrical characterization of germanium p-channel MOSFETs

In this letter, we report germanium (Ge) p-channel MOSFETs with a thin gate stack of Ge oxynitride and low-temperature oxide (LTO) on bulk Ge substrate without a silicon (Si) cap layer. The fabricated devices show 2 /spl times/ higher transconductance and /spl sim/ 40% hole mobility enhancement over the Si control with a thermal SiO/sub 2/ gate dielectric, as well as the excellent subthreshold characteristics. For the first time, we demonstrate Ge MOSFETs with less than 100-mV/dec subthreshold slope.     

Mobility enhancement in surface channel SiGe PMOSFETs with HfO/sub 2/ gate dielectrics

We report for the first time drive current enhancement and higher mobilities than the universal mobility for SiO/sub 2/ on Si in compressively strained Si/sub 1-x/Ge/sub x/-on-Si surface channel PMOSFETs with HfO/sub 2/ gate dielectrics, for gate lengths (L/sub G/) down to 180 nm. Thirty six percent drive current enhancement was achieved for Si/sub 0.8/Ge/sub 0.2/ channel PMOSFETs compared to Si PMOSFETs with HfO/sub 2/ gate dielectric. We demonstrate that using Si/sub 1-x/Ge/sub x/ in the channel may be one way to recover the mobility degradation due to the use of HfO/sub 2/ on Si.     

Partially depleted SOI MOSFETs under uniaxial tensile strain

The effects of tensile uniaxial strain on the DC performance of partially-depleted silicon-on-insulator n and p-channel MOSFETs as a function of orientation and gate length are reported. The drain current of the n-MOSFETs increases for both longitudinal and transverse strain orientations with respect to the current flow direction. In the n-MOSFET, longitudinal strain provides greater enhancement than transverse strain. In contrast, for p-MOSFETs, longitudinal strain decreases the current while transverse strain increases the drain current. The magnitude of the fractional change in drain current decreases as gate length is reduced from 20 to 0.35 /spl mu/m. These phenomena are consistent with those of bulk silicon MOSFETs and are shown to be qualitatively correlated with the piezoresistance coefficients of the Si inversion layer. Analysis of the linear drain current versus gate voltage characteristics shows that the threshold voltage is independent of strain while the change in drain current tracks with the change in effective electron and hole mobility. Closer examination shows that as the gate length is reduced from 20 to 0.35 /spl mu/m, the relative increase in low-field electron and hole mobility is constant for transverse strain and generally decreases with gate length for longitudinal strain.     

Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

The authors present a study on the layout dependence of the silicon-germanium source/drain (Si/sub 1-x/Ge/sub x/ S/D) technology. Experimental results on Si/sub 1-x/Ge/sub x/ S/D transistors with various active-area sizes and polylengths are combined with stress simulations. Two technologically important configurations are investigated: the nested transistor, where a polygate is surrounded by other gates, and isolated transistors, where the active area is completely surrounded by isolation oxide. The channel stress, caused by epitaxial Si/sub 1-x/Ge/sub x/ is reduced substantially when the active area is decreased from a large size towards typical values for advanced CMOS technology nodes. Nested transistors with longer gate lengths are more sensitive towards layout scaling than shorter gates. Increasing recess depth and germanium concentration gives larger channel stress, but does not change layout sensitivity. Increased lateral etching leads to higher stress, as well as to reduced layout sensitivity. In small-size transistors, there exists an optimal recess depth, beyond which the stress in the channel will not increase further. For isolated transistor structures, the interaction between Si/sub 1-x/Ge/sub x/ and the isolating oxide can even lead to stress reduction when the recess depth is increased. When technology advances, active-area dimensions will be scaled together with gate lengths and widths. For typical sizes of advanced silicon CMOS Si/sub 1-x/Ge/sub x/ S/D transistors, simulations indicate that the channel stress can be maintained in future technology nodes.     

High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments

For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, the resulting optimal structure obtained was a UT low-defect 2-nm fully strained Ge epi channel on relaxed Si, with a 4-nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5/spl times/ over bulk Si devices, 2/spl times/ mobility enhancement and >10/spl times/ BTBT reduction over 4-nm strained Ge, and surface channel 50% strained SiGe devices. Strained SiGe MOSFETs having UT (T/sub Ge/<3 nm) very high Ge fraction (/spl sim/ 80%) channel and Si cap (T/sub Si cap/<3 nm) have also been successfully fabricated on thin relaxed SOI substrates (T/sub SOI/=9 nm). The tradeoffs in obtaining a high-mobility (smaller bandgap) channel with low tunneling leakage on UT-SOI have been investigated in detail. The fabricated device shows very high mobility enhancements of >4/spl times/ over bulk Si devices, >2.5/spl times/ over strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and >1.5/spl times/ over 60% strained SiGe (on relaxed bulk Si) devices.     

Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs

Large differences in the experimentally observed strain-induced threshold-voltage shifts for uniaxial and biaxial tensile-stressed silicon (Si) n-channel MOSFETs are explained and quantified. Using the deformation potential theory, key quantities that affect threshold-voltage (electron affinity, bandgap, and valence band density of states) are expressed as a function of strain. The calculated threshold-voltage shift is in agreement with uniaxial wafer bending and published biaxial strained-Si on relaxed-Si/sub 1-x/Ge/sub x/ experimental data , and explains the technologically important observation of a significantly larger (>4x) threshold-voltage shift for biaxial relative to uniaxial stressed MOSFETs. The large threshold shift for biaxial stress is shown to result from the stress-induced change in the Si channel electron affinity and bandgap. The small threshold-voltage shift for uniaxial process tensile stress is shown to result from the n/sup +/ poly-Si gate in addition to the Si channel being strained and significantly less bandgap narrowing.     

Application of silicon-germanium in the fabrication of ultra-shallow extension junctions for sub-100 nm PMOSFETs

This work summarizes the results of several experiments to investigate the potential applications of Silicon-Germanium alloy in the fabrication of shallow source/drain (S/D) extension Junctions for deep submicron PMOS transistors. Two approaches were used for the fabrication of p/sup +/-Si/sub 1-x/Ge/sub x//n-Si heterojunctions. In the first approach, high dose Ge ion implantation followed by boron implantation into Si was used to form very shallow p/sup +/-Si/sub 1-x/Ge/sub x//n-Si junctions (x/spl les/0.2). In the second approach, thin Ge films were deposited onto Si substrates by conventional low pressure chemical vapor deposition. This was followed by boron implantation into the Ge and thermal annealing to co-diffuse Ge and B atoms into Si and form p/sup +//n heterojunctions. The electrical characteristics of the heterojunction diodes were comparable to those of conventional Si (homo) junctions. Secondary ion mass spectrometry (SIMS) concentration-depth profiles indicate that dopant segregation in the Si/sub 1-x/Ge/sub x/ regions resulted in the formation of ultra-shallow and abrupt junctions that could be used as S/D extensions for sub-100 nm CMOS generations. PMOS transistors fabricated using these techniques exhibit superior short-channel performance compared to control devices, for physical gate lengths down to 60 nm.     

Characteristics of In/sub x/Al/sub 1-x/N-GaN high-electron mobility field-effect transistor

GaN-based field effect transistors commonly include an Al/sub x/Ga/sub 1-x/N barrier layer for confinement of a two-dimensional electron gas (2DEG) in the barrier/GaN interface. Some of the limitations of the Al/sub x/Ga/sub 1-x/N-GaN heterostructure can be, in principle, avoided by the use of In/sub x/Al/sub 1-x/N as an alternative barrier, which adds flexibility to the engineering of the polarization-induced charges by using tensile or compressive strain through varying the value of x. Here, the implementation and electrical characterization of an In/sub x/Al/sub 1-x/-GaN high electron mobility transistor with Indium content ranging from x=0.04 to x=0.15 is described. The measured 2DEG carrier concentration in the In/sub 0.04/Al/sub 0.96/N-GaN heterostructure reach 4/spl times/10/sup 13/ cm/sup -2/ at room temperature, and Hall mobility is 480 and 750 cm/sup 2//V /spl middot/ s at 300 and 10 K, respectively. The increase of Indium content in the barrier results in a shift of the transistor threshold voltage and of the peak transconductance toward positive gate values, as well as a decrease in the drain current. This is consistent with the reduction in polarization difference between GaN and In/sub x/Al/sub 1-x/N. Devices with a gate length of 0.7 /spl mu/m exhibit f/sub t/ and f/sub max/ values of 13 and 11 GHz, respectively.     

A novel strained Si/sub 0.7/Ge/sub 0.3/ surface-channel pMOSFET with an ALD TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack

Proof-of-concept pMOSFETs with a strained-Si/sub 0.7/Ge/sub 0.3/ surface-channel deposited by selective epitaxy and a TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack grown by atomic layer chemical vapor deposition (ALD) techniques were fabricated. The Si/sub 0.7/Ge/sub 0.3/ pMOSFETs exhibited more than 30% higher current drive and peak transconductance than reference Si pMOSFETs with the same gate stack. The effective mobility for the Si reference coincided with the universal hole mobility curve for Si. The presence of a relatively low density of interface states, determined as 3.3 /spl times/ 10/sup 11/ cm/sup -2/ eV/sup -1/, yielded a subthreshold slope of 75 mV/dec. for the Si reference. For the Si/sub 0.7/Ge/sub 0.3/ pMOSFETs, these values were 1.6 /spl times/ 10/sup 12/ cm/sup -2/ eV/sup -1/ and 110 mV/dec., respectively.     

Scaling and strain dependence of nanoscale strained-Si p-MOSFET performance

Self-consistent fullband Monte Carlo simulations based on nonlocal empirical pseudopotential band structures including spin-orbit splitting are employed to estimate the on-current in nanoscale strained-Si p-MOSFETs. Effective gate lengths from L/sub eff/ = 75 nm down to L/sub eff/ = 25 nm and strain levels corresponding to germanium contents of up to x = 0.4 in the relaxed Si/sub 1-x/Ge/sub x/ substrate are considered. It is found that the on-current continuously increases for growing substrate germanium contents. The strain-induced performance enhancement moderately decreases with scaling, but the improvement at L/sub eff/ = 25 nm still attains 20% for x = 0.4. In contrast to strained-Si n-MOSFETs, increasing the substrate germanium content beyond x = 0.2 is essential for p-MOSFET performance improvement by strain in the sub 0.1 /spl mu/m regime. However, even for x = 0.4 the on-current in a strained-Si p-MOSFET is still smaller than in a corresponding unstrained-Si n-MOSFET.     

Low-Cost and Highly Manufacturable Strained-Si Channel Technique for Strong Hole Mobility Enhancement on 35-nm Gate Length pMOSFETs

Local strained-silicon channel pMOSFETs with minimum gate length down to 22 nm have been fabricated by integrating Ge preamorphization implantation (PAI) for source/drain (S/D) extension, which induces a uniaxial compressive stress in the channel to attain an enhanced pMOSFET performance without additional masks. A 43 % improvement of hole effective mobility has been obtained for 35-nm gate length pMOSFETs with an optimized Ge PAI condition for S/D extension at 1.1-MV cm vertical effective field, and the hole mobility improvement is nearly maintained at higher vertical field. The corresponding enhancement of a saturated drive current is 25 % at 1.3-MV ldr cm vertical field. The scaling strengthens the enhancement of the hole mobility remarkably. No negative effect on electron effective mobility is observed. An analysis by using a zero-order Laue zone diffraction on large angle convergent beam electron diffraction patterns in a transmission electron microscopy confirms that the significant residual compressive strain up to -3.0 % in the channel region is induced for 60-nm gate length strained channel pMOSFETs with the same optimized Ge PAI condition as that of 35-nm gate length pMOSFETs. The depth profiles of the residual compressive strain and shear strain in the channel region are given, respectively. The possible mechanisms are discussed.     

High mobility Ge-on-insulator p-channel MOSFETs using Pt germanide Schottky source/drain

We demonstrate, for the first time, successful operation of Schottky-barrier source/drain (S/D) germanium-on-insulator (GOI) MOSFETs, where a buried oxide and a silicon substrate are used as a gate dielectric and a bottom gate electrode, respectively. Excellent performance of p-type MOSFETs using Pt germanide S/D is presented in the accumulation mode. The hole mobility enhancement of 50%/spl sim/40% against the universal hole mobility of Si MOSFETs is obtained for the accumulated GOI channel with the SiO/sub 2/-Ge interface.     

High work function Ir/sub x/Si gates on HfAlON p-MOSFETs

We have fabricated the fully silicided Ir/sub x/Si-gated p-MOSFETs on HfAlON gate dielectric with 1.7-nm equivalent oxide thickness. After 950/spl deg/C rapid thermal annealing, the fully Ir/sub x/Si/HfAlON device has high effective work function of 4.9 eV, high peak hole mobility of 80 cm/sup 2//V/spl middot/s, and the advantage of being process compatible to the current VLSI fabrication line.     

Si/SiGe n-MODFETs on thin SiGe virtual substrates prepared by means of He implantation

Si/SiGe n-type modulation-doped field-effect transistors grown on a very thin strain-relieved Si/sub 0.69/Ge/sub 0.31/ buffer on top of a Si(100) substrate were fabricated and characterized. This novel type of virtual substrate has been created by means of a high dose He ion implantation localized beneath a 95-nm-thick pseudomorphic SiGe layer on Si followed by a strain relaxing annealing step at 850/spl deg/C. The layers were grown by molecular beam epitaxy. Electron mobilities of 1415 cm/sup 2//Vs and 5270 cm/sup 2//Vs were measured at room temperature and 77 K, respectively, at a sheet carrier density of about 3/spl times/10/sup 12//cm/sup 2/. The fabricated transistors with Pt-Schottky gates showed good dc characteristics with a drain current of 330 mA/mm and a transconductance of 200 mS/mm. Cutoff frequencies of f/sub t/=49 GHz and f/sub max/=95 GHz at 100 nm gate length were obtained which are quite close to the figures of merit of a control sample grown on a conventional, thick Si/sub 0.7/Ge/sub 0.3/ buffer.