Thermal dependence of low-frequency noise in polysilicon thin film transistors

Thermal dependence of low frequency noise in low temperature (≤ 600 °C) polysilicon thin film transistors is studied in devices biased from weak to moderate inversion and operating in the linear mode. Drain current noise spectral density, measured in the temperature range from 260 K to 310 K, is thermally activated following the Meyer Neldel rule. Analysis of the thermal activation of noise, supported by the theory of trapping/detrapping processes of carriers into oxide traps located close to the interface, leads to the calculation of the deep state interface distribution in function of the Meyer Neldel characteristic energy.     

Electrical characteristic analysis using low-frequency noise in low-temperature polysilicon thin film transistors

This study carried out an electrical characteristic analysis using low-frequency noise (LFN) in top gate p-type low-temperature polysilicon thin film transistors (LTPS TFTs) with different active layer thicknesses between 40 nm and 80 nm. The transfer characteristic curves show that the 40-nm device has better electrical characteristics compared with the 80-nm device. The carrier number fluctuation, with and without correlated mobility fluctuation model in both devices, has modeled well the measured noise. On the other hand, the trap density and coulomb scattering in the 40-nm device are smaller compared with the 80-nm device. To confirm the effectiveness of the LFN noise analysis, the trap densities at a grain boundary are extracted using in both devices the similar methods of Proano et al. and Levinson et al. That is, coulomb scattering, caused by the trapped charges at or near the interface, has a greater effect on the device with inferior electrical properties. Based on the LFN and the quantitative analysis of the trap density at a grain boundary, the interface traps between the active layer and the gate insulator can explain the devices' electrical degradation.     

Analysis of self-heating related instability in n-channel polysilicon thin film transistors fabricated on polyimide

In this work, we investigated self-heating related instability in polysilicon thin film transistors (poly-Si TFTs) fabricated on polyimide (PI) substrates. Indeed, when Joule heating becomes relevant, the temperature of the active layer can substantially rise, since the devices are fabricated on thermally insulating substrates. As a result, electrical instability is triggered and attributed to the generation of interface states, due to the Si–H bond breaking, and charge trapping into the gate insulator. In addition, by using 3-dimensional numerical simulations, coupling the thermodynamic and transport models, we analyzed the temperature distribution of the device under operating conditions and found that self-heating is more severe for devices fabricated on plastic substrates.     

Turn-off current variation in drain-offset polysilicon thin film transistors

Bottom gate drain-offset polysilicon thin film transistors (poly-Si TFTs) were fabricated on SiO₂ coated Si wafers. After completing gate oxide deposition, we exposed the wafers to air in a clean room. Poly-Si films were deposited on the gate oxides for the active layer of the drain offset poly-Si TFTs with changing the air-exposure time. Threshold voltage shift to positive value and turn-off current raise with increasing the air-exposure time were observed. In this paper, we focused on evaluating the causes of the turn-off current raise with the air-exposure time. The carbons piled up at the poly-Si/SiO₂ interface were observed by a SIMS measurement, which is considered to be the origin of negative charges. The concentration of the carbon was remarkably increased by expanding the air-exposure time. The existence of the negative charges in the oxide was also found by a capacitance-voltage measurement. We conclude that the carbons originated from the air in the clean room are the main cause of the threshold voltage and turn-off current variation in the drain-offset poly-Si TFTs.     

Modelling velocity saturation and kink effects in p-channel polysilicon thin-film transistors

Experimental measurements and full-2D numerical simulations show that velocity saturation effects in polysilicon thin-film transistor (TFTs) cannot be neglected in order to obtain a precise modelling of output characteristics. Since full-2D numerical simulations are time consuming and unpractical for circuit simulations, we have developed a new quasi-2D model, that takes into account both velocity saturation effects and the presence of a longitudinal electric field in the Poisson's equation, and includes the effect of parasitic bipolar transistor (PBT) action to reproduce kink effect. The agreement of the quasi-2D model with experimental data from p-channel polysilicon TFTs is very satisfactory even for short channel device, and the presence of a velocity-saturated region with a nearly constant free carrier concentration is reproduced without introducing further assumptions.     

Device degradation behavior and polysilicon film morphology of thin film transistors fabricated using advanced excimer laser lateral solidification techniques

The degradation of polysilicon thin film transistors fabricated in films obtained using variations of advanced through-mask excimer laser anneal sequential lateral solidification (SLS) schemes was investigated. The morphology and grain structure of these 50 nm thick polysilicon films was studied using SEM and AFM. Very elongated or square-like polycrystalline silicon grains were observed, as shaped by each crystallization technique. Hot carrier stressing measurements, under gate and drain DC biases, were performed and the TFT device parameters and characteristics were extracted for various stressing times. The threshold voltage V_th, subthreshold slope S and transconductance G_m were observed to exhibit shifts with stressing time, indicating some active layer and interface degradation ascribed to hot carrier injection and trap generation. These shifts depended both on stress conditions and on the fabrication technique used. The hot carrier stressing results thus indicate that the material structure affects the degradation rates of the TFT parameters and trap densities. Furthermore, the device structure and the crystallization conditions, with the resulting film morphology, affect not only the TFT degradation behavior but also other aspects of device performance; the susceptibility to drain current avalanche effects was found to be lower for TFTs in 2^N-shot polysilicon compared to ones in very elongated grain (directional) material.     

Role of high-k gate insulators for oxide thin film transistors

In conventional TFTs, SiO₂ or SiN_x have been used as gate insulators. But they could not induce the high on-current due to their low-capacitance. Since they have low-capacitance that originated from low dielectric constant, on-current of TFTs with low-k insulated are limited by low-capacitance. We have investigated high-k materials, such as HfO₂, ZrO₂ and modified structures for the use of gate insulators in oxide thin film transistors. ZrO₂ and HfO₂ are the most attractive materials with their superior properties, such as high breakdown field intensity (~ 15 MV/cm), high dielectric constant (~ 25), and the capability of room-temperature process. Since they have high-capacitance due to high dielectric constant, it can be easily expected to result in high on-current. In this work, we demonstrated the comparison of oxide thin film transistors with HfO₂, ZrO₂ and SiO₂ and the roles of gate insulators are analyzed. In the result, oxide thin film transistors with SiO₂, HfO₂ and ZrO₂ have on-currents of ~100 μA, ~500 μA, and ~3 mA, respectively. Especially oxide thin film transistor with ZrO₂ has larger on-current than oxide thin film transistor with HfO₂. The result means that ZrO₂ is more suitable than HfO₂ for the gate-dielectric material which can be fabricated at room temperature.     

Electrical stability in self-aligned p-channel polysilicon thin film transistors

In this work we present a study of the electrical stability of self-aligned p-channel thin film transitor fabricated using excimer laser annealing. The electrical stability was tested performing different bias-temperature stress experiments and we found an increased degradation in devices with large channel width and also for increasing temperatures in the bias-temperature stress performed at zero drain voltage. These results clearly point out to instabilities related to self-heating effects of the devices, showing a substantial increase of the threshold voltage and degradation of the subthreshold region, as well as a transconductance (G_m) increase. From extensive analysis of the phenomenon through numerical simulations, we found that the bias-temperature-stress effects, including G_m overshoot, could be perfectly reproduced assuming that degradation is confined in a narrow channel region near the source and/or drain contacts. From the present results we conclude that self-heating triggers some degradation of a spatially limited region of the channel, presumably related to residual damage of the ion-implantation process.     

Determination of bulk and interface density of states in polycrystalline silicon thin film transistors

The aim of our investigation is to determine the bulk and interface density of states in excimer laser annealed polycrystalline silicon thin film transistors (polysilicon TFTs). The exponential energy distribution of the band tail states in the bulk of the polysilicon layer is obtained from analysis of the space charge limited current in n⁺-i-n⁺ structures. The density of traps at the gate oxide/polysilicon interface and the slope of the exponential band tail states in a thin layer adjacent to the channel/gate oxide interface are extracted from low-frequency noise measurements. The experimental results indicate that the degree of disorder is improved in the upper part of the polysilicon layer due to its columnar growth.     

Properties of n-type ZnN thin films as channel for transparent thin film transistors

In this work we fabricated, by rf magnetron sputtering from a ZnN target, zinc nitride thin films and examined their properties in order to be used as channel layer in thin film transistors. The films were deposited at 100 W rf power and the Ar pressure was 5 mTorr. The zinc nitride thin films were n-type, and depending on the thickness they exhibited low resistivity (10-10^− 2 Ohm?cm), high carrier concentration (10¹⁸-10²⁰ cm^− 3) and very low transmittance values due to the excess zinc in their structure. After annealing at 300 °C, in flowing nitrogen, the films became more conductive, but annealing at higher temperatures deteriorated the electrical properties and became transparent. Transparent thin film transistor having zinc nitride as channel layer exhibited promising transistor characteristics after nitrogen annealing. Improvements in output transistor characteristics due to both material (zinc nitride) and transistor optimization are addressed.     

Influence of process steps on the performance of microcrystalline silicon thin film transistors

Bottom gate microcrystalline silicon thin film transistors (μc-Si TFT) have been realized with two types of films: μc-Si(1) and μc-Si(2) with crystalline fraction of 80% and close to 100% respectively. On these TFTs we applied two types of passivation (SiN_x and resist). μc-Si TFTs with resist as a passivation layer present a low leakage current of about 2.10^− 12 A for V_G = − 10 and V_D = 0.1V an ON to OFF current ratio of 10⁶, a threshold voltage of 7 V, a linear mobility of 0.1 cm²/V s, and a sub-threshold voltage of 0.9 V/dec. Microcrystalline silicon TFTs with SiN_x as a passivation present a new phenomenon: a parasitic current for negative gate voltage (− 15 V) causes a bump and changes the shape of the sub-threshold region. This excess current can be explained by and oxygen contamination at the back interface.     

Multi-material gate poly-crystalline thin film transistors: Modeling and simulation for an improved gate transport efficiency

In this work, a two-dimensional potential distribution formulation is presented for multi-material gate poly-crystalline silicon thin film transistors. The developed formulation incorporates the effects due to traps and grain-boundaries. In short-channel devices, short-channel effects and drain-induced barrier lowering (DIBL) effect exists, and are accounted for in the analysis. The work aims at the reduction of DIBL effect and grain-boundary effects i.e. to reduce the potential barriers generated in the channel by employing gate-engineered structures. A study of work-functions and electrode lengths of multi-material gate electrode is done to suppress the potential barriers, hot electron effect and to improve the carrier transport efficiency. Green's function approach is adopted for the two-dimensional potential solution. The results obtained show a good agreement with simulated results, thus, demonstrating the validity of our model.     

Hydrogenation of nanocrystalline Si thin film transistors employing inductively coupled plasma chemical vapor deposition for flexible electronics

We have investigated the plasma hydrogenation effect on a nanocrystalline silicon (nc-Si) thin film transistor (TFT) fabricated by inductively coupled plasma chemical vapor deposition (ICP-CVD) at 150 °C. The top-gate nc-Si TFT showed a mobility of ∼ 6 cm²/Vs and V_th of 8 V. The hydrogenation employing ICP-CVD was performed at 100 °C for 4 min in order to improve the characteristics of nc-Si TFT. The mobility was increased from ∼ 6 cm²/Vs to 11 cm²/Vs. The V_th of the nc-Si TFTs was decreased to about 6.8 V from 8.1 V. The on-current at the saturation regime also increased by 66% while the off current was increased slightly. The improvement of mobility, threshold voltage and on-current can be attributed to the hydrogen passivation of the Si dangling bonds in the nc-Si film. The experimental results showed that the 100 °C ICP-CVD hydrogenation is effective to improve the 150 °C nc-Si TFT.     

A new method for the determination of the channel length reduction in polysilicon thin film transistors (TFTs)

The accurate knowledge of the effective channel length in a polysilicon thin film transistor (TFT) is of great importance. The reduction ΔL of the channel length is due to lateral diffusion from the source and drain contacts into the gate region. The usual method for determining ΔL is based on plotting the straight line 1/I_D versus length mask L_m in the linear region and extrapolating the straight line to intersect the x-axis. We show that this method is approximate and leads to an underestimation of the reduction channel length due to the existence of the access resistance. We propose an alternative method based on the saturation current I_Dsat using the 1/I_Dsat versus L_m plots. We show that this method is more accurate especially when the access resistance of the device is important. The extracted parameters ΔL for n- and p-channel polysilicon TFTs are more compatible with the device performance.     

Effects of additive hydrogen gas on the instability due to air exposure in ZnO-based thin film transistors

The effect of adding hydrogen gas (H₂) when depositing a zinc oxide (ZnO) thin film in a thin film transistor (TFT) using the ZnO as the channel layer on the electrical characteristics of the ZnO-TFTs, particularly the change in the characteristics according to long-term exposure to air, was investigated. As the amount of added H₂ gas was increased, the resistivity of ZnO films was monotonously decreased and their crystallinity was weakened. Compared with the TFT using a ZnO without H₂ addition, the threshold voltage (V_th) decreased and the on/off current ratio (I_on/I_off) greatly increased, if the amount of H₂ entry was small (≤ 0.3 sccm). However, when an excessive (≥ 0.5 sccm) amount of H₂ was added, the TFT's properties deteriorated. In addition, the ZnO TFTs showed a positive V_th-shift with increased air exposure time. The analysis using the X-ray photoelectron spectroscopy (XPS) confirmed that this was attributed to the reduction of oxygen vacancies due to air exposure. It was noticed that the TFTs that were manufactured using ZnO films with H₂ addition showed significant suppression of the V_th-shift according to air exposure.     

Numerical modelling of impact rupture in polysilicon microsystems

A 2D geometrical model for polycrystals was developed in this paper by means of a Voronoi tessellation in which each crystal is assumed to be elastic anisotropic. An implicit–explicit FE dynamic code coupled with an automatic procedure for the introduction of cohesive interface elements with cohesive traction-jump softening laws was used in order to simulate intergranular and transgranular fracture. Accidental drop simulations were performed with the principal aim to capture the maximum acceleration and to simulate local rupture phenomena in MEMS. In order to reduce the excessive problem size, a simplified, decoupled global–local three level multi-scale approach was used.     

声学仿真软件在噪声预测和评价中的应用

本文对声学仿真软件RAYNOISE的功能、结构及特点作了简单介绍。并对其在环境噪声及车间噪声预测中的应用作了探讨，可以看出RAYNOISE仿真软件在环境噪声预测，室内噪声预测，建声设计，电声设计方面都有广泛的应用。     

I-V and low frequency noise characterization of poly and amorphous silicon Ti- and Co-salicide resistors

Accurate characterization of polysilicon resistors can help in the design and the fabrication of deep-sub-micron CMOS technologies. In this paper we have studied poly and amorphous silicon Ti- and Co-salicide resistors. In order to discriminate between contact and bulk material contribution transmission line model (TLM) test structures are well adapted for both current-voltage (I-V) and low frequency noise (LFN) characterization. Measurements are undertaken as a function of the geometry (inter-electrode length and electrode width) and of the bias current.From I-V measurements sheet resistance of the different bulk materials (poly or amorphous silicon) and contact resistances of the two different processes (TiSi₂ or CoSi₂) are extracted.Experimentally noise voltage spectral density is measured and converted in resistance spectral density. Noise spectra were always fitted with a 1/f component and white noise. Then, like for I-V characterization (i.e. analyzing the noise of different sample lengths), the contact and bulk 1/f noise contribution is extracted. When contact noise is found to be negligible, bulk material noise is directly modelled according to Hooge relation; otherwise we can only estimate the bulk material. Then the normalised α parameter is used to compare material quality.     

Application of fluorine doped oxide (SiOF) spacers for improving reliability in low temperature polycrystalline thin film transistors

The novel process of self-aligned fluorine doped oxide (SiOF) spacers on low temperature poly-Si (LTPS) lightly doped drain (LDD) thin film transistors (TFTs) is proposed. A fluorine doped oxide spacers were provided to generate the lower dissociation Si-F bonds adjusted to the interface of the drain which is the largest lateral electric field region for lightly doped drain structure. The stronger Si-F bonds can reduce the bonds broken by impact ionization. It is found that the output characteristics of SiOF spacers TFTs show the superior immunity to kink effect. The degradations in Vth shifting, subthreshold slope, drain current and transconductance of SiOF spacers after DC stress are improved.     

土木工程下击暴流风速数值模拟的研究

雷暴天气下击暴流之类的高强风对诸如输电塔这样的晶格状结构具有很大的破坏性。因此,建立可靠合理的下击暴流风速模型来分析这些结构在这种极端风荷载作用下的动力响应是很有必要的。通过运用一些时频分析工具可以发现:下击暴流风速表现出明显的非平稳性。而且,下击暴流非平稳风速时程可以分解为随时间变化的平均风速即时变平均风速与具有一定相关性的随机脉动成分。基于Holmes平均风速模型和Vicroy风速竖向分布模型,使用Deo-datis提出的均匀调制非平稳随机场的模拟方法,数值模拟了雷暴天气下击暴流行进路线上某一固定位置处的竖向分布风速场。在随机脉动成分的数值模拟过程中,引入了三次样条函数插值技术,以减少Cholesky分解的次数,进一步提高了数值模拟雷暴天气下击暴流风速的效率。