三维闪存中基于钨互连的空气隙结构的制备工艺

将空气隙应用于逻辑器件后段金属互连线中可以有效降低互连线间的寄生电容,提升电路信号传输速度,但制备过程仍具有一定的困难。基于三维闪存(3D NAND)中后段(BEOL)W的自对准双重图形化(SADP)工艺,利用湿法刻蚀的方法在W化学机械平坦化(CMP)之后去除SiO_2介质层,然后再利用化学气相淀积(CVD)法淀积一层台阶覆盖率较低的介质在金属互连线层内形成空气隙。采用空气隙结构代替原来的SiO_2介质层可降低约37.4%的寄生电容,且薄膜的台阶覆盖率会进一步降低电容。TCAD仿真和电性能测试结果表明,采用该方法制备的空气隙结构可降低互连延迟。     

Air-Gaps for High-Performance On-Chip Interconnect Part II: Modeling, Fabrication, and Characterization

Air-gaps are the ultimate low-k material in microelectronics due to air having a low dielectric constant close to 1.0. The interconnect capacitance can further be reduced by extending the air-gaps into the interlayer dielectric region to reduce the fringing electric field. An electrostatic model (200 nm half-pitch interconnect with an aspect ratio of 2.0), was used to evaluate the dielectric properties of the air-gap structures. The incorporation of air-gaps into the intrametal dielectric region reduced the capacitance by 39% compared with SiO₂. Extending the air-gap 100 nm into the top and bottom interlayer SiO₂ region lowered the capacitance by 49%. The ability to fabricate air-gaps and ‹extended air-gaps’ was demonstrated, and the capacitance decrease was experimentally verified. Cu/air-gap and extended Cu/air-gap interconnect structures were fabricated using high-modulus tetracyclododecene (TD)-based sacrificial polymer. The aspect ratio of the air-gap was 1.8 and the air-gap was extended 80 nm and 100 nm into the top and bottom interlevel SiO₂ region, respectively. The measured effective dielectric constant (k _eff) of the Cu/air-gap and the extended Cu/air-gap structures with SiO₂ interlevel dielectric was 2.42 and 2.17, respectively. The effect of moisture uptake within the extended Cu/air-gap structure was investigated. As the relative humidity increased from 4% to 92%, the k _eff increased by 7%. Hexamethyldisilazane was used to remove adsorbed moisture and create a hydrophobic termination within the air-cavities, which lowered the effect of humidity on the k _eff. A dual Damascene air-gap and extended air-gap fabrication processes were proposed and the challenges of using a sacrificial polymer placeholder approach to form air-cavities are compared to other integration approaches of dual Damascene air-gap.     

空气隙Cu互连结构热应力史研究

将空气引入Cu导线间形成空气隙,可有效降低等效介电常数K_(eff),但同时也使互连结构的机械稳定性面临着挑战。利用ANSYS进行了有限元热分析,研究了制备空气隙Cu互连结构的两种主流工艺过程,即CVD沉积法和热分解牺牲层法,模拟了Cu导线上的热应力变化趋势,并比较了两者的优劣,最终发现互连结构经过一系列热应力的循环作用后,各种材料在不同程度上都有较大的形变,这将影响结构的机械稳定性,甚至引起破坏。所以,需要进一步改善结构设计和使用理想电介质。     

铜互连结构热应力分析及介电材料选择优化

基于Ansys有限元软件,采用三级子模型技术对多层铜互连结构芯片进行了三维建模。研究了10层铜互连结构总体互连线介电材料的弹性模量和热膨胀系数对铜互连结构热应力的影响,在此基础上对总体互连线介电材料的选择进行优化。结果表明,总体互连线介电材料的热膨胀系数对铜互连结构的热应力影响较小,而弹性模量对其影响较大;各层介电材料热应力与弹性模量成正比,SiN界面热应力与弹性模量成反比。最后,为了降低铜互连结构关键位置热应力,通过选用不同参数材料组合对总体互连线介电材料的选取进行优化,提高了铜互连结构可靠性。     

Air-gaps in 0.3 /spl mu/m electrical interconnections

A copper/air-gap interconnection structure using a sacrificial polymer and SiO/sub 2/ in a damascene process has been demonstrated. The air-gap occupies the entire intralevel volume with fully densified SiO/sub 2/ as the planar interlevel dielectric. The copper was deposited by physical vapor deposition and planarized by chemical-mechanical planarization. The Ta/Cu barrier/seed layer was deposited by physical vapor deposition; the bulk copper was electrochemically deposited. The resulting structure has an effective intralevel dielectric constant of 2.19.     

Effect of NH3-plasma treatment and CMP modification onTDDB improvement in Cu metallization

Time-dependent dielectric breakdown (TDDB) between Cu interconnects is investigated. TDDB lifetime strongly depends on the surface condition of the Cu interconnect and surrounding pTEOS. A NH₃-plasma treatment prior to cap-pSiN deposition on Cu interconnect improved the dielectric breakdown lifetime (T_BD) over cap-pSiN deposition only. The plasma treatment also has the beneficial effect of suppressing wiring resistance increase during pSiN deposition. These results suggest that CuO reduction to Cu, and CuN formation at the Cu interconnect surface prevents Cu silicidation during pSiN deposition. Furthermore, SiN formation and bond termination by hydrogen radicals at the pTEOS surface diminish surface defects such as dangling bonds. TDDB lifetime also strongly depends on the Cu CMP process, in which mechanical damage of the SiO₂ surface during CMP process degrades TDDB. Adoption of a mechanical damage free slurry or a post-CMP HF treatment to remove the damaged layer from the surface improves TDDB     

Air-gap formation during IMD deposition to lower interconnectcapacitance

The use of air-gaps between interconnect metal lines to reduce interconnect capacitance has been explored. Simulations were performed to determine the reduction in capacitance obtainable using air-gaps. The formation of air-gaps in the isolation oxide between metal lines was simulated using Stanford Profile Emulator for Etching and Deposition in IC Engineering (SPEEDIE). The capacitance of the SPEEDIE profiles was then extracted using Raphael (an electrical analysis simulator from TMA). The feasibility of air-gaps was also demonstrated experimentally. Fabricated air-gap structures exhibited a 40% reduction in capacitance when compared to a HDP-CVD oxide gap-fill process with K=4.1. Additionally, the air-gap structures did not exhibit any appreciable leakage current     

A Model for Understanding Electromigration-Induced Void Evolution in Dual-Inlaid Cu Interconnect Structures

Electromigration-induced void evolution in various dual-inlaid copper (Cu) interconnect structures was simulated by applying a phenomenological model assisted by Monte Carlo-based simulations, considering the redistribution of heterogeneously nucleated voids and/or pre-existing vacancy clusters at the Cu/dielectric cap interface during electromigration. The results indicate that this model can qualitatively explain the electromigration-induced void evolution observed during experimental in situ secondary-electron microscopy (SEM) investigations as well as in various other reported studies. The electromigration mechanism in Cu interconnect structures and differences in the peculiar electromigration-induced void evolution in various dual-inlaid Cu interconnect structures can be clearly understood based on this model. These findings warrant reinvestigation of technologically important electromigration mechanisms by developing rigorous models based on similar concepts.     

Dielectric deposition process for Cu/SiO2 integration in a dual damascene interconnection architecture

A challenge to integrate Cu in device interconnections is to avoid Cu diffusion into silicon active zone that could seriously damage device performance, and into interlevel dielectric that could induce shorts or degrade dielectric performance. This paper relates the integration of Cu-CVD with SiO₂. Structures studied are SiO₂ deposited on Cu-CVD, and SiO₂/SiN/Cu structure: a thin SiN layer is deposited on Cu before SiO₂ to act as diffusion barrier and as an etch stop during the interconnect structure patterning. Both SiO₂ and SiN dielectric processes are made in plasma-enhanced chemical vapor deposition processes, from SiH₄ precursor with addition of, respectively, N₂O or NH₃. Cu contamination is shown to occur during the dielectric deposition onto Cu, and is enhanced by the fluorine presence in the deposition chamber. Deposition processes were evaluated in order to lower Cu contamination in the dielectric bulk. On an other hand, a noticeable degradation in Cu layer resistance was evidenced after dielectric deposition due to copper contamination during the dielectric deposition process. This issue can be addressed by the optimization of the dielectric deposition process.     

A novel sub-half micron Al-Cu via plug interconnect using lowdielectric constant material as inter-level dielectric

A novel Al-Cu via plug interconnect using low dielectric constant (low-ϵ) material as inter-level dielectric (ILD) has been demonstrated. The interconnect structure was fabricated by spin-on deposition of the low-ϵ ILD and physical vapor deposition (PVD) of the Al-Cu. Excellent local ILD planarization was achieved by a two-step spin-on coating process. The dielectric constant of the low-ϵ no is about 2.7, which leads to significant interconnect wiring capacitance reduction. For the first time, completely filled Al-Cu:0.5% plugs with nearly vertical sidewalls were fabricated in organic low-ϵ ILD. Excellent via fill was observed with via size down to 0.30 μm. Low via resistance and excellent via reliability have been observed     

Effects of plasma treatment on the high frequency characteristics of Cu/Ta/hydrogen silsesquioxane (HSQ) system and electrical behaviors of Cu/Ta/HSQ/Pt MIM capacitors

With the increasing of the operating frequencies, insertion loss, signal propagation delay, and parasitic coupling capacitance become the significant problems. Small capacitance (C) between interconnects is required to reduce the crosstalk, insertion loss, and RC delay associated with the metal interconnect system. Therefore, the interconnect with low dielectric constant (k) material is required. Implementation of Cu/low-k dielectric is used for reducing insertion loss, RC delay, crosstalk noises, etc. In this work, Cu-hydrogen silsesquioxane (HSQ) systems are studied. Ammonia (NH₃) plasma is employed for the nitridation of HSQ. The effects of NH₃ plasma treatments on the high frequency characteristics (100 MHz to 20 GHz) of the interconnect structure Cu/Ta/HSQ and electrical behaviors of Cu/Ta/HSQ/Pt MIM capacitors are evaluated.Auger electron spectroscopy (AES) results suggest the diffusion of oxygen and copper atoms during copper annealing. This raises resistance of Cu interconnect and increases the conductance of the HSQ films. Hence, 400 °C-annealed Cu/Ta/HSQ interconnect systems become lossy at high frequencies (>2 GHz). Ammonia (NH₃) plasma bombardments break some of the Si-H bonds and the resulting dangling Si bonds increase the moisture absorption. Meanwhile, NH₃ plasma treatments reduce the leakage current by passivating the Si dangling bond and forming silicon nitride. The absorption of moisture and/or the formation of SiN_x result in high dielectric constant of HSQ after prolonged NH₃ plasma bombardment. The dielectric constant of HSQ decreases and then increases with the increase of NH₃ plasma treatment time and a minimum dielectric constant of 2.2 is obtained after 50 s NH₃ plasma treatment at 200 W. Among various specimens in this study, the smallest insertion loss is 1.97 dB/mm at 20 GHz for the 400°C-annealed Cu/Ta/HSQ (NH₃-plasma-treated for 50 s). Appropriate NH₃-plasma bombardment helps to form a thin SiN_x barrier layer which prevents the diffusion of oxygen without increasing the dielectric constant of the Cu-HSQ interconnect system. The leakage currents versus electric field characteristics suggest that a Schottky emission dominate conduction mechanism.     

Electromigration and integration aspects for the copper-SiLK system

In this study, the thermal characteristics and electromigration (EM) resistance of two dielectrics, SiLK™ and SiO₂, are investigated to evaluate the feasibility of low dielectric-constant SiLK for intermetal dielectric applications. Liftoff patterning was employed to fabricate the Cu interconnect for the EM test, and the Taguchi method was used in the experimental design to identify the key parameters for a successful liftoff. It was shown that the thermal impedance of the metal lines passivated with SiLK is 14% higher than that of metal lines passivated with SiO₂. On the basis of the thermal impedance and temperature rise of the interconnect, it was concluded that the major heat transfer path is via the underlayer dielectric to the Si substrate. The activation energy of EM for Cu passivated with SiLK is smaller, and the EM lifetime is shorter than that of Cu passivated with SiO₂. Possible mechanisms are discussed.     

Electrochemical aspects of new materials and technologies in microelectronics

Major scaling issues, which need to be addressed to continue scaling according to Moore’s law, include increase of transistor leakage due to use of thin gate oxide (about 1 nm limit for SiO₂), power (reaching 100 W/cm²) and RC delay (dielectric constant limit is 1 for air and Cu resistivity increases with scaling down the feature sizes). Integration of new materials and technologies will allow us to continue scaling and improve device performance. Examples of new materials include high-k dielectrics and strained silicon in the frond end of wafer processing, low-k carbon-doped oxide and electroplated copper in the back end of wafer processing as well as electroplated bumps, high thermal conductivity interface, heat sink and heat spreader materials in packaging. Electrochemical technologies will play an increasingly important role in silicon technology due to low cost, use of self-assembly processing and self-aligned growth ability. New electrochemical technologies in silicon processing include copper electroplating (replaced Al interconnect to reduce RC delay and increase reliability), bump electroplating (replaced wire bonding to allow increased I/O and improve reliability), and porous silicon for silicon on isolator fabrication (to reduce transistor leakage). Copper electroplating allows a low R, an excellent gap fill capability and superior materials properties with (111) textured Cu films and large grain size, and a stable and controlled process.     

Electron fluence driven,Cu catalyzed,interface breakdown mechanism for BEOL low-k time dependent dielectric breakdown

During technology development, the study of low-k time dependent dielectric breakdown (TDDB) is important for assuring robust chip reliability. It has been proposed that the fundamentals of low-k TDDB are closely correlated with the leakage conduction mechanism of low-k dielectrics. In addition, low-k breakdown could also be catalyzed by Cu migration occurring mostly at the interface between capping layer and low-k dielectrics. In this paper, we first discuss several important experimental results including leakage modulation by changing the capping layer without changing the electric field, TDDB modulation by Cu-free and liner-free interconnect builds, 3D on-flight stress-induced leakage current (SILC) measurement, and triangular voltage sweep (TVS) versus TDDB to confirm the proposed electron fluence driven, Cu catalyzed interface low-k breakdown model. Then we review several other low-k TDDB models that consider only intrinsic low-k breakdown, especially the impact damage model. Experimental attempts on validation of various dielectric reliability models are discussed. Finally, we propose that low-k breakdown seems to be controlled by a complicated competing breakdown process from both intrinsic electron fluence and extrinsic Cu migration during bias and temperature stress. It is hypothesized that the amount of Cu migration during TDDB stress strongly depends on process integration. The different roles of Cu in low-k breakdown could take different dominating effects at different voltages and temperatures. A great care must be taken in evaluating low-k dielectric TDDB as its ultimate breakdown kinetics could be strongly dependent on interconnect space, process, material, stress field, and stress temperature.     

Integration and characterization of gas cluster processing for copper interconnects electromigration improvement

Basic physical properties as well as electrical and reliability performance of Infusion™ processing were evaluated. This approach, proposed as an alternative to CuSiN and electrolessly deposited Co-alloys, was shown to join the benefits of these two techniques without well-known associated drawbacks. Indeed, it is a uniform process, acting as an efficient Cu diffusion barrier, which does not require specific integration development. Different processes were introduced in a multi-level interconnect stack using ULK/USG stack as IMD, showing excellent electrical properties, and three times electromigration time-to-failure improvement with respect to standard SiCN barrier. However, it was shown that existing process conditions lead to some introduction of N atoms into ULK dielectric, showing there is still some room for process optimization in architectures using un-capped ULKs, to keep the benefits of EM improvement and aggressive effective dielectric constant.     

具有冗余设计的铜互连线电迁移可靠性评估

铜互连的电迁移可靠性与晶粒结构、几何结构、制造工艺以及介质材料等因素有着密切的关系。分别试制了末端有一定延伸的互连线冗余结构设计的样品,以及无冗余结构的互连线样品,并对样品进行了失效加速测试。测试结果显示,采用冗余结构设计的互连线失效时间更长,具有更好的抗电迁移可靠性。对冗余结构的失效模式进行了讨论,并结合互连线的制造工艺,指出采用冗余结构设计的互连线可以在有效改善互连线的电迁移特性,而且不会引入其他影响可靠性的因素,是一种有效提高铜互连电迁移可靠性的方法。     

Selective electroless copper for VLSI interconnection

Cu is studied as a candidate for low-resistance VLSI interconnection. Simulation studies show that for effective channel length less than 0.5 μm, the RC time constant of interconnection is a major part of the total delay. By reducing the resistivity of the interconnect, the operating speed can be increased by more than 20% without any change in design rule. A selective electroless deposition process was used to solve the Cu patterning difficulty. Patterns of 2.2-μm pitch have been achieved with this process. The copper contamination issue is also studied; dielectric films such as silicon oxynitride and silicon nitride are shown to be effective in stopping Cu diffusion. By coating a thin Ni film on Cu, Cu corrosion can be reduced from 0.2 μ/h to less than 0.05 μm/h at 100°C in 4% KCL solution     

Effect of in-line electron beam treatment on the electrical performance of Cu/organic low-k damascene interconnects

The interface quality and reliability issues have shown significant importance in Cu/organic low-k damascene integration. In this letter, a post-etch in-line electron beam (E-beam) treatment was used to modify the interface properties of sidewall barrier/organic low-k dielectric without impairing either the film properties or the dielectric constant. X-ray photoelectron spectroscopy (XPS) analysis indicated that oxygen content at the low-k surface, which mostly came from oxygen/moisture intake from ambient during process, was eliminated by E-beam exposure and subsequent rapid thermal annealing. As a result, Cu/organic low-k interconnects exhibited a lower line-to-line leakage current and a higher breakdown strength. The interconnect structures, after this in-line E-beam treatment process, also showed a good reliability performance against thermal stress, with good leakage current characteristics after a 500-h burn-in at 200/spl deg/C.     

Copper interconnect electromigration behaviors in various structures and lifetime improvement by cap/dielectric interface treatment

Copper interconnect electromigration performance was examined in various structures and three low-k materials (k = 2.65–3.6) using advanced BEOL technology. Strong current dependence effect on electromigration lifetime in three levels via terminated metal lines structure was shown. Moreover, different process approach will lead to different EM behavior and related failure mode. Multi-modality electromigration behavior of Cu dual damascene interconnects were studied. Both Superposition and Weak-Link models were used for statistical determination of lifetimes of each failure models (Statistical method). Results were correlated to the lifetimes of respective failure models physically identified according to resistance time evolution behaviors (Physical method). Good agreement was achieved. Various testing structures are designed to identify the EM failure modes. Extensive failure analysis was carried out to understand the failure phenomena of various test structures. The activation energies of failure modes were calculated. The weak links of interconnect system were also identified. A significant improvement of electromigration (EM) lifetime is achieved by modification of the pre-clean step before cap-layer deposition and by changing Cu cap/dielectric materials. A possible mechanism for EM lifetime enhancement was proposed. Cu-silicide formation before cap-layer deposition and adhesion of Cu/cap interface were found to be critical factors in controlling Cu electromigration reliability. The adhesion of the Cu/cap interface can be directly correlated to electromigration MTF and activation energy. Results of present study suggest that interface of Cu interconnects is the key factor for EM performance for advanced BEOL technology design rules.     

化学机械抛光技术现状与发展趋势

概述了ITRS对铜互连工艺提出的要求及90～65nmCMP技术所面临的挑战,介绍了W熏STI熏Cu/低k材料CMP及其清洗和终点检测技术的发展现状,最后讨论了CMP技术的一些发展趋势。