A Ka Band Balanced Third LO-Harmonic Mixer Using a Lumped-Elements Quadrature Hybrid

A novel configuration of a subharmonic mixer utilizing third local oscillation (LO) harmonic is presented. The mixer is capable of down-converting a Ka-Band radio frequency (RF) signal with the third harmonic of an X-band LO signal to produce a 2 GHz intermediate frequency signal. It is fabricated on a 4 mil substrate using a 0.15 mum GaAs PHEMT process. A novel quadrature hybrid is realized by using compact lumped elements, and it is beneficial for the reduction of chip size for an LO at a relatively low frequency in this topology. This is because it does not need any bulky via holes. Compared with published subharmonic mixers, it provides a more flexible requirement for an LO source at a relatively low frequency for an overall communication system design. The measured results show that the best conversion loss is about 13.2 dB at a RF frequency of 29 GHz as a 10.5 dBm 9 GHz LO signal is pumped. The chip area of the mixer is less than 3.14 mm².     

Compact 28-GHz subharmonically pumped resistive mixer MMIC using a lumped-element high-pass/band-pass balun

This work reports a novel lump-element balun for use in a miniature monolithic subharmonically pumped resistive mixer (SPRM) microwave monolithic integrated circuit. The proposed balun is simply analogous to the traditional Marchand balun. The coupled transmission lines are replaced by lump elements, significantly reducing the size of the balun. This balun requires no complicated three-dimensional electromagnetic simulations, multilayers or suspended substrate techniques; therefore, the design parameters are easily calculated. A 2.4-GHz balun is demonstrated using printed circuit board technology. The measurements show that the outputs of balun with high-pass and band-pass responses, a 1-dB gain balance, and a 5/spl deg/ phase balance from 1.7 to 2.45 GHz. The balun was then applied in the design of a 28-GHz monolithic SPRM. The measured conversion loss of the mixer was less than 11dB at a radio frequency (RF) bandwidth of 27.5-28.5 GHz at a fixed 1 GHz IF, a local oscillator (LO)-RF isolation of over 35 dB, and a 1-dB compression point higher than 9 dBm. The chip area of the mixer is less than 2.0 mm/sup 2/.     

A 0.7-7 GHz wideband reconfigurable receiver RF front-end in CMOS

In this paper,a 0.7-7 GHz wideband RF receiver front-end SoC is designed using the CMOS process.The front-end is composed of two main blocks:a single-ended wideband low noise amplifier (LNA) and an inphase/quadrature (I/Q) voltage-driven passive mixer with IF amplifiers.Based on a self-biased resistive negative feedback topology,the LNA adopts shunt-peaking inductors and a gate inductor to boost the bandwidth.The passive down-conversion mixer includes two parts:passive switches and IF amplifiers.The measurement results show that the front-end works well at different LO frequencies,and this chip is reconfigurable among 0.7 to 7 GHz by tuning the LO frequency.The measured results under 2.5-GHz LO frequency show that the front-end SoC achieves a maximum conversion gain of 26 dB,a minimum noise figure (NF) of 3.2 dB,with an IF bandwidth of greater than 500 MHz.The chip area is 1.67 × 1.08 mm2.     

26.5–30-GHz Resistive Mixer in 90-nm VLSI SOI CMOS Technology With High Linearity for WLAN

A resistive mixer with high linearity for wireless local area networks is presented in this paper. The fully integrated circuit is fabricated with a 90-nm very large scale integration silicon-on-insulator (SOI) CMOS technology and has a very compact size of 0.38 mm$, times,$0.32 mm. Design guidelines are given to optimize the circuit performance. Analytical calculations and simulations with an SOI large-signal Berkeley simulation model show good agreement with measurements. At an RF of 27 GHz, an IF of 2.5 GHz and zero dc power consumption, a conversion loss of 9.7 dB, a single-sideband noise figure of 11.4 dB, and a high third-order intercept point at the input of 20 dBm are measured at a local-oscillator (LO) power of 10 dBm. At lower LO power of 0-dBm LO power, the loss is 10.3 dB. To the knowledge of the author, the circuit has by far the highest operation frequency reported to date for a resistive CMOS mixer. Furthermore, it provides the highest linearity for a CMOS mixer operating at such high frequencies.     

A Low-Voltage 5-GHz Downconversion Mixer Employing A Second Harmonic Injection Linearization Technique

In this paper, a low-voltage CMOS mixer topology, appropriate for operation in the 5-GHz frequency band, is presented. The mixer combines several design techniques in order to achieve high linearity performance with minimum current consumption in a restricted 1-V supply. The proposed mixer utilizes an integrated transformer to improve the high frequency performance and to achieve large LO to RF isolation. In addition, a novel linearization technique based on second harmonic injection, is introduced to optimize linearity performance. The design is being implemented in a 0.13-mum CMOS technology.     

60 GHz MMIC double balanced Gilbert mixer in mHEMT technology with integrated RF, LO and IF baluns

A 60 GHz MMIC double balanced Gilbert mixer (DBGM) with integrated RF, LO and IF baluns has been designed, fabricated in an mHEMT MMIC technology and characterised with probed measurements. Although a standard mixer topology for integrated circuits in the low gigahertz region, the DBGM has had very little impact in the millimetre-wave range. To the authors' knowledge, the presented DBGM operates at the highest RF frequency ever published for any FET-based Gilbert type mixer, double or single balanced. A measured down conversion gain of 1.5 dB at 60 GHz is obtained with a DC power consumption of 300 mW. Further, IF bandwidth, isolation between the LO, RF and IF ports, 1 dB compression point for the RF input, and LO input power is presented     

Highly integrated 60 GHz transmitter and receiver MMICs in a GaAs pHEMT technology

Highly integrated transmitter and receiver MMICs have been designed in a commercial 0.15 /spl mu/m, 88 GHz f/sub T//183 GHz f/sub MAX/ GaAs pHEMT MMIC process and characterized on both chip and system level. These chips show the highest level of integration yet presented in the 60 GHz band and are true multipurpose front-end designs. The system operates with an LO signal in the range 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO chain, resulting in an IF center frequency of 2.5 GHz. Although the chips are inherently multipurpose designs, they are especially suitable for high-speed wireless data transmission due to their very broadband IF characteristics. The single-chip transmitter MMIC consists of a balanced resistive mixer with an integrated ultra-wideband IF balun, a three-stage power amplifier, and the X8 LO chain. The X8 is a multifunction design by itself consisting of a quadrupler, a feedback amplifier, a doubler, and a buffer amplifier. The transmitter chip delivers 3.7/spl plusmn/1.5 dBm over the RF frequency range of 54-61 GHz with a peak output power of 5.2 dBm at 57 GHz. The single-chip receiver MMIC contains a three-stage low-noise amplifier, an image reject mixer with an integrated ultra-wideband IF hybrid and the same X8 as used in the transmitter chip. The receiver chip has 7.1/spl plusmn/1.5 dB gain between 55 and 63 GHz, more than 20 dB of image rejection ratio between 59.5 and 64.5 GHz, 10.5 dB of noise figure, and -11 dBm of input-referred third-order intercept point (IIP3).     

60 GHz Single-Chip Front-End MMICs and Systems for Multi-Gb/s Wireless Communication

Single-chip 60 GHz transmitter (TX) and receiver (RX) MMICs have been designed and characterized in a 0.15mum (f_T~ 120 GHz/f _MAX> 200 GHz) GaAs mHEMT MMIC process. This paper describes the second generation of single-chip TX and RX MMICs together with work on packaging (e.g., flip-chip) and system measurements. Compared to the first generation of the designs in a commercial pHEMT technology, the MMICs presented in this paper show the same high level of integration but occupy smaller chip area and have higher gain and output power at only half the DC power consumption. The system operates with a LO signal in the range of 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO multiplier chain, resulting in an IF center frequency of 2.5 GHz. Packaging and interconnects are discussed and as an alternative to wire bonding, flip-chip assembly tests are presented and discussed. System measurements are also described where bit error rate (BER) and eye diagrams are measured when the presented TX and RX MMICs transmits and receives a modulated signal. A data rate of 1.5 Gb/s with simple ASK modulation was achieved, restricted by the measurement setup rather than the TX and RX MMICs. These tests indicate that the presented MMICs are especially well suited for transmission and reception of wireless signals at data rates of several Gb/s     

Multifunction silicon MMIC's for frequency conversion applications

The application of advanced silicon bipolar IC technology to multifunction microwave monolithic integrated circuits (MMICs) is demonstrated. The modeling, design, and testing of two silicon MMICs for frequency conversion applications are illustrated. The first product is a wideband frequency doubler with conversion gain, 20-dBc rejection of harmonics, and a 2-GHz bandwidth. The second product is a wideband vector demodulator (or image reject mixer) that utilizes an onchip digital frequency divider to generate 0° and 90° local oscillator (LO) phases from 0.05 to 1.5 GHz. Both products operate from a single 5-V supply, are load insensitive, require no external baluns, and are packaged in 180-mil hermetic packages. These frequency conversion MMICs and others currently under development have been prototyped on the analog silicon transistor array starCHIP-1, which is also described     

A fully integrated 24-GHz eight-element phased-array receiver in silicon

This paper reports the first fully integrated 24-GHz eight-element phased-array receiver in a SiGe BiCMOS technology. The receiver utilizes a heterodyne topology and the signal combining is performed at an IF of 4.8 GHz. The phase-shifting with 4 bits of resolution is realized at the LO port of the first down-conversion mixer. A ring LC voltage-controlled oscillator (VCO) generates 16 different phases of the LO. An integrated 19.2-GHz frequency synthesizer locks the VCO frequency to a 75-MHz external reference. Each signal path achieves a gain of 43 dB, a noise figure of 7.4 dB, and an IIP3 of -11 dBm. The eight-path array achieves an array gain of 61 dB and a peak-to- ratio of 20 dB and improves the signal-to-noise ratio at the output by 9 dB.     

A high-performance W-band uniplanar subharmonic mixer

A uniplanar subharmonic mixer has been implemented in coplanar waveguide (CPW) technology. The circuit is designed to operate at RF frequencies of 92-96 GHz, IF frequencies of 2-4 GHz, and LO frequencies of 45-46 GHz. Total circuit size excluding probe pads and transitions is less than 0.8 mm ×1.5 mm. The measured minimum single-sideband (SSB) conversion loss is 7.0 dB at an RF of 94 GHz, and represents state-of-the-art performance for a planar W-band subharmonic mixer. The mixer is broad-band with a SSB conversion loss of less than 10 dB over the 83-97-GHz measurement band. The measured LO-RF isolation is better than -40 dB for LO frequencies of 45-46 GHz. The double-sideband (DSB) noise temperature measured using the Y-factor method is 725 K at an LO frequency of 45.5 GHz and an IF frequency of 1.4 GHz. The measured data agrees well with the predicted performance using harmonic-balance analysis (HBA). Potential applications are millimeter-wave receivers for smart munition seekers and automotive-collision-avoidance radars     

A subharmonic self-oscillating mixer with integrated antenna for60-GHz wireless applications

A balanced integrated-antenna self-oscillating mixer at 60 GHz is presented in this paper. The modal radiation characteristics of a dual-feed planar quasi-Yagi antenna are used to achieve RF-local oscillator (RF-LO) isolation between closely spaced frequencies. The balanced mixer is symmetric, inherently broad band, and does not need an RF balun. Pseudomorphic high electron-mobility transistors are used in a 30-GHz push-pull circuit to generate the second harmonic and a 30-GHz dielectric resonator was used to stabilize the fundamental oscillation frequency. This allows the possibility of building a balanced low-cost self-contained antenna integrated receiver with low LO leakage for short-range narrow-band communication. Phase locking can be done with half of the RF frequency. The circuit exhibits a conversion loss less than 15 dB from 60 to 61.5 GHz, radiation leakage of -26 dBm at 60 GHz, and IF phase noise of -95 dBc/Hz at 100-kHz offset     

K-Band CMOS Sub-Harmonic Resistive Mixer With a Miniature Marchand Balun on Lossy Silicon Substrate

A K-band sub-harmonically pumped resistive mixer is demonstrated using standard 0.13 mum CMOS technology. A miniature Marchand Balun is integrated with the resistive mixer to generate equal amplitude and out-of-phase signals for mixer's local oscillation (LO) port directly on the lossy silicon substrate. The sub-harmonic resistive mixer with the integrated Marchand balun has conversion loss of 11-12 dB at f_IF = 100 MHz and P_LO = 7 dBm for RF frequencies from 18 to 26 GHz. The LO-RF and LO-IF isolations are approximately 30 and 33 dB, respectively.     

A Q-band monolithic balance resistive HEMT mixer usingCPW/slotline balun

A Q-band balanced, resistive high-electron-mobility-transistor (HEMT) mixer has been developed for integration in monolithic millimeter-wave receivers. The mixer consists of two AlGaAs/GaAs HEMTs, a coplanar-waveguide (CPW)-to-slotline local oscillator (LO) balun, and an active IF balun. CPWs are used to eliminate the backside or via-hole process step, which increases the circuit yield and shortens the processing time. The conversion loss of the mixer while downconverting a 42-46-GHz RF to a 2.3-3.2-GHz IF is between 4 and 8 dB using an LO drive of 14 dBm. A 17.5-dBm input two-tone third-order intermodulation intercept point is achieved with an LO drive of 10.5 dBm, while a 5.5-dBm input, 1-dB compression point can be achieved with an LO drive of 14 dBm. This is the first reported monolithic CPW resistive HEMT mixer operating at Q-band frequencies     

A 23–37 GHz Miniature MMIC Subharmonic Mixer

A novel configuration of subharmonic mixer using an anti-parallel diode pair is presented for operating over the 23-37 GHz band. The monolithic microwave integrated circuit is implemented by GaAs 0.15 mum PHEMT technology with the compact size of 0.85 times 0.85 mm². This mixer employs a directional coupler, LC low-pass filter, and a short stub for isolating three ports corresponding to radio frequency (RF), local oscillation (LO) input, and intermediate frequency (IF) output ports. The directional coupler also provides impedance transformation between the diode pair, RF, and LO ports. This makes the subharmonic mixer more compact and flexible. The best conversion loss of the subharmonic mixer is 9.4 dB, and the LO-to-RF and LO-to-IF isolations are better than 22 and 31 dB, respectively.     

A 210 GHz Dual-Gate FET Mixer MMIC With ${>}$2 dB Conversion Gain, High LO-to-RF Isolation, and Low LO-Drive Requirements

We demonstrate the first active mixer monolithic microwave integrated circuit (MMIC) with positive conversion gain beyond 200 GHz. The presented dual-gate topology is realized in a 100 nm gate length metamorphic high electron mobility transistor technology. Without any pre- or post-amplification, the down-conversion mixer achieves $>$ 2 dB conversion gain and $>$16 dB local oscillation to radio frequency (LO-to-RF) isolation at 210 GHz, outperforming state-of-the-art resistive MMIC mixers. The conversion gain becomes positive for LO power levels larger than 0 dBm, making the mixer suitable for being driven by an MMIC-based frequency doubler. A comparison to state-of-the-art G-band mixers is given.      

A 60-GHz uniplanar MMIC 4/spl times/ subharmonic mixer

A uniplanar GaAs monolithic microwave integrated circuit /spl times/4 subharmonic mixer (SHM) has been fabricated for 60-GHz-band applications using an antiparallel diode pair in finite ground coplanar (FGC) waveguide technology. This mixer is designed to operate at an RF of 58.5-60.5 GHz, an IF of 1.5-2.5 GHz, and an LO frequency of 14-14.5 GHz. FGC transmission-line structures used in the mixer implementation were fully characterized using full-wave electromagnetic simulations and on-wafer measurements. Of several mixer configurations tested, the best results show a maximum conversion loss of 13.2 dB over the specified frequency range with a minimum local-oscillator power of 3 dBm. The minimum upper sideband conversion loss is 11.3 dB at an RF of 58.5 GHz and an IF of 2.5 GHz. This represents excellent performance for a 4/spl times/ SHM operating at 60 GHz.     

An I/Q mixer with an integrated differential quadrature all-pass filter for on-chip quadrature LO signal generation

A down-conversion in-phase/quadrature (I/Q) mixer employing a folded-type topology, integrated with a passive differential quadrature all-pass filter (D-QAF), in order to realize the final down-conversion stage of a 60 GHz receiver architecture is presented in this work. Instead of employing conventional quadrature generation techniques such as a polyphase filter or a frequency divider for the local oscillator (LO) of the mixer, a passive D-QAF structure is employed. Fabricated in a 65 nm CMOS process, the mixer exhibits a voltage gain of 7-8 dB in an intermediate frequency (IF) band ranging from 10 MHz-1.75 GHz. A fixed LO frequency of 12 GHz is used to down-convert a radio frequency (RF) band of 10.25-13.75 GHz. The mixer displays a third order input referred intercept point (IIP₃) ranging from -8.75 to -7.37 dBm for a fixed IF frequency of 10 MHz and a minimum single-sideband noise figure (SSB-NF) of 11.3 dB. The mixer draws a current of 6 mA from a 1.2 V supply voltage dissipating a power of 7.2 mW.     

Fully integrated 60-GHz single-ended resistive mixer in 90-nm CMOS technology

This letter presents the design and characterization of a fully integrated 60-GHz single-ended resistive mixer in a 90-nm CMOS technology. A conversion loss of 11.6dB, 1-dB compression point of 6dBm and IIP3 of 16.5dBm were measured with a local oscillator (LO) power of 4dBm and zero drain bias. The possibility of improvement in IIP3 with selective drain bias has been verified. A 3-dB improvement in IIP3 was obtained with 150-mV dc voltage applied at the drain. Microstrip transmission lines are used to realize matching and filtering at LO and radio frequency ports.     

A 10–35 GHz Low Power Bulk-DrivenMixer Using 0.13 $mu$m CMOS Process

10-35 GHz doubly balanced mixer using a 0.13-mum CMOS foundry process is presented in this letter. Using the bulk-driven topology, the number of transistors of the doubly balanced mixer is reduced; thus the mixer can achieve a low supply voltage and low power consumption. This bulk-driven mixer exhibits a measured conversion gain of -1 plusmn 2 dB from 10 to 35 GHz of radio frequency (RF) with a fixed intermediate frequency (IF) of 100 MHz. The measured local oscillation (LO) to IF and RF-IF isolations are better than 30 dB. The chip area of the mixer is 0.6 times 0.4 mm². The total power consumption included output buffer is only 6 mW.