Sub-1/4-μm dual-gate CMOS technology using in-situ dopedpolysilicon for nMOS and pMOS gates

A new dual poly-Si gate CMOS fabrication process is proposed. The incorporated technology features a boron-penetration-resistant MBN gate structure for pMOSFET's, and a dual poly-Si gate CMOS process involving separate depositions of in-situ doped n⁺ and p⁺ poly-Si for the nMOS and pMOS gates, 0.2-μm CMOS devices with 3.5-nm gate oxide have been successfully fabricated. The advantages of the new process are demonstrated on these test devices. A CMOS 1/16 dynamic frequency divider fabricated by the new process functions properly up to 5.78 GHz at a 2-V supply voltage     

Co-integration of GaAs MESFET and Si CMOS circuits

Co-integration of GaAs MESFET and Si CMOS circuits is demonstrated using GaAs-on-Si epitaxial growth on prefabricated Si wafers. This is thought to be the first report of circuit-level integration of the two types of devices in a coplanar structure. A 2-μm gate Si CMOS ring oscillator has shown a minimum delay of 570 ps/gate, whereas on the same wafer a 1-μm gate GaAs MESFET buffered-FET-logic (BFL) ring oscillator has a minimum delay of only 70 ps/gate. A composite ring oscillator consisting of Si CMOS invertors and GaAs MESFET invertors connected in a ring has been successfully fabricated     

A low-resistance self-aligned T-shaped gate for high-performancesub-0.1-μm CMOS

This paper describes the high performance of T-shaped-gate CMOS devices with effective channel lengths in the sub-0.1-μm region. These devices were fabricated by using selective W growth, which allows low-resistance gates smaller than 0.1 μm to be made without requiring fine lithography alignment. We used counter-doping to scale down the threshold voltage while still maintaining acceptable short-channel effects. This approach allowed us to make ring oscillators with a gate-delay time as short as 21 ps at 2 V with a gate length of 0.15 μm. Furthermore, we experimentally show that the high circuit speed of a sub-0.1-μm gate length CMOS device is mainly due to the PMOS device performance, especially in terms of its drivability     

Cutoff frequency and propagation delay time of 1.5-nm gate oxideCMOS

The high-frequency AC characteristics of 1.5-nm direct-tunneling gate SiO₂ CMOS are described. Very high cutoff frequencies of 170 GHz and 235 GHz were obtained for 0.08-μm and 0.06-μm gate length nMOSFETs at room temperature. Cutoff frequency of 65 GHz was obtained for 0.15-μm gate length pMOSFETs using 1.5-nm gate SiO₂ for the first time. The normal oscillations of the 1.5-nm gate SiO₂ CMOS ring oscillators were also confirmed. In addition, this paper investigates the cutoff frequency and propagation delay time in recent small-geometry CMOS and discusses the effect of gate oxide thinning. The importance of reducing the gate oxide thickness in the direct-tunneling regime is discussed for sub-0.1-μm gate length CMOS in terms of high-frequency, high-speed operation     

Ultrafast operation of Vth-adjustedp+-n+ double-gate SOI MOSFET's

To optimize the V_th of double-gate SOI MOSFET's, we fabricated devices with p⁺ poly-Si for the front-gate electrode and n⁺ poly-Si for the back-gate electrode on 40-nm-thick direct-bonded SOI wafers. We obtained an experimental V_th of 0.17 V for nMOS and -0.24 V for pMOS devices. These double-gate devices have good short-channel characteristics, low parasitic resistances, and large drive currents. For gates 0.19 μm long, front-gate oxides 8.2 nm thick, and back-gate oxides 9.9 nm thick, we obtained ring oscillator delay times of 43 ps at 1 V and 27 ps at 2 V. To our knowledge, these values are the fastest reported for this gate length with suppressed short-channel effects     

Low-resistance self-aligned Ti-silicide technology for sub-quartermicron CMOS devices

A low-resistance self-aligned Ti-silicide process featuring selective silicon deposition and subsequent pre-amorphization (SEDAM) is proposed and characterized for sub-quarter micron CMOS devices. 0.15-μm CMOS devices with low-resistance and uniform TiSi₂ on gate and source/drain regions were fabricated using the SEDAM process. Non-doped silicon films were selectively deposited on gate and source/drain regions to reduce suppression of silicidation due to heavily-doped As in the silicon. Silicidation was also enhanced by pre-amorphization, using ion-implantation, on the narrow gate and source/drain regions. Low-resistance and uniform TiSi₂ films were achieved on all narrow, long n⁺ and p⁺ poly-Si and diffusion layers of 0.15-μm CMOS devices. TiSi₂ films with a sheet resistance of 5 to 7 Ω/sq were stably and uniformly formed on 0.15-μm-wide n⁺ and p⁺ poly-Si. No degradation in leakage characteristics was observed in pn-junctions with TiSi₂ films. It was confirmed that, using SEDAM, excellent device characteristics were achieved for 0.15-μm NMOSFET's and PMOSFET's with self-aligned TiSi₂ films     

High-performance subquarter-micrometer gate CMOS technology

A single phosphorous-doped poly(n⁺)-Si gate, a 3.5-nm-thick gate oxide, and a retrograde twin-well structure with trench isolation are used in the devices considered. Latchup holding voltages exceed 8 V. The transconductances of 0.22-μm-gate-length n and p MOSFETs are 450 and 330 mS/mm, respectively, and unloaded ring oscillator delays are 36 ps at 2 V. A static-type 1/2 divider utilizing nMOSFETs of 0.16-μm gate length and pMOSFETs of 0.22-μm gate length achieved a maximum operating frequency of 1.3 GHz and power of 5.6 mW at a supply voltage of 2 V     

High-performance 0.10-μm CMOS devices operating at roomtemperature

The authors have fabricated 0.10-μm gate-length CMOS devices that operate with high speed at room temperature. Electron-beam lithography was used to define 0.10-μm polysilicon gate patterns. Surface-channel type p- and n-channel MOSFETs were fabricated using an LDD structure combined with a self-aligned TiSi₂ process. Channel doping was optimized so as to suppress punchthrough as well as to realize high transconductance and low drain junction capacitance. The fabricated 0.10-μm CMOS devices have exhibited high transconductance as well as a well-suppressed band-to-band tunneling current, although the short-channel effect occurred somewhat. The operation of a 0.10-μm gate-length CMOS ring oscillator has been demonstrated. The operation speed was 27.7 ps/gate for 2.5 V at room temperature, which is the fastest CMOS switching ever reported     

High Performance 70nm CMOS Devices

首次在国内成功地制作了栅长为70nm的高性能CMOS器件．为了抑制70nm器件的短沟道效应同时提高它的驱动能力,采用了一些新的关键工艺技术,包括3nm的氮化栅氧化介质,多晶硅双栅电极,采用重离子注入的超陡倒掺杂沟道剖面,锗预无定形注入加低能注入形成的超浅源漏延伸区,以及锗预无定形注入加特殊清洗处理制备薄的、低阻自对准硅化物等．CMOS器件的最短的栅长(即多晶硅栅条宽度)只有70nm,其NMOS的阈值电压、跨导和关态电流分别为0.28V、490mS/m和0.08nA／μm;而PMOS阈值电压、跨导和关态电流分别为－0.3V、340mS／mm和0.2nA／μm．并研制成功了100nm栅长的CMOS57级环形振荡器,其在1.5V、2V和3V电源电压下的延迟分别为23.5ps/级、17.5ps/级和12.5ps/级．     

High-performance dual-gate CMOS utilizing a novel self-alignedpocket implantation (SPI) technology

A self-aligned pocket implantation (SPI) technology is discussed. This technology features a localized pocket implantation using the gate and drain electrodes (TiSi₂ film) as well as self-aligned masks. The gate polysilicon is patterned by KrF excimer laser lithography. The measured minimum gate length L_g (the physical gate length) is 0.21 μm for both N- and P-MOSFETs. A newly developed photoresist was used to achieve less than quarter-micrometer patterns. This process provides high punchthrough resistance and high current driving capability even in such a short channel length. The subthreshold slope of the 0.21-μm gate length is 76 mV/dec for N-MOSFETs and 83 mV/dec for P-MOSFETs. The SPI technology maintains a low impurity concentration in the well (less than 5×10 ¹⁶ cm^-3). The drain junction capacitance is decreased by 36% for N-MOSFETs and by 41% for P-MOSFETs, compared to conventional LDD devices, which results in high-speed circuit operation. The delay time per stage of a 51-stage dual-gate CMOS ring oscillator is 50 ps with a supply voltage of 3.3 V and a gate length of 0.36 μm, and 40 ps with a supply voltage of 2.5 V and a gate length of 0.21 μm     

High-speed NMOS circuits made with X-ray lithography and reactive sputter etching

The performance of fine line NMOS circuits fabricated with X-ray lithography and reactive sputter etching shows that NMOS can be competitive with other high-speed technologies. Enhancement and depletion mode silicon gate devices with 0.25 µm junction depth, 200 Å gate oxide and 0.7 µm channel length have been used in a 175 ps delay per stage ring oscillator with a 5V power-delay product of .24 pJ and a 600 MHz, 4 stage counter. Slight technology changes also produced a 92 ps delay ring oscillator with a 5V power delay product of 0.53 pJ.     

Fabrication of self-aligned 90-nm fully depleted SOI CMOS SLOTFETs

We have developed a novel sub-100-nm fully depleted silicon-on-insulator (SOI) CMOS fabrication process, in which conventional 248-nm optical lithography and nitride spacer technology are used to define slots in a sacrificial layer (SLOTFET process). This process features a locally thinned SOI channel with raised source-drain regions, and a low-resistance T-shaped poly-Si gate; Both n- and p-channel MOSFETs with 90-nm gate length have been demonstrated. At a 0.5 V bias voltage, ring-oscillator propagation delay of less than 50 ps per stage has been measured     

0.25 μm gate length CMOS devices for cryogenic operation

Under cryogenic operation, a low V_th realizes a high speed performance at a greatly reduced power-supply voltage, which is the most attractive feature of Cryo-CMOS. It is very important in sub-0.25 μm Cryo-CMOS devices to reconcile the miniaturization and the low V_th. Double implanted MOSFET's technology was employed to achieve the low V_th while maintaining the short channel effects immunity. We have investigated both the DC characteristics and the speed performance of 0.25 μm gate length CMOS devices for cryogenic operation. The measured transconductances in the saturation region were 600 mS/mm for 0.2 μm gate length n-MOSFET's and 310 mS/mm for 0.25 μm gate length p-MOSFET's at 80 K. The propagation delay time in the fastest CMOS ring oscillator was 22.8 ps at V_dd=1 V at 80 K. The high speed performance at extremely low power-supply voltages has been experimentally demonstrated. The speed analysis suggests that the sub-l0 ps switching of Cryo-CMOS devices will be realized by reducing the parasitic capacitances and through further miniaturization down to 0.1 μm gate length or below     

Fully symmetric cooled CMOS on (110) plane

A cooled CMOS device using dual-polysilicon gates, (110) Si substrates, lightly doped drains with doping concentrations of 10¹⁴ cm^-2, and no channel implant is described. It is found that the peak mobility of a p⁺ polysilicon gate pMOS transistor on a (110) plane is 1.6 times larger than that on a (100) plane at 77 K. This pMOS transistor si very promising for use at 77 K because of its steeper subthreshold slope and higher hole mobility. The design has realized fully symmetrical cooled CMOS devices with 0.8-μm gates in which saturation currents and transductances of both n and pMOS transistors have been almost equalized. This fully symmetric cooled CMOS increases the ring oscillator speed by a factor of 1.2 and allows flexible CMOS circuit design that allows effective use of NOR gates     

Damascene W/TiN gate MOSFETs with improved performance for 0.1-/spl mu/m regime

W/TiN gate CMOS technologies with improved performance were investigated using a damascene metal gate process. 0.1-/spl mu/m W/TiN stacked gate CMOS devices with high performance and good driving ability were fabricated successfully by optimizing the W/TiN stacked gate structure, improving the W/TiN gate electrode sputtering technology, and reducing W/TiN stacked gate MOSFET surface states and threshold voltages. A super steep retrograde (SSR) channel doping with heavy ion implantation, /sup 115/In/sup +/ for NMOS and /sup 121/Sb/sup +/ for PMOS, was applied here to obtain a reasonably lower threshold voltage and to suppress short-channel effects (SCEs). Non-CMP technology, used to replace CMP during the damascene metal gate process, was also explored. The propagation delay time of 57 stage W/TiN gate CMOS ring oscillators was 13 ps/stage at 3 V and 25 ps/stage at 1.5 V, respectively. Better performance would be achieved by using Co/Ti salicide source/drain (S/D) and thinner gate dielectrics.     

P-MOSFET's with ultra-shallow solid-phase-diffused drain structureproduced by diffusion from BSG gate-sidewall

A p-MOSFET structure with solid-phase diffused drain (SPDD) is proposed for future 0.1-μm and sub-0.1-μm devices. Highly doped ultrashallow p⁺ source and drain junctions have been obtained by solid-phase diffusion from a highly doped borosilicate glass (BSG) sidewall. The resulting shallow, high-concentration drain profile significantly improves short channel effects without increasing parasitic resistance. At the same time, an in situ highly-boron-doped LPCVD polysilicon gate is introduced to prevent the transconductance degradation which arises in ultrasmall p-MOSFETs with lower process temperature as a result of depletion formation in the p⁺-polysilicon gate. Excellent electrical characteristics and good hot-carrier reliability are achieved     

Experimental high performance sub-0.1 μm channel nMOSFET's

Very high performance sub-0.1 μm channel nMOSFET's are fabricated with 35 Å gate oxide and shallow source-drain extensions. An 8.8-ps/stage delay at V_dd=1.5 V is recorded from a 0.08 μm channel nMOS ring oscillator at 85 K. The room temperature delay is 11.3 ps/stage. These are the fastest switching speeds reported to date for any silicon devices at these temperatures. Cutoff frequencies (f_T) of a 0.08 μm channel device are 93 GHz at 300 K, and 119 GHz at 85 K, respectively. Record saturation transconductances, 740 mS/mm at 300 K and 1040 mS/mm at 85 K, are obtained from a 0.05 μm channel device. Good subthreshold characteristics are achieved for 0.09 μm channel devices with a source-drain halo process     

n+/p+ Gate Bulk FinFETs With Locally Separated Channel Structure for Sub-50-nm DRAM Cell Transistors

We proposed a new p⁺/n⁺ poly-Si gate bulk fin-type field-effect transistor that has two channel fins separated locally by a shallow trench filled with oxide or p⁺ polygate. Key device characteristics were investigated by changing the n⁺ poly-Si gate length La, the material filling the trench, and the width and length of the trench at a given gate length L_g. It was shown that the trench filled with p⁺ poly-Si gate should not be contacted with the source/drain diffusion region to achieve an excellent I_on/I_off (> 1010) that is suitable for sub-50-nm dynamic random access memory cell transistors. Based on the aforementioned device structure, we designed reasonable Ls/Lg and channel fin width W_cfin at given L_g 's of 30, 40, and 50 nm.     

N+多晶硅栅薄膜全耗尽SOI CMOS器件与电路的研究

选用SIMOX(Separation by Implantation of Oxygen)衬底材料,对全耗尽SOI CMOS工艺进行了研究,开发出了N 多晶硅栅全耗尽SOI CMOS器件及电路工艺,获得了性能良好的器件和电路。nMOS和pMOS的驱动电流都比较大,且泄漏电流很小,在工作电压为3V时,1．2μm101级环振的单级延迟仅为50．5ps。     

Process integration and device performance of a submicrometerBiCMOS with 16-GHz ft double poly-bipolar devices

Submicrometer-channel CMOS devices have been integrated with self-aligned double-polysilicon bipolar devices showing a cutoff frequency of 16 GHz. n-p-n bipolar transistors and p-channel MOSFETs were built in an n-type epitaxial layer on an n⁺ buried layer, and n-channel MOSFETs were built in a p-well on a p⁺ buried layer. Deep trenches with depths of 4 μm and widths of 1 μm isolated the n-p-n bipolar transistors and the n- and p-channel MOSFETs from each other. CMOS, BiCMOS, and bipolar ECL circuits were characterized and compared with each other in terms of circuit speed as a function of loading capacitance, power dissipation, and power supply voltage. The BiCMOS circuit showed a significant speed degradation and became slower than the CMOS circuit when the power supply voltage was reduced below 3.3 V. The bipolar ECL circuit maintained the highest speed, with a propagation delay time of 65 ps for C_L=0 pF and 300 ps for C_L=1.0 pF with a power dissipation of 8 mW per gate. The circuit speed improvements in the CMOS circuits as the effective channel lengths of the MOS devices were scaled from 0.8 to 0.4 μm were maintained at almost the same ratio