超高压器件界面电荷诱发击穿电压退化的改善

本研究提出了一种创新的P型表面掺杂工程技术,可专门应用于仿真程序时,优化布局中具交互指叉(interdigital)几何图案的器件结构内,不同区域的PN结反向击穿电压退化现象。如:超高压器件的源极中心(Source Center)、漏极中心(Drain Center)、或是平坦区(flat region)。超高压器件的工艺中,PN结反向击穿电压的退化往往归咎于界面陷阱电荷(interface-trapped charge)。而在硅晶圆阶段中,由于封装等级(package level)可靠度测试(reliability test)所带来的热应力,亦可使击穿电压退化与电流拥挤(current crowding)等现象浮现。因此,在优化的过程中,为了保有器件的高击穿电压特性,吾人藉由改变P型表面掺杂的二维几何设计,同时也利用静电放电测试(ESD test),来观察界面陷阱电荷,在器件遭受静电放电攻击后的分布变化。本研究最终针对具备最大长度结构(length structure)的P型表面掺杂,在击穿电压操作范围内,以及静电放电测试中,如何得到更佳的稳定性,作深入探讨。     

Study of the manufacturing feasibility of 1.5-nm direct-tunnelinggate oxide MOSFETs: uniformity, reliability, and dopant penetration ofthe gate oxide

Although direct tunneling gate oxide MOSFETs are expected to be useful in high-performance applications of future large-scale integrated circuits (LSIs), there are many concerns related to their manufacture. The uniformity, reliability, and dopant penetration of 1.5-nm direct-tunneling gate oxide MOSFETs were investigated for the first time. The variation of oxide thickness in an entire 150-mm wafer was evaluated by TEM and electrical measurements. Satisfactory values of standard deviations in the TEM measurements and threshold voltage measurements for MOSFETs with a gate area of 5 μm×0.75 μm, were obtained. These values improved significantly in the case of MOS capacitors with larger gate areas. The oxide breakdown field and the reliability with respect to charge injection were evaluated for the 1.5-nm gate oxides and found to be better than those of thicker gate oxides. Dopant penetration was not observed in n⁺ polysilicon gates subjected to RTA at 1050°C for 20 s and furnace annealing at 850°C for 30 min. Although much more data will be required to judge the manufacturing feasibility, these results suggest that 1.5-nm direct-tunneling oxide MOSFETs are likely to have many practical applications     

Sub-quarter micron silicon integrated circuits and single wafer processing

This paper describes the role of single wafer processing in the development of sub-quarter micron silicon integrated circuits (ICs). The issues related to device processing, choice of materials, performance, reliability, and manufacturing are covered. Single wafer processing based rapid photothermal processing (dominant photons with wavelength less than about 800 nm) is an ideal answer to almost all the thermal processing requirements of current and future Si ICs. For process integration, a new model for process optimization based on minimization of thermal stress is proposed. For breaking the sub-100 nm manufacturing barriers, high throughput lithography based on direct writing is a proposed solution.     

New tools for yield improvement in integrated circuit manufacturing: can they be applied to reliability?

This paper will start with a discussion of why probe yield (the number of good chips per silicon wafer) is so important to financial success in integrated circuit manufacturing. Actual data will be quoted and a numerical example shown. A simple model will be given to demonstrate the main factors influencing yield and the relationship between yield and reliability of the final product. In the last few years a range of new tools have been deployed in manufacturing, and these have accelerated the pace of yield improvement, thus increasing competitive pressures. These tools will be described, along with examples of their use. Topics will include in-line inspection and control, automatic defect classification and data mining techniques. A proposal is made to extend these tools to the improvement of reliability of products already in manufacturing by maintaining absolute chip identity throughout the entire wafer fabrication, packaging and final testing steps.     

C4NP-无铅倒装晶片焊凸形成生产工艺与可靠性数据

受控倒塌芯片连接新工艺是一种由IBM公司开发、由Suss Micro Tec公司推向商品化的新型焊凸形成技术。受控倒塌芯片连接新工艺采用各种无铅焊料合金致力于解决现有的凸台。形成技术限定,使低成本小节距焊凸形成成为可能。受控倒塌芯片连接新工艺是一种焊球转移技术,熔焊料被注入预先制成并可重复使用的玻璃模板(模具)。这种注满焊料的模具在焊料转入圆片之前先经过检查以确保高成品率。注满焊料的模具与圆片达到精确的接近后以与液态熔剂复杂性无关的简单工序转移在整个300mm(或300mm以下)圆片上。受控倒塌芯片连接新工艺技术能够在焊膏印刷中实现小节距凸台形成的同时提供相同合金选择的适应性。这种简单的受控倒塌芯片连接新工艺使低成本、高成品率以及快速封装周期的解决方法对于细节距FCiP以及WLCSP凸台形成均能适用。     

Stencil mask ion implantation technology

The ion implantation process is important for the development or manufacturing of semiconductor devices, because ion implantation conditions directly influence some characteristics of semiconductor devices. Recently, we developed a new implantation technology, stencil mask ion implantation technology (SMIT). In the SMIT system, the stencil mask acts like a resist mask, and ions passing through the mask holes are implanted into selected regions of the Si substrate chip by chip. Use of SMIT has several advantages, notably lower manufacturing cost and shorter process time than in the case of conventional processing, because no photolithography process (including deposition and stripping of resist) is required. We have already demonstrated an application of SMIT to transistor fabrication, using various implanted dose conditions for the same wafer. Threshold voltage values can be controlled as effectively by implanted doses as they can by conventional implantation, and the dose dependence of the threshold voltage could be obtained from one wafer to which various implantation conditions are applied. Using SMIT, implantation conditions can be changed chip by chip without additional processes. This flexibility of implantation conditions is another advantage of SMIT. In this paper, we propose stencil mask ion implantation technology and show some fundamental results obtained by applying SMIT     

Relationship between wafer fracture reduction and controlling during the edge manufacturing process

Given the trend towards wafers of a larger diameter, microelectronics circuits are driven by modern IC manufacturing technology. Silicon wafer breakage has become a major concern of all semiconductor fabrication lines because silicon wafer is brittle and high stresses are induced in the manufacturing process. Additionally, the production cost is increasing. Even a breakage loss of a few per cent drives up device costs significantly if wafers are broken near completion, but wafer breakage even near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength empolying a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.This work presents an approach for characterizing silicon wafer failure strength using a simple drop test, to improve our understanding of the stress accumulated in wafer bulk before failure. However, this work will describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unknown reasons. According to an analysis based on the material mechanical theory for the bevel lengths (A1, A2), the edge length and the bevel angle (θ) are optimized to design the edge profile of the produced wafer, to prevent wafer breakage. Restated, when proper material and process control techniques are utilized, silicon wafer breakage should be prevented. This work is the first to demonstrate the importance of understanding wafer strength using a simple mechanical approach.     

Relationship between wafer edge design and its ultimate mechanical strength

Due to its brittle nature, high stress-induced in manufacturing process, silicon wafer breakage has become a major concern for all semiconductor fabrication line. Furthermore, the production cost had increased in advanced technology day by day. Even a some-percent breakage loss drives device costs up significantly if wafers are broken near completion. Consequently, wafer breakage even near the beginning of the process is significant. In short words, silicon wafer breakage has become a major concern for all semiconductor fabrication lines, and so high stresses are easily induced in its manufacture process. The production cost is increasing even breakage loss of a few percent significantly drives device costs up, if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength employing a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.A physical model would also be proposed to explain the results. This model demonstrates that the fracture rate of wafers can be reduced by controlling the uniformity of the difference between the front and rear bevel lengths during the wafer manufacturing process.     

Computer-Aided Small-Signal Characterization of IMPATT Diodes

This paper is a discussion of IMPATT wafer small-signal characteristics in the frequency range of 2.0-8.0 GHz. These characteristics have been obtained by computer conversion of reflection phase-gain data. The data handling technique which allows establishment of the desired reference plane and the reduction of the admittance data into the desired equivalent circuit is presented. A calibration procedure using reference impedances consistent with the diode geometry is discussed. The validity of the microwave measurement technique and the data handling process is demonstrated by comparison of the values of junction capacitance determined at microwave frequencies with junction capacitance measurements at 30 MHz. Representative plots are given for wafer conductance and susceptance as a function of frequency with current density as a parameter. In addition, typical values obtained for the circuit elements are presented. These data illustrate the capability of determining package inductance, series resistance as a function of bias voltage, and, with the diode in avalanche, the parallel G, L, and C of the wafer admittance. The diode equivalent circuit was studied as a function of current density to compare results with the existing analytical small-signal theories. This procedure permits the separation of the wafer elements from the parasitic elements of the package. Data obtained from these measurements are extremely useful for ascertaining wafer design parameters and assisting in circuit design.     

Yield and performance enhancement through redundancy in VLSI and WSI multiprocessor systems

New challenges have been brought to fault-tolerant computing and processor architecture research because of developments in IC technology. One emerging area is development of architectures, built by interconnecting a large number of processing elements on a single chip or wafer. Two important areas, related to such VLSI processor arrays, are the focus of this paper; they are fault-tolerance and yield improvement techniques. Fault tolerance in these VLSI processor arrays is of real practical significance; it provides for much-needed reliability improvement. Therefore, we first describe the underlying concepts of fault tolerance at work in these multiprocessor systems. These precepts are useful to then present certain techniques that will incorporate fault tolerance integrally into the design. In the second part of the paper we discuss models that evaluate how yield enhancement and reliability improvement may be achieved by certain fault-tolerant techniques.     

An introduction to fast wafer level reliability monitoring for integrated circuit mass production

The continuous verification of process reliability is essential to semiconductor manufacturing. The tool that accomplishes this task in the required short time is the fast wafer level reliability monitoring (fWLR). The basic approaches for this task are described in this introductory overview. It summarizes sampling plans, discusses the feasibility of using fWLR for screening and describes the data assessment and application of control cards. Beyond these general topics many of the fWLR stress methods are described in detail: Dielectric stressing by means of an exponential current ramp is compared to ramped voltage stress. Especially for thin oxides the methods differ regarding the soft breakdown detection and the time they consume. Another task of fWLR is the detection of plasma induced damage, which can be achieved by applying a revealing stress to MOSFETs with antenna. The design challenges of the structures and the test method as well as the data assessment are described in detail. An important section deals with fWLR for interconnects. In this section the appropriate test structures (including thermal simulations) are illustrated and fast electromigration stresses are discussed and the details of standard wafer level electromigration accelerated test (SWEAT) are included. For contacts and vias a simple method to check reliability is presented. Finally the monitoring of device reliability is treated. It is shown that using indirect parameters that correlate well to standard parameters such as the drain current can be beneficial for fWLR. For both, the interconnects and the devices, it is essential to have locally heated test structures in order to keep the stress time low. The detection and verification of mobile ions can also be performed with such a self-heated structure. For the described methods examples are given to illustrate the usefulness.     

Ultrathin wafer level chip size package

The ShellCase wafer-level packaging process uses commercial semiconductor wafer processing equipment. Dies are packaged and encapsulated into separate enclosures while still in wafer form. This wafer level chip size package (WLCSP) process encases the die in a solid die-size glass shell. The glass encapsulation prevents the silicon from being exposed and ensures excellent mechanical and environmental protection. A proprietary compliant polymer layer under the bumps provides on board reliability. Bumps are placed on the individual contact pads, are reflowed, and wafer singulation yields finished packaged devices. This WLCSP fully complies with Joint Electron Device Engineering Council (JEDEC) and surface mount technology (SMT) standards. Such chip scale packages (CSP's) measure 300-700 μm in thickness, a crucial factor for use in various size sensitive electronic products     

表面掺杂浓度对低压TVS的影响研究

瞬态电压抑制器(TVS)是一种二极管形式的接口保护器件,其中低压TVS通常由低阻外延层和其表面的高浓度掺杂区构成。在芯片制造工艺过程中,圆片的表面掺杂浓度对器件特性有很大的影响,非正常的杂质扩散变化极易导致器件参数异常。文章就某低压TVS制造过程中出现的参数异常进行了排查,确认异常原因为表面掺杂浓度过高,并就表面掺杂浓度与器件参数的变化趋势进行了分析,并通过实验得到验证。     

Wafer-level hermetic MEMS packaging by anodic bonding and its reliability issues

This paper reviews wafer-level hermetic packaging technology using anodic bonding from several reliability points of view. First, reliability risk factors of high temperature, high voltage and electrochemical O₂ generation during anodic bonding are discussed. Next, electrical interconnections through a hermetic package, i.e. electrical feedthrough, is discussed. The reliability of both hermetic sealing and electrical feedthrough must be simultaneously satisfied. In the last part of this paper, a new wafer-level MEMS packaging material, anodically-bondable low temperature cofired ceramic (LTCC) wafer, is introduced, and its reliability data on hermetic sealing, electrical interconnection and flip-chip mounting on a printed circuit board (PCB) are described.     

超薄型圆片级芯片尺寸封装技术

ShellCase公司的圆片级封装技术工艺,采用商用半导体圆片加工设备,把芯片进行封装并包封到分离的腔体中后仍为圆片形式。圆片级芯片尺寸封装(WL-CSP)工艺是在固态芯片尺寸玻璃外壳中装入芯片。玻璃包封防止了硅片的外露,并确保了良好的机械性能及环境保护功能。凸点下面专用的聚合物顺从层提供了板级可靠性。把凸点置于单个接触焊盘上,并进行回流焊,圆片分离形成封装器件成品。WL-CSP封装完全符合JEDEC和SMT标准。这样的芯片规模封装(CSP),其测量厚度为300μm-700μm,这是各种尺寸敏感型电子产品使用的关键因素。     

圆片级封装技术——超CSPTM

文章论述了超CSPTM圆片级封装技术工艺。在封装制造技术方面此CSP封装技术的优越性在于其使用了标准的IC工艺技术。这不仅便于圆片级芯片测试和老炼筛选,而且在圆片制造末端嵌入是理想的。同时,文章也论述了超CSP封装技术的电热性能特征。     

Verification and reduction of surface charging during high/medium current implantations by implementing plasma damage monitoring

Dielectric charging damage during IC processing is the result of complex interactions between the wafer environment and the wafer itself. Understanding these interactions and recognizing the relative importance of the different mechanisms capable of causing damage, is essential for successful diagnosis and control of charging damage during wafer manufacturing. Avoiding gate oxide damage due to excessive wafer charging has always been an issue with high current implanters. Whether it is caused by shrinking of device dimensions, or its use as a backup for high current applications, charging level awareness becomes the primary limiting factor for running higher beam currents in medium current implanters. Flooding the wafer with low energy electrons from a plasma flood gun (PFG) which is a self-regulated electron shower, has been the widely accepted means of reducing wafer charging. The effectiveness of the PFG in reducing charging as a function of primary ion current, voltage of electron extraction from the PFG, ion beam positioning and other parameters in a beam path to the wafer have been investigated. This investigation was carried out on medium and high current implanters, VIISta 810HP and VIIStaHC respectively, using the plasma damage monitoring (PDM) technique on metrology tool FAaST350.     

HgCdTe/CdZnTe P-I-N high-energy photon detectors

Classical solid-state detection of x-ray and gamma-ray radiation consists of a high voltage applied between two metallic contacts sandwiching a high resistivity, high dielectric strength material; high voltage and high resistivity are required to enable complete charge collection while minimizing the resolution-degrading leakage current (dark current). We report here the conception and successful fabrication and test of a new device construct which changes this paradigm. P-type and n-type layers are fabricated by mercury cadmium telluride (HC.T) liquid phase epitaxy (LPE) on opposite sides of a high-quality wafer of CdZnTe (CZT) in order to construct a p-i-n diode structure. Wafers up to 9 cm² area have been grown. This diode structure provides an extremely high effective resistivity and barrier to the flow of dark current in the device. Several wafer lots have repeatably yielded p-i-n detectors which exhibit typical diode current-voltage (I-V) curves with very low dark currents at very high bias voltages. Spectra obtained from these detectors produce exceptionally sharp photopeaks which exhibit very little low-energy tailing.     

Introducing a scale structure to correlate quality and reliability

The most important reliability in microelectronics is the reliability that the end customer experiences. In order to improve or build-in reliability, measurements are needed as early in semiconductor processing as possible. Often, quality and capability of a semiconductor wafer are the earliest available measurements. This work describes a test structure that converts physical attributes into parametric variables. This double conversion can further be correlated from quality to reliability by conventional or wafer level aging. The result is an early and efficient method of assessing reliability.