Nanoscale two-bit/cell NAND silicon-oxide-nitride-oxide-silicon memory device with different tunneling oxide thicknesses

Nanoscale two-bit/cell NAND-type silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices with different tunneling oxide thicknesses were designed to reduce the short channel effect and the coupling interference. The process step and the electrical characteristics of the proposed SONOS memory devices were simulated by using SUPREM-4 and MEDICI, respectively. The short channel effect in the nanoscale two-bit/cell SONOS devices was decreased than that of the conventional devices due to a larger effective channel length. The drain current at the on-state of the proposed NAND SONOS memory devices decreased than that of the conventional NAND SONOS devices due to the high channel resistivity. The I on/I off ratio of the proposed NAND SONOS memory devices was larger than that of the conventional memory devices due to the dramatic decrease in the subthreshold current of the proposed devices. The electrical characteristics of the NAND SONOS memory devices with different tunneling oxide thicknesses were better than those of the conventional NAND SONOS devices.     

Fabrication and program/erase characteristics of 30-nm SONOS nonvolatile memory devices

In this paper, we have fabricated nanoscale silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices by means of the sidewall patterning technique. The fabricated SONOS devices have a 30-nm-long and 30-nm-wide channel with 2.3/12/4.5-nm-thick oxide/nitride/oxide film on fully depleted-silicon-on-insulator (FD-SOI) substrate. The short channel effect is well suppressed though devices have very short channel length and width. Also, the fabricated SONOS devices guarantee good retention and endurance characteristics. In 30-nm SONOS devices, channel hot electron injection program mechanism is inefficient and 2-b operation based on localized carrier trapping in the nitride film is difficult. The erase speed is improved by means of band-to-band (BTB) assisted hole injection mechanism. In 30-nm SONOS devices, program and erase operation can be performed efficiently with improved erase speed by combination of Fowler-Nordheim (F-N) tunneling program and BTB assisted hole injection erase mechanism because the entire channel region programmed by F-N tunneling can be covered by two-sided hole injection from source and drain.     

Fully integrated SONOS flash memory cell array with BT (body tied)-FinFET structure

Fully integrated SONOS memory cell arrays with BT (body tied)-FinFET structure have been fabricated successfully by using manufacturable NOR flash technology. The uniformity of threshold voltage (V/sub th/) distribution of the fabricated FinFET SONOS cells is fairly better than that of conventional flash cells thanks to both the widening effective channel width of FinFET structure and negligible coupling interference of SONOS device. New two-step channel implantation process has been introduced for the compensation for the boron out-diffusion of a three-dimensional silicon fin structure. The measured FinFET SONOS cells with a two-step channel doping profile show the improved program and erase characteristics. For the improvement of program/erase and retention characteristics all together, we have investigated the modulation of erase bias condition with respect to back tunneling effect.     

Nanoscale two-bit/cell NAND silicon-oxide-nitride-oxide-silicon devices with a separated double-gate saddle-type structure

Nanoscale two-bit/cell NAND silicon-oxide-nitride-oxide-silicon flash memory devices based on a separated double-gate (SDG) saddle structure with a recess channel region had two different doping regions in silicon-fin channel to operate two-bit per cell. A simulation results showed that the short channel effect, the cross-talk problem between cells, and the increase in threshold voltage distribution were minimized, resulting in the enhancement of the scaling-down characteristics and the program/erase speed.     

Comparative analysis of trap-based program/erase behaviors with different tunnel barriers

In this study, we comparatively analyze the trap-based memory characteristics of Oxide-Nitride-Oxide (ONO) devices with different tunnel dielectrics. We fabricated two kinds of ONO devices-one is the conventional single tunnel oxide structure and the other is the bandgap engineered structure in which the modulated tunnel dielectric replaces the single tunnel oxide. The charge storage layer is 9 nm and the blocking oxide is 7 nm in both two kinds of ONO devices. Based on experimental results, we find that the memory speed is promoted to 2-4 times and 10-year data retention greatly improves in the bandgap engineered device comparing to those in the conventional device. As a result, the bandgap engineered tunnel barrier device embodies both fast P/E operation speeds and excellent long-term data retention characteristics, hence, the bandgap engineered tunnel barrier is expected to conduct performance optimization for the future scaled SONOS flash memory.     

Charge trapping devices using a bilayer oxide structure

This experiment is the first exploration of use of charge traps in the bulk of deposited top oxide and at the interface between thermal oxide and deposited top oxide. We report the operational characteristics of SiO2/SiO2 device structures with 0.5 microm gate width and length. Low power operations are achieved through very thin gate stacks of 3 nm of thermally grown oxide and 7 nm of deposited oxide. However, narrow memory windows have been acquired comparing with conventional silicon-oxide-nitride-oxide-silicon (SONOS) memory cells due to a low trap density at the interface between a grown oxide and a deposited oxide. Additionally, the electric field between the channel and the charge is determined by solving 1D Poisson equation at a given write voltage, then total tunneling current density is calculated to make a program modeling for charge trapping devices. Tunneling/trapping simulation based on Fowler-Nordheim (F-N) tunneling performed and it fits the programming curves well. The memory window is almost constant after 100,000 cycles, and the retention characteristics are deteriorated rapidly.     

Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile

The effects of a nonuniform source/drain (S/D) doping profile on the FinFET characteristics are investigated using three-dimensional device simulation. With a fixed S/D doping profile, larger silicon-on-insulator (SOI) thickness can suppress short-channel effects due to the coexistence of longer channel regions. There can be some design margin in the channel thickness due to this reduced short-channel effect. Drain saturation current in FinFET is proportional to the effective device width and SOI thickness. To determine the appropriate SOI thickness of FinFET, alternating current (AC) characteristics are investigated. Device capacitance increases with SOI thickness, but this is not for the gate delay, as the drive current also increases and compensates for the increase of capacitance. When driving a constant capacitance load such as interconnect, devices with larger drain current or thicker SOI are more favorable for the fixed S/D doping condition.     

Design of on-chip error correction systems for multilevel NOR and NAND flash memories

The design of on-chip error correction systems for multilevel code-storage NOR flash and data-storage NAND flash memories is concerned. The concept of trellis coded modulation (TCM) has been used to design on-chip error correction system for NOR flash. This is motivated by the non-trivial modulation process in multilevel memory storage and the effectiveness of TCM in integrating coding with modulation to provide better performance at relatively short block length. The effectiveness of TCM-based systems, in terms of error-correcting performance, coding redundancy, silicon cost and operational latency, has been successfully demonstrated. Meanwhile, the potential of using strong Bose-Chaudhiri-Hocquenghem (BCH) codes to improve multilevel data-storage NAND flash memory capacity is investigated. Current multilevel flash memories store 2 bits in each cell. Further storage capacity may be achieved by increasing the number of storage levels per cell, which nevertheless will correspondingly degrade the raw storage reliability. It is demonstrated that strong BCH codes can effectively enable the use of a larger number of storage levels per cell and hence improve the effective NAND flash memory storage capacity up to 59.1% without degradation of cell programming time. Furthermore, a scheme to leverage strong BCH codes to improve memory defect tolerance at the cost of increased NAND flash cell programming time is proposed.     

Four‐Bits‐Per‐Cell Operation in an HfO2‐Based Resistive Switching Device

The quadruple‐level cell technology is demonstrated in an Au/Al₂O₃/HfO₂/TiN resistance switching memory device using the industry‐standard incremental step pulse programming (ISPP) and error checking/correction (ECC) methods. With the highly optimistic properties of the tested device, such as self‐compliance and gradual set‐switching behaviors, the device shows 6σ reliability up to 16 states with a state current gap value of 400 nA for the total allowable programmed current range from 2 to 11 µA. It is demonstrated that the conventional ISPP/ECC can be applied to such resistance switching memory, which may greatly contribute to the commercialization of the device, especially competitively with NAND flash. A relatively minor improvement in the material and circuitry may enable even a five‐bits‐per‐cell technology, which can hardly be imagined in NAND flash, whose state‐of‐the‐art multiple‐cell technology is only at three‐level (eight states) to this day.     

Ultrashort SONOS memories

We report the operational characteristics of ultrashort SONOS memories down to /spl sim/30-nm effective gate length. Good sub-threshold swing, good drain-induced barrier lowering (/spl sim/120 mV/decade), and /spl sim/2.4 V of memory window down to the smallest dimensions demonstrate the improvements that result from a thin tunneling oxide and a large trapping center density. The use of distributed defects and thin tunneling oxide is reflected in a memory window that is stable up to at least 10/sup 5/ cycles for the smallest devices. The smallest structures tested employ /spl sim/75 electrons for memory storage, which allows for device to device reproducibility. The capture and emission processes asymmetries point to the differences in the energy parameters of the two processes. The smallest structures, however, do show loss of retention time compared to the larger structures, for the same oxide-nitride-oxide stack thickness, and this is believed to arise from higher leakage due to higher defects distribution in the gate insulators from process-induced damage. All tested devices, down to /spl sim/30-nm effective gate length, show very good endurance characteristics.     

Comparison of hot-carriers effects in soi and bulk devices using a photon emission technique

This paper concerns recent results on photon emission used for hot carriers degradation analysis. In a first part, we focus on quantitative light emission analysis on n- and p- channel MOSFETs for bulk and SOI technologies. On each device, the photon counts for different gate and drain voltages were measured and compared with the value of the substrate current. This shows that the measured value of the substrate current in SOI devices can be inaccurate. In a second part, we investigate light emission spectra for some specific biases. These measurements allow a clear comparison of the different technologies. Finally, a photon emission technique was used to analyse hot carrier degradation in circuits, the highest emissions are observed on NMOS transistors working at high frequencies, but emission have also been detected on PMOS transistors. A clear correlation with the working frequencies of the MOS has also been demonstrated.     

基于 NAND Flash 的嵌入式文件系统设计

主要介绍了针对 NAND Flash 型存储器设计的嵌入式文件系统. 其硬件平台是为了顺应多功能、大容量集成化存储的需求而开发的基于 ADSP-BF532 芯片与 NAND Flash 结合的高性能嵌入式存储系统. 此存储系统采用了多片并行流水的存储模式,开发出独特有效的闪存管理技术与改良的文件系统,通过设置访问权限实现多用户管理,使得处理器、存储器以及文件管理层软件的多方优势得以充分发挥.     

Capacitorless single transistor dynamic random-access memory devices fabricated on silicon-germanium-on-insulator substrates

Capacitorless single transistor dynamic random-access memory (1T-DRAM) cells on silicon-germanium-on-insulator (SGOI) substrates with various Ge mole fractions in the relaxed-SiGe layers were investigated. SGOI substrates with strained-Si channels showed higher on-currents and carrier mobility than a silicon-on-insulator (SOI) substrate with unstrained-Si channels. SGOI 1T-DRAM devices had larger memory windows than a similar device with SOI; memory window increased with increasing Ge mole fraction in the relaxed-SiGe layer. The SGOI 1T-DRAMs showed degraded retention times. High-temperature annealing reduced the effects of crystalline defects and thus improved the electrical properties of the SGOI substrates, leading to higher carrier mobility, larger memory window, and longer data retention.     

High-performance bottom-gate poly-Si polysilicon-oxide-nitride-oxide-silicon thin film transistors crystallized by excimer laser irradiation for two-bit nonvolatile memory applications

High-performance bottom-gate (BG) poly-Si polysilicon-oxide-nitride-oxide-silicon (SONOS) TFTs with single grain boundary perpendicular to the channel direction have been demonstrated via simple excimer-laser-crystallization (ELC) method. Under an appropriate laser irradiation energy density, the silicon grain growth started from the thicker sidewalls intrinsically caused by the bottom-gate structure and impinged in the center of the channel. Therefore, the proposed ELC BG SONOS TFTs exhibited superior transistor characteristics than the conventional solid-phase-crystallized ones, such as higher field effect mobility of 393 cm2/V-s and steeper subthreshold swing of 0.296 V/dec. Due to the high field effect mobility, the electron velocity, impact ionization, and conduction current density could be enhanced effectively, thus improving the memory performance. Based on this mobility-enhanced scheme, the proposed ELC BG SONOS TFTs exhibited better performance in terms of relatively large memory window, high program/erase speed, long retention time, and 2-bit operation. Such an ELC BG SONOS TFT with single-grain boundary in the channel is compatible with the conventional a-Si TFT process and therefore very promising for the embedded memory in the system-on-panel applications.     

Channel width and length dependence in Si nanocrystal memories with ultra-nanoscale channel

The use of nanoscale channel MOSFETs as a candidate for future nonvolatile memory is extensively investigated. The device consists of a wire channel MOSFET with nanometer dimensions on which Si nanocrystals (Si-NCs) are deposited. The memory characteristics as a function of the channel widths for different channel lengths are presented. The channel length dimensions are defined between 100-1000 nm by electron beam lithography and the width dimensions are reduced from a few tens of nanometers down to sub-5 nm by wet etching and thermal oxidation processes. It is found that the controllability of the fabrication process is enhanced as the channel length is reduced to 100 nm. Moreover, memory performances are improved with decreasing channel width due to the bottleneck effect. These results show that the Si-NCs memory is highly scalable in terms of the channel size. In the narrowest channel devices, i.e., in the sub-5-nm range, coulomb-blockade oscillations are obtained due to the ultra-small regions formed in the channel. In such devices, a strong enhancement of the retention characteristics has been found as a result of the quantum mechanical narrow channel effect in the ultra-narrow channel.     

Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures

This work studies the operation of source-follower buffers implemented with standard and graded-channel (GC) fully depleted (FD) SOI nMOSFETs at low temperatures. The analysis is performed by comparing the voltage gain of buffers implemented with GC and standard SOI nMOS transistors considering devices with the same mask channel length and same effective channel length. It is shown that the use of GC devices allows for achieving improved gain in all inversion levels in a wide range of temperatures. In addition, this improvement increases as temperature is reduced. It is shown that GC transistors can provide virtually constant gain, while for standard devices, the gain departs from the maximum value depending on the temperature and inversion level imposed by the bias current and input voltage. Two-dimensional numerical simulations were performed in order to study the reasons for the enhanced gain of GC MOSFETs at low temperatures.     

Design and optimization of two-bit double-gate nonvolatile memory cell for highly reliable operation

In this paper, characterization and optimization have been performed on the 2-b floating-gate-type nonvolatile memory (NVM) cell based on a double-gate (DG) MOSFET structure using two-dimensional numerical simulation. The thickness and the difference of charge amount between programmed and erased states are found to be the crucial factors that put the NVM cell operation under optimum condition. Under fairly good conditions, the silicon thickness can reach below 30 nm while suppressing the read disturbance level within 1 V. With these results, operating schemes are investigated for both NAND - and NOR-type memory cells. This paper is based on simulation works which can give a reasonable intuition in flash memory operation. Although we adopted a floating-gate-type device since the exact modeling of Si/sub 3/N/sub 4/ used for the storage node is absent in the current numerical simulator, this helps to predict the operation of an oxide-nitride-oxide dielectric flash memory cell at a good degree.     

DC and AC characteristics of sub-50-nm MOSFETs with source/drain-to-gate nonoverlapped structure

A MOSFET structure with a nonoverlapped source/drain (S/D) to gate region was proposed to overcome the challenges in sub-50-nm CMOS devices. Key device characteristics were investigated by extensive simulation study. Fringing gate electric field through the spacer induces an inversion layer in the nonoverlap region to act as an extended S/D region. An oxide spacer is used to reduce parasitic gate overlap capacitance. A reasonable amount of inversion electrons were induced under the spacers. Internal physics, speed characteristics, short channel effects, and RF characteristics were studied with the nonoverlap distance at a fixed metallurgical channel length of 40 nm. The proposed structure had good drain-induced barrier lowering and V/sub T/ rolloff characteristics and showed reasonable intrinsic gate delay and cutoff frequency compared to those of an overlapped structure.     

Scaling considerations for sub-90 nm split-gate flash

A systematic methodology is presented to scale split-gate (SG) flash memory cells in the sub-90 nm regime within the presently known scaling constraints of flash memory. The numerical device simulation results show that the high performance sub-90 nm NOR-type SG cells can be achieved by a suitable channel and source-drain engineering. An asymmetric channel doping profile along with ultra-shallow source-drain junctions was used to achieve the target drain programming voltage (V_sp) for an efficient cell programming while keeping the cell breakdown voltage, BV > V_sp, with tolerable leakage currents. The study shows that with properly optimised technology parameters, 65 nm SG-NOR flash memory can be achieved with an adequate cell read current, a tolerable programmed cell leakage current at the read condition and efficient write and erase times.     

A figure of merit for optimization of nanocrystal flash memory design

Nanocrystals can be used as storage media for carriers in flash memories. The performance of a nanocrystal flash memory depends critically on the choice of nanocrystal size and density as well as on the choice of tunnel dielectric properties. The performance of a nanocrystal memory device can be expressed in terms of write/erase speed, carrier retention time and cycling durability. We present a model that describes the charge/discharge dynamics of nanocrystal flash memories and calculate the effect of nanocrystal, gate, tunnel dielectric and substrate properties on device performance. The model assumes charge storage in quantized energy levels of nanocrystals. Effect of temperature is included implicitly in the model through perturbation of the substrate minority carrier concentration and Fermi level. Because a large number of variables affect these performance measures, in order to compare various designs, a figure of merit that measures the device performance in terms of design parameters is defined as a function of write/erase/discharge times which are calculated using the theoretical model. The effects of nanocrystal size and density, gate work function, substrate doping, control and tunnel dielectric properties and device geometry on the device performance are evaluated through the figure of merit. Experimental data showing agreement of the theoretical model with the measurement results are presented for devices that has PECVD grown germanium nanocrystals as the storage media.