Power-Driven Routing-Constrained Scan Chain Design

Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized scan chains under a given routing constraint. The proposed technique is a three-phase process based on clustering and reordering of scan cells in the design. It allows to reduce average power consumption during scan testing. Owing to this technique, short scan connections in scan chains are guaranteed and congestion problems in the design are avoided.     

An Accumulator-Based BIST Approach for Two-Pattern Testing

Two-pattern tests target the detection of most common failure mechanisms in cmos vlsi circuits, which are modeled as stuck-open or delay faults. In this paper the Accumulator-Based Two-pattern generation (ABT) algorithm is presented, that generates an exhaustive n-bit two-pattern test within exactly 2 ⁿ × (2 ⁿ – 1) + 1 clock cycles, i.e. within the theoretically minimum time. The ABT algorithm is implemented in hardware utilizing an accumulator whose inputs are driven by either a binary counter (counter-based implementation) or a Linear Feedback Shift Register (LFSR-based implementation). With the counter-based implementation different modules, having different number of inputs, can be efficiently tested using the same generator. For circuits that do not contain counters, the LFSR-based implementation can be implemented, since registers (that typically drive the accumulator inputs into dapatapath cores) can be easily modified to LFSRS with small increase in the hardware overhead. The great advantage of the presented scheme is that it can be implemented by augmening existing datapath components, rather than building a new pattern generation structure.     

考虑测试功耗的扫描链划分新方法

提出考虑测试功耗的扫描链划分新方法.首先为基于扫描设计电路的峰值测试功耗和平均功耗建模,得出测试功耗主要由内部节点的翻转引起的结论,因此考虑多条扫描链情况,从输入测试集中寻找相容测试单元,利用扫描单元的兼容性,并考虑布局信息,将其分配到不同的扫描链中共享测试输入向量,多扫描链的划分应用图论方法.在ISCAS89平台上的实验结果表明,有效降低了峰值测试功耗和平均测试功耗.     

Reducing Average and Peak Test Power Through Scan Chain Modification

Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. The transitions embedded in both test stimuli and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as well as inversion of capture paths. No performance degradation ensues as these modifications have no impact on functional execution. To reduce average and peak power, we herein propose computationally efficient schemes that identify the location and the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.     

适用于嵌入式五口SRAM的多频率内建自测电路

提出了一种多频率带有扫描链的 BIST方案 ,用于五口的 32× 32嵌入式 SRAM的可测性设计。分析了多口 SRAM的结构并确定其故障模型 ,在此基础上提出了一种名为“对角线移动变反法”( OMOVI)的新算法及其电路实现。与传统的“移动变反法”( MOVI)相比 ,在保证故障覆盖率前提下 ,测试图形的测试步数由原来的12 N log2 N减小为 N/ 2 +2 N log2 N( N为 SRAM的容量 )。该方案集功能测试、动态参数提取和故障分析定位于一体 ,而且具有很强的灵活性和可扩展性     

LFSR-Based Deterministic TPG for Two-Pattern Testing

This paper proposes an approach to designing a cost-effective deterministic test pattern generator (TPG) for two-pattern testing. Given a set of pre-generated test-pair set (obtained by an ATPG tool) with a pre-determined (path delay) fault coverage, a simple TPG is synthesized to apply the given test-pair set in a minimal test time. To achieve this objective, a configurable linear feedback shift register (CLFSR) structure is used. Techniques are developed to synthesize such a TPG, which is used to generate an unordered deterministic test-pair set. The resulting TPG is efficient in terms of hardware size and speed performance. Experiments on benchmark circuits indicate that TPG designed using the proposed procedure obtain high path delay fault coverage in short test length.     

JTAG测试中扫描链的配置问题研究

分析了常见扫描链路配置中面临的问题,提出了一种扫描链配置方案。结合工程测试中出现的实际问题,给出了有关扫描链路配置的一些建议和注意事项。     

Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique

With increasing defect density and process variations in nanometer technologies, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. This paper presents a novel test technique based on supply gating, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overhead. Experimental results on a set of ISCAS89 benchmarks show an average reduction of 34% in area overhead with an average improvement of 65% in delay overhead and 90% in power overhead during normal mode of operation, compared to the enhanced scan implementation.

基于核的信息安全处理芯片可测性设计

从可测性设计角度讨论了信息安全处理芯片的芯片级测试控制器的设计以及相应核的可测性设计.综合结果显示,所设计的芯片级测试控制器所占用的面积代价非常小.     

多链扫描可测性设计中扫描链的选取

本文提出了多链扫描可测性设计中扫描链的构造方法．根据电路的规模、输人／输出管脚数及测试时间的要求确定扫描链个数，引人临界时间的概念，采用动态编程的方法确定每条链中的扫描触发器．采用该方法，计算速度比传统方法显著提高，同时节省了存储空间．     

A New Scan Partition Scheme for Low‐Power Embedded Systems

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low‐power embedded systems. In scan‐based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph‐based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.     

Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees

In this paper, a new method for reducing scan shifts is presented. Scan design is one of the most popular designs for test method for sequential circuits. However, for circuits with many flip-flops, it requires a long test application time and high test-data volume. Our new scan method utilizes two configurations of scan chains, a folding scan tree and a fully compatible scan tree to alleviate these problems. It is observed that uncompacted test patterns typically contain a large fraction of don't care values. This property is exploited in the fully compatible scan tree to reduce scan shifts without degrading fault coverage. Then, a folding scan tree is configured to further reduce the length of scan chain and scan shifts. Experimental results on benchmark circuits show that this scan method can significantly reduce scan shifts. Hiroyuki Yotsuyanagi received his B.E., M.E. and Ph.D degrees from Osaka University, in 1993, 1995 and 1998, respectively. In 1998 he joined the Department of Electrical and Electronic Engineering, the University of Tokushima, where he is currently an Associate Professor. His research interest includes test synthesis for sequential circuits and current testing for CMOS ICs. He is a member of the IEICE and the IEEE. Toshimasa Kuchii received B.E., M.E., and Ph.D. degrees in Electrical and Electronic Engineering from the University of Tokushima in 1994, 1996, and 1999, respectively. He is currently a DFT engineer at Sharp Corporation. His research interests are DFT methodologies for SoC devices, PLL jitter testing, and DFT for image sensor devices. Shigeki Nishikawa received B.E. in the Department of Information and Behavioral Sciences from Hiroshima University in 1980. He is currently a manager of LSI test engineering department at Sharp Corporation. His research interests are DFT, DFM and the total solution of testing technologies in the CAE tools. Masaki Hashizume received his B.E. and M.E. degrees in electrical engineering from the Univ. of Tokushima and Dr.E. degree from Kyoto Univ., in 1978, 1980 and 1993, respectively. He is currently a Professor of the Department of Electrical and Electronic Engineering, Faculty of Engineering, the Univ. of Tokushima. His research interests are logic synthesis and supply current testing of logic circuits. Kozo Kinoshita received B.E., M.E., and Ph.D. in Communication Engineering from Osaka University in 1959, 1961, and 1964, respectively. From 1964 to 1966 he was an Assistant Professor and from 1967 to 1977, an Associate Professor of Electronic Engineering at Osaka University, Osaka, Japan. From 1978 to 1989, he was a Professor in the Department of Information and Behavioral Sciences, Hiroshima University, Hiroshima, Japan. From 1989 to 2000, he again joined Osaka University as a Professor in the Department of Applied Physics, and is enumerates professor of Osaka University. Since April 2000, he has been a professor at Faculty of Informatics, Osaka Gakuin University, and is the Dean of Informatics. His fields of interest are test generation, fault diagnosis, memory testing, current testing, crosstalk testing, compact testing and testable design for logic circuits. He organized a series of Asian Test Symposium and was the Group Chair of Asian and Pacific Activities in Test Technology Technical Council of IEEE Computer Society until 2002. Prof. Kinoshita is IEEE Life Fellow, IEICE Fellow and a member of the Institute of Information Processing of Japan. He was a member of the editorial board of JETTA until 2000.     

扫描测试和扫描链的构造

本文首先论述了扫描设计与测试向量自动生成（ATPG）这种测试方法的关键技术，并由此为依据，提出部分扫描设计中，扫描链构造的分层次的三个选取原则。     

一个基于扫描方法的DFT设计与实现

DFT技术已经成为集成电路设计的一个重要组成部分.详细介绍了基于扫描测试的DFT原理和实现步骤,并对一个32位FIFO存储器电路实例进行扫描设计.根据扫描链的特点和电路多时钟域问题,采用了三种设计方案,整个流程包括了行为级Verilog代码的修改、扫描设计综合以及自动测试模板产生(ATPG).对不同的设计方案给出了相应的故障覆盖率,并对生成的模板进行压缩优化,减少了测试仿真时间.最后分析了导致故障覆盖率不同的一些因素和设计中的综合考虑.     

Efficient Test Data Compression and Low Power Scan Testing in SoCs

Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan‐in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't‐care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.     

Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing

In this paper we propose a new approach to generate a primary input blocking pattern for applying to the primary inputs during shift cycle such that the switching activity occurred in the combinational part of the circuit under test can be suppressed as much as possible. The primary input blocking technique suppresses transitions of gates in the combinational part during scan by assigning controlling values to one of the gates' inputs. However, simultaneously assigning controlling values to the gates may result in conflicts in the setting of binary values on the primary inputs. Instead of the heuristics based on fanout in other approaches, we use the impact function which is based on transition density to determine the priorities of the gates to be blocked. Experiments performed on the ISCAS 89 benchmark circuits show that the proposed approach can always produce better results than the existing approaches.

A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers

This paper presents a design for testability (DFT) technique for testing high-speed circuits with a low-speed test mode clock. With this technique, the test mode clock frequency can be reduced with virtually no lower limit. Even with the reduced speed requirement on the automatic test equipment (ATE), our method facilitates the test of the rated-speed timing and allows performance binning. A CMOS implementation of the DFT hardware with 50 ps timing accuracy is presented. To demonstrate the effectiveness of the technique we designed a 16-bit, 1.4 GHz pipelined multiplier as a test vehicle. Simulations using a test clock frequency much lower than the rated clock frequency show that delay faults of sizes as small as 50 ps are detected and that the new test technique provides correct performance binning.     

Partial Scan Testing on the Register-Transfer Level

This paper presents a methodology to insert scan paths in a design that is specified on the Register Transfer Level (RT-Level). The results indicate that selecting registers on this level guarantees a reduction in DFT design time and improvement of fault coverage, without incurring high hardware overhead.     

一款百万门缀SOC芯片的可测性设到

本文介绍了一款基于65nm工艺的数字处理芯片的可测性设计,采用了边界扫描测试,存储器内建自测试和内部扫描测试技术。这些测试技术的使用为该芯片提供了方便可靠的测试方案,实验结果表明该设计的测试覆盖率符合工程应用要求。     

基于边界扫描技术的集成电路测试系统设计与实现

介绍了边界扫描的技术原理,及其在集成电路测试中的具体应用,并给出了一种基于边界扫描技术的板级集成电路测试系统的方案及实现。