RF circuit design aspects of spiral inductors on silicon

The design and optimization of spiral inductors on silicon substrates, the related layout issues in integrated circuits, and the effect of the inductor-Q an the performance of radio-frequency (RF) building blocks are discussed. Integrated spiral inductors with inductances of 0.5-100 nH and Q's up to 40 are shown to be feasible in very-large-scale-integration silicon technology. Circuit design aspects, such as a minimum inductor area, the cross talk between inductors, and the effect of a substrate contact on the inductor characteristics are addressed. Important RF building blocks, such as a bandpass filter, low-noise amplifier, and voltage-controlled oscillator are shown to benefit substantially from an improved inductor-Q     

An Assessment of µ-Czochralski, Single-Grain Silicon Thin-Film Transistor Technology for Large-Area, Sensor and 3-D Electronic Integration

Single-grain (SG) thin-film transistors (TFTs) fabricated inside location-controlled silicon grains using the mu-Czochralski method are benchmarked for analog and RF applications. Each silicon grain is defined by excimer laser recrystallization of polysilicon. Thin-film transistors may be fabricated in this manner on silicon or low-cost flexible plastic substrates as processing temperatures remain below 350degC, making the SG-TFT a potential enabling technology for large-area highly integrated electronic systems or systems-in-package with low manufacturing cost. Operational amplifier and voltage reference circuits of varying complexity were designed and measured in order to evaluate the effects of channel position and processing variation on analog circuits. A two-stage telescopic cascode operational amplifier fabricated in an experimental 1.5 mum SG-TFT technology demonstrates a DC gain of 55 dB (unity-gain bandwidth of 6.3 MHz), while a prototype CMOS voltage reference with a power supply rejection ratio (PSRR) of 50 dB is also demonstrated. With f_T comparable to single-crystal MOSFETs of comparable gate length, the SG-TFT can also enable RF circuits for wireless applications. A 12 dB gain RF cascode amplifier with on-chip inductors and operating in the 433 MHz ISM band is demonstrated. Excellent agreement with simulations is attained using a modified BSIM-SOI model extracted from measurements of experimental SG-TFT devices.     

High-performance large-inductance embedded inductors in thin array plastic packaging (TAPP) for RF system-in-package applications

We report the first demonstration of high-Q embedded inductors fabricated using a thin-array-plastic-packaging (TAPP) technology. The TAPP technology provides a platform that integrates digital, analog, RF integrated circuits, along with high-performance passive components for system-in-package implementation. Embedded inductors ranging from 14 to 300 nH were fabricated. All the inductors with inductance less than 100 nH exhibit self-resonant frequency above 1 GHz. For a 14-nH inductor, Q factor of 35 was achieved at 1.6 GHz and the self-resonance frequency was measured at 6.15 GHz.     

Substrate noise coupling through planar spiral inductor

While precious studies on substrate coupling focused mostly on noise induced through drain-bulk capacitance, substrate coupling from planar spiral inductors at radiofrequency (RF) via the oxide capacitance has not been reported. This paper presents the experimental and simulation results of substrate noise induced through planar inductors. Experimental and simulation results reveal that isolation between inductor and noise source is less than -30 dB at 1 GHz. Separation by distance reduces coupling by less than 2 dB in most practical cases. Practical examples reveal an obstacle in integrating RF tuned-gain amplifier with sensitive RF receiver circuits on the same die. Simulation results indicate that hollow inductors have advantages not only in having a higher self-resonant frequency, but also in reducing substrate noise as compared to conventional inductors. The effectiveness of using a broken guard ring in reducing inductor induced substrate noise is also examined     

The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application

The impact of CMOS technology scaling on the various radio frequency (RF) circuit components such as active, passive and digital circuits is presented. Firstly, the impact of technology scaling on the noise and linearity of the low-noise amplifier (LNA) is thoroughly analyzed. Then two new circuits, i.e., CMOS complementary parallel push-pull (CCPP) circuit and vertical-NPN (V-NPN) circuit for direct-conversion receiver (DCR), are introduced. In CCPP, the high RF performance of pMOS comparable to nMOS provides single ended differential RF signal processing capability without the use of a bulky balun. The use of parasitic V-NPN bipolar transistor, available in triple well CMOS technology, has shown to provide more than an order of magnitude improvement in 1/f noise and dc offset related problems, which have been the bottleneck for CMOS single chip integration. Then CMOS technology scaling for various passive device performances such as the inductor, varactor, MIM capacitor, and switched capacitor, is discussed. Both the forward scaling of the active devices and the inverse scaling of interconnection layer, i.e., more interconnection layers with effectively thicker total dielectric and metal layers, provide very favorable scenario for all passive devices. Finally, the impact of CMOS scaling on the various digital circuits is introduced, taking the digital modem blocks, the various digital calibration circuits, the switching RF power amplifier, and eventually the software defined radio, as examples.     

RF power amplifier employing a frequency-tunable impedance matching network based on coupled inductors

Coupled inductors can be used as tunable inductances. Employing coupled inductors in the output impedance matching network of an RF power amplifier leads to superior performance when operating in more than one frequency band. As proof of this concept, the design of a dual-band RF power amplifier for the 200 and 300 MHz bands is presented. Simulation and measurement results validate the technique.     

High-performance inductors on plastic substrate

Wafer-transfer technology (WTT) has been applied to transfer RF inductors from a silicon wafer to an opaque plastic substrate (FR-4). By completely eliminating silicon substrate, the high performance of integrated inductors (Q-factor > 30 for inductance /spl sim/3 nH with resonant frequency /spl sim/23 GHz) has been achieved. Based on the analysis of a modified /spl pi/-network model, our results suggest that the performance limitation is switched from being a synthetic mechanism of substrate and metal-ohmic losses on low resistivity Si-substrate to merely a metal-ohmic loss on FR-4. Thus, the inductor patterns, which are optimized currently for RFICs on silicon wafer, can be further optimized to take full advantage of the WTT on new substrate from the newly obtained design freedom.     

Surface-passivated high-resistivity silicon as a true microwave substrate

This paper addresses the properties of a surface-passivated (enhanced) high-resistivity silicon (HRS) substrate for use in monolithic microwave technology. The detrimental effects of conductive surface channels and their variations across the wafer related to the local oxide and silicon/silicon-dioxide interface quality are eliminated through the formation of a thin amorphous layer at the wafer surface. Without passivation, it is found that the surface channels greatly degrade the quality of passive components in HRS by masking the excellent properties of the bulk HRS substrate and by causing a spread in parameters and peak values across the wafer. Moreover, it is seen that the surface passivation leads to excellent agreement of the characteristics of fabricated components and circuits with those predicted by electromagnetic (EM) simulation based on the bulk HRS properties. This is experimentally verified for lumped (inductors and transformers) and distributed (coplanar waveguide, Marchand balun) passive microwave components, as well as for a traveling-wave amplifier, through which also the integration of transistors on HRS and the overall parameter control at circuit level are demonstrated. The results in this paper indicate the economically important possibility to transfer microwave circuit designs based on EM simulations directly to the HRS fabrication process, thus avoiding costly redesigns.     

The triamplifier, a new circuit element, and its use in active filters

A new operational amplifier circuit building block-the triamplifier-is described. This is basically a symmetrical amplifier with three inputs and three outputs. The triamplifier can be used to realize high-performance floating inductors, and appears to offer significant advantages over alternative circuits.     

Fabrication of ultrathin SOI by SIMOX water bonding (SWB)

Ultrathin silicon-on-insulator (SOI) layers of separation by implantation of oxygen (SIMOX) wafers have been transferred onto thermally oxidized silicon wafers by wafer bonding technology. Due to the technical availability and the complementary nature of SIMOX and wafer bonding approaches, SIMOX wafer bonding (SWB) solves some of the respective major difficulties faced by both SIMOX and wafer bonding for device quality ultrathin SOI mass production: the preparation of adequate buried oxide (including its interfaces) in SIMOX and the uniformly thinning one of the bonded wafers to less than 0.1 μm in wafer bonding. The effect of positive charges in the oxide on bondability of ultrathin SOI films and possible applications of SWB will also be outlined.     

Single-grain Si thin-film transistors SPICE model,analog and RF circuit applications

Single-grain thin-film transistors (SG-TFTs) fabricated inside location-controlled using μ-Czochralski process exhibit SOI-FETs like performance despite processing temperatures remaining below 350 °C. Thus, the SG-TFT is a potential technology for large-area highly-integrated electronic system and system-in-package, taking advantage of the system-on-flexible substrate and low manufacturing cost capabalities. The SG-TFT is modeled based on the BSIMSOI SPICE model where the mobility parameter is modified to fit the SG-TFT behavior. Therefore, analog and RF circuits can be designed and benchmarked. A two-stage telescopic cascode operational amplifier fabricated in a prototype 1.5 μm SG-TFT technology demonstrates DC gain of 55 dB and unity-gain bandwidth of 6.3 MHz. A prototype CMOS voltage reference demonstrates a power supply rejection ratio (PSRR) of 50 dB. With unity-gain frequency, f_T, in the GHz range, the SG-TFT can also enable RF circuits for wireless applications. A 12 dB gain RF cascode amplifier with integrated on-chip inductors operating in the 433 MHz ISM band is demonstrated.     

SOI/bulk hybrid technology on SIMOX wafers for high performancecircuits with good ESD immunity

A new SOI/bulk hybrid technology with devices on both the thin film and the bottom substrate of SIMOX wafers has been studied. By fabricating ESD protection circuits on the substrate of SIMOX wafers, ESD reliability of high performance CMOS SOI circuits can be significantly improved. Despite the higher surface defect density and micro-roughness on the bottom substrate of SIMOX wafers compared to ordinary bulk wafers, similar electron mobility, intrinsic thermal oxide properties and hot-carrier degradation are observed among MOSFET's fabricated on the different substrates. Thus, the hybrid technology is capable of combining the advantages both of SOI and bulk technology in fabricating high performance circuits     

Design of RF integrated circuits using SiGe bipolar technology

We report on design aspects and the implementation of radio-frequency integrated circuits using TEMIC's SiGe technology. The differences between the device parameters of silicon bipolar junction transistor and silicon germanium heterojunction bipolar transistor technology and their influence on IC design are discussed. Design and measurement results of RFICs, including low noise amplifier, power amplifier, and single-pole, double-throw antenna switch for application in a 1.9 GHz digital enhanced cordless telecommunications RF front end are presented     

IIP2 Calibration by Injecting DC Offset at the Mixer in a Wireless Receiver

A major contributor to degraded input-referred second-order intercept point (IIP2) in integrated RF systems-on-chips is local oscillator (LO) leakage to the input of RF circuits. In this brief, we present a digital calibration technique for improving IIP2 by injecting controlled dc offset at the mixer output through a three-port network of switched-capacitor filters. The dc offset at mixer output gets up-converted to LO frequency at the input of RF circuits due to poor reverse isolation of the receiver front-end. By controlling the amplitude of the injected dc, IIP2 degradation due to LO leakage at the input of RF amplifiers can be compensated. Mathematical analysis is presented and supported by measurement data from a quad-band GSM/GPRS receiver implemented in 90-nm digital CMOS process. Calibrated IIP2 of 50 dBm is reported for the receiver at low-noise amplifier input.     

2.4GHz全集成CMOS Doherty功率放大器

采用0.18μm CMOS工艺设计并制作了一个2.4 GHz全集成CMOS Doherty功率放大器.着重考虑了片上螺旋电感的回流路径对电感模型的影响,并在设计中使用了一种新颖的螺旋电感版图结构来避免回流路径的影响.实测结果表明该功率放大器增益达到16dB,1dB压缩点为20.5dBm,峰值输出功率和对应功率附加效率分别为21.2dBm和20.4％,整个芯片面积为2.8mm×1.7mm.     

Micromachined planar inductors on silicon wafers for MEMSapplications

This paper describes three micromachined planar inductors (a spiral type, a solenoid type, and a toroidal meander type) with electroplated nickel-iron permalloy cores which have been realized on a silicon wafer using micromachining techniques. The electrical properties among the fabricated inductors are compared and the related fabrication issues are discussed, with emphasis on the low-temperature CMOS-compatible process, the high current-carrying capacity, the high magnetic flux density, the closed magnetic circuits, and the low product cost. The micromachined on-chip inductors can be applied for magnetic microelectromechanical systems devices, such as micromotors, microactuators, microsensors, and integrated power converters, which envisages new micropower magnetics on a chip with integrated circuits     

Alternative realisations of switched-capacitor floating inductors

Several switched-capacitor circuits simulating grounded and floating inductors have been published recently. Several alternative realizations are presented of s.c. inductors using one operational amplifier, which can be derived from a configuration reported previously.     

SIMOX硅片埋氧层垂直方向热导率的测量

提出了一种简单、有效而且准确的测量SOI硅片埋氧层垂直方向热导率的方法,并采用这种方法测量了用SIMOX工艺制作的SOI硅片的埋氧层垂直方向的热导率.测量结果显示至少在5 5nm以上的尺度上对于SIMOX硅片的埋氧层垂直方向经典的热导率定义仍然成立,且为一明显小于普通二氧化硅的热导率(1 4W/mK)的常数1 0 6W/mK .测量中发现硅/二氧化硅边界存在边界热阻,并测量了该数值.结果表明,边界热阻在SOI器件尤其是薄二氧化硅背栅的双栅器件热阻的计算中不可忽略.     

Class E high-efficiency switching-mode tuned power amplifier with only one inductor and one capacitor in load network-approximate analysis

A class E high-efficiency switching-mode tuned power amplifier can be realized with only one inductor and one capacitor in the load network; previously published class E circuits contained at least two inductors and two capacitors. Switch conduction duty ratio and network loaded Q cannot be chosen independently as they can in the circuits published previously. This simplified circuit is appropriate for applications in which the harmonic content and the phase-modulation noise of the output are not important criteria, e.g. in providing RF energy for heating, for generation of sparks, arcs, or plasmas, for communications jamming, or for input drive to a higher power stage; or to a rectifier so that the entire circuit functions as a high-efficiency DC/DC converter. Experimental results and an approximate analysis are given; the two are in good-to-fair agreement.     

Miniature 3-D inductors in standard CMOS process

The structure of a miniature three-dimensional (3-D) inductor is presented in this paper. The proposed miniature 3-D inductors have been fabricated in a standard digital 0.35-μm one-poly-four-metal (1P4M) CMOS process. According to the measurement results, the self-resonance frequency f_SR of the proposed miniature 3-D inductor is 34% higher than the conventional stacked inductor. Moreover, the inductor occupies only 16% of the area of the conventional planar spiral inductor with the same inductance and maximum quality factor Q_max. A 2.4-GHz CMOS low-noise amplifier (LNA), which utilized the proposed miniature 3-D inductors, has also been fabricated. By virtue of the small area of the inductor, the size and cost of the radio frequency (RF) chip can be significantly reduced