Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS transistors by taking into account the presence of source/drain contact plugs. The accuracy of the model is tested by comparing the modeled results with the results obtained from three-dimensional (3-D) Monte-Carlo simulations and two-dimensional (2-D) device simulations over a wide range of channel length and oxide thickness. The model is also used to study the dependence of parasitic capacitance on gate length, gate electrode thickness, gate oxide thickness, gate dielectric constant, and spacer width.     

In-process voltage stressing to increase reliability of MOS integrated circuits

Time-dependent dielectric breakdown of gate oxides is one of the principal failure mechanisms of MOS integrated circuits. Voltage stressing of completed devices, which has been used to screen oxide defects and to thereby increase product reliability, is less effective with scaled high-density MOS integrated circuits because of limitations in the voltage which can be applied. Inprocess voltage stressing of silicon wafers, prior to completion of wafer processing, offers a feasible technique for achieving an effective voltage screen. Several possible techniques for inprocess voltage stressing are described, and the advantages and limitations of these are outlined. Data are presented showing typical fast-ramp dielectric breakdown distributions for MOS transistor arrays with an oxide thickness of 35 and 50 nm. Time-dependent dielectric breakdown distribution data on devices from the same wafers indicate that with all MOS transistors of an integrated circuit connected in parallel, as in one type of inprocess voltage stressing, defective oxide sites can be screened in periods of time ranging from a few seconds to hours. Inprocess voltage stressing, by decreasing susceptibility of completed devices to time-dependent dielectric breakdown, can substantially increase MOS integrated circuit reliability.     

具有栅介质电场屏蔽作用的新型GaN纵向槽栅MOSFET器件设计

基于氮化镓(GaN)等宽禁带(WBG)半导体的金氧半场效应晶体管(MOSFET)器件在关态耐压下,栅介质中存在与宽禁带半导体临界击穿电场相当的大电场,致使栅介质在长期可靠性方面受到挑战。为了避免在GaN器件中使用尚不成熟的p型离子注入技术,提出了一种基于选择区域外延技术制备的新型GaN纵向槽栅MOSFET,可通过降低关态栅介质电场来提高栅介质可靠性。提出了关态下的耗尽区结电容空间电荷竞争模型,定性解释了栅介质电场p型屏蔽结构的结构参数对栅介质电场的影响规律及机理,并通过权衡器件性能与可靠性的关系,得到击穿电压为1 200 V、栅介质电场仅0.8 MV/cm的具有栅介质长期可靠性的新型GaN纵向槽栅MOSFET。     

Modeling for reduced gate capacitance of nanoscale MOSFETs

As gate oxides become thinner, in conjunction with scaling of MOS technologies, a discrepancy arises between the gate oxide capacitance and the total gate capacitance, due to the increasing importance of the carrier distributions in the polysilicon electrodes. For the first time, based on least-squares curve fit, we quantitatively explore the impact of quantum mechanics effects in polysilicon gate region on gate capacitance. Comparing the theoretical curves with an extensive set of simulation ones has validated this model.     

D.C. measurement of the space charge capacitance and impurity profile beneath the gate of an MOST

An analysis of the MOS Transistor with bias between the source and substrate has shown that when the surface is weakly inverted, the silicon space charge capacitance over a wide range of temperature and bias can be obtained from the change in gate voltage required to maintain a constant channel current. The substrate impurity profile beneath the gate oxide can then be calculated from capacitance-bias measurements.     

Gate capacitance attenuation in MOS devices with thin gatedielectrics

As gate oxides become thinner, in conjunction with scaling of MOS technologies, a discrepancy arises between the gate oxide capacitance and the total gate capacitance, due to the increasing importance of the carrier distributions in the silicon and polysilicon electrodes. For the first time, we quantitatively explore the combined impact of degenerate carrier statistics, quantum effects, and the semiconducting nature of the gate electrode on gate capacitance. Only by including all of these effects can we successfully model the capacitance-voltage behavior of sub-10 nm MOS capacitors. For typical devices, we find the gate capacitance to be 10% less than the oxide capacitance, but it can be attenuated by 25% or more for 4 nm oxides with polysilicon gates doped to less than 10²⁰ cm^-3     

Empirically Verified Thermodynamic Model of Gate Capacitance and Threshold Voltage of Nanoelectronic MOS Devices With Applications to HfO2 and ZrO2 Gate Insulators

A thermodynamic variational model derived by minimizing the Helmholtz free energy of the MOS device is presented. The model incorporates an anisotropic permittivity tensor and accommodates a correction for quantum-mechanical charge confinement at the dielectric/substrate interface. The energy associated with the fringe field that is adjacent to the oxide is of critical importance in the behavior of small devices. This feature is explicitly included in our model. The model is verified using empirical and technology-computer-aided-design-generated capacitance-voltage data obtained on MOS devices with ZrO₂, HfO₂, and SiO₂ gate insulators. The model includes considerations for an interfacial low-k interface layer between the silicon substrate and the high-k dielectric. This consideration enables the estimation of the equivalent oxide thickness. The significance of sidewall capacitance effects is apparent in our modeling of the threshold voltage (V_th) for MOS capacitors with effective channel length at 30 nm and below. In these devices, a variation in high-k permittivity produces large differences in V_th. This effect is also observed in the variance of V_th, due to dopant fluctuation under the gate.     

镶嵌在超薄SiO_2层中的纳米硅的库仑阻塞现象

采用等离子体氧化和逐层 (layer by layer)生长技术在等离子体增强化学气相沉积 (PECVD)系统中原位制备了 Si O2 /nc- Si/Si O2 的双势垒纳米结构 ,从 nc- Si薄膜的喇曼谱中观察到结晶峰 ,估算出该薄膜的晶化成分和平均晶粒尺寸分别约为 6 5 %和 6 nm.通过对该纳米结构的电容 -电压 (C- V)测量 ,研究了载流子的隧穿和库仑阻塞特性 .在不同测试频率的 C- V谱中观测到了由于载流子隧穿引起的最大电容值抬升现象 .通过低温低频 C- V谱 ,计算出该结构中 nc- Si的库仑荷电能为 5 7me V.     

Frequency response of charge transfer in MOS inversion layers

The dynamics of charge transfer from a reservoir into an MOS inversion layer, which limits the frequency response of an MOS transistor or a charge-coupled device, is investigated. Using Berman and Kerr's model of space-charge capacitance in the semiconductor, a small-signal distributed model is developed for an MOS structure which transfers charge in an inversion channel due to a variation in the gate voltage. The dynamics of the charge transfer is characterized by a time constant which is determined by the length of the inversion channel and its mobility. Experimental data of gate capacitance vs frequency, taken from a test structure with a diffused source/drain well, are satisfactorily fitted by theoretical curves derived from the model. The channel mobility is precisely determined from the adjusted time constant. The influence of interface states on the capacitance-frequency relationship is also briefly discussed.     

Anticipation of nitrided oxides electrical thickness based on XPS measurement

Plasma nitridation of thermally grown oxide films has proven to be an excellent gate dielectric in meeting the electrical requirements of the 65 nm node. As the 65 nm device performance is very sensitive to both physical thickness and nitrogen dose of these dielectric films, it is highly desirable to predict the electrical properties of such films. We present a simple physical model to forecast the capacitance-equivalent thickness (CET) of nMOS devices for 65 nm technology. The model is based on the total nitrogen dose and the dielectric physical thickness, both given by in-line X-ray photoelectron spectroscopy (XPS) measurement of the plasma nitrided gate dielectric. This model uses an estimated gate oxide dielectric constant, the gate depletion capacitance and the inversion layer capacitance. A good correlation is obtained between calculated and measured CET for plasma nitrided oxides from 19 to 30 Å CET and for a large range of incorporated nitrogen doses.     

0.86-nm CET Gate Stacks With Epitaxial$hboxGd_2hboxO_3$High-$k$Dielectrics and FUSI NiSi Metal Electrodes

In this letter, ultrathin gadolinium oxide$(hboxGd_2hboxO_3)$high-$k$gate dielectrics with complementary-metal-oxide-semiconductor (CMOS)-compatible fully silicided nickel-silicide metal gate electrodes are reported for the first time. MOS capacitors with a$hboxGd_2hboxO_3$thickness of 3.1 nm yield a capacitance equivalent oxide thickness of$ CET = hbox0.86 hboxnm$. The extracted dielectric constant is$k = hbox13-hbox14$. Leakage currents and equivalent oxide thicknesses of this novel gate stack meet the International Technology Roadmap for Semiconductors targets for the near term schedule and beyond.     

氮注入多晶硅栅对超薄SiO_2栅介质性能的影响

p+ 多晶硅栅中的硼在 Si O2 栅介质中的扩散会引起栅介质可靠性退化 ,在多晶硅栅内注入 N+ 的工艺可抑制硼扩散 .制备出栅介质厚度为 4 .6 nm的 p+栅 MOS电容 ,通过 SIMS测试分析和 I- V、C- V特性及电应力下击穿特性的测试 ,观察了多晶硅栅中注 N+工艺对栅介质性能的影响 .实验结果表明 :在多晶硅栅中注入氮可以有效抑制硼扩散 ,降低了低场漏电和平带电压的漂移 ,改善了栅介质的击穿性能 ,但同时使多晶硅耗尽效应增强、方块电阻增大 ,需要折衷优化设计 .     

A simple model for the overlap capacitance of a VLSI MOS device

A simple approximate analytical expression for the overlap capacitance between gate- and source-drain of a VLSI MOS device is derived. The expression takes into account finite polysilicon gate thickness, source-drain junction depth and different dielectric constants of silicon and oxide. A numerical procedure is also described to calculate the exact overlap capacitance with fringing, using the solution of Laplace's equation. A comparison is made to check the accuracy of the analytical expression. Good agreement is found. Experimently obtained gate-source capacitance curves are described. Overlap capacitance and fringing component values derived from these curves are also in good agreement to those predicted by the model.     

HfTiO氮化退火对MOS器件电特性的影响

采用磁控溅射方法,在Si衬底上淀积HfTiO高k介质,研究了NO、N2O、NH3和N2不同气体退火对MOS电特性的影响。结果表明,由于NO氮化退火能形成类SiO2/Si界面特性的HfTiSiON层,所制备的MOS器件表现出优良的电特性,即低的界面态密度、低的栅极漏电和高的可靠性。根据MOS器件栅介质(HfTiON/HfTiSiON)物理厚度变化(ΔTox)和电容等效厚度变化(ΔCET)与介质(HfTiON)介电常数的关系,求出在NO气氛中进行淀积后退火处理的HfTiON的介电常数达到28。     

Capacitance-voltage characterization of fully silicided gated MOS capacitor

This paper investigates the capacitance-voltage (C-V) measurement on fully silicided (FUSI) gated metal-oxide-semiconductor (MOS) capacitors and the applicability of MOS capacitor models. When the oxide leak-age current of an MOS capacitor is large, two-element parallel or series model cannot be used to obtain its real C-V characteristic, A three-element model simultaneously consisting of parallel conductance and series resistance or a four-element model with further consideration of a series inductance should be used. We employed the three-element and the four-element models with the help of two-frequency technique to measure the Ni FUSI gated MOS capacitors. The results indicate that the capacitance of the MOS capacitors extracted by the three-element model still shows some frequency dispersion, while that extracted by the four-element model is close to the real capacitance, showing little frequency dispersion. The obtained capacitance can be used to calculate the dielectric thickness with quantum effect correction by NCSU C-V program. We also investigated the influence of MOS capacitor's area on the measurement accuracy. The results indicate that the decrease of capacitor area can reduce the dissipation fac-tor and improve the measurement accuracy. As a result, the frequency dispersion of the measured capacitance is significantly reduced, and real C-V characteristic can be obtained directly by the series model. In addition, this pa-per investigates the quasi-static C-V measurement and the photonic high-frequency C-V measurement on Ni FUSI metal gated MOS capacitor with a thin leaky oxide. The results indicate that the large tunneling current through the gate oxide significantly perturbs the accurate measurement of the displacement current, which is essential for the quasi-static C-V measurement. On the other hand, the photonic high-frequency C-V measurement can bypass the leakage problem, and get reliable low-frequency C-V characteristic, which can be used to evaluate whether the full silicidation has completed or not, and to extract the interface trap density of the SiO2/Si interface.     

Gate length dependent polysilicon depletion effects

Degradation of MOS gate capacitance in the inversion region becomes worse as the gate length is scaled down, according to a new experiment. Namely, the polysilicon depletion effect has gate length dependence. The origin of this gate length-dependent polydepletion effect has been modeled and verified by using device simulation. As a result, the gradient of dopant distribution resulting from ion implantation is shown to be an additional potential drop in the polygate. In addition, the enlarged depletion width at the gate sidewall can worsen the polydepletion effect for very-small MOSFETs     

Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT /spl sim/ 1 nm) SiO/sub 2/ and high-/spl kappa/ gate stacks

Building on a previously presented compact gate capacitance (C/sub g/-V/sub g/) model, a computationally efficient and accurate physically based compact model of gate substrate-injected tunneling current (I/sub g/-V/sub g/) is provided for both ultrathin SiO/sub 2/ and high-dielectric constant (high-/spl kappa/) gate stacks of equivalent oxide thickness (EOT) down to /spl sim/ 1 nm. Direct and Fowler-Nordheim tunneling from multiple discrete subbands in the strong inversion layer are addressed. Subband energies in the presence of wave function penetration into the gate dielectric, charge distributions among the subbands subject to Fermi-Dirac statistics, and the barrier potential are provided from the compact C/sub g/-V/sub g/ model. A modified version of the conventional Wentzel-Kramer-Brillouin approximation allows for the effects of the abrupt material interfaces and nonparabolicities in complex band structures of the individual dielectrics on the tunneling current. This compact model produces simulation results comparable to those obtained via computationally intense self-consistent Poisson-Schro/spl uml/dinger simulators with the same MOS devices structures and material parameters for 1-nm EOTs of SiO/sub 2/ and high-/spl kappa//SiO/sub 2/ gate stacks on (100) Si, respectively. Comparisons to experimental data for MOS devices with metal and polysilicon gates, ultrathin dielectrics of SiO/sub 2/, Si/sub 3/N/sub 4/, and high-/spl kappa/ (e.g., HfO/sub 2/) gate stacks on (100) Si with EOTs down to /spl sim/ 1-nm show excellent agreement.     

A methodology for measuring the gate-drain capacitance of CMOSdevices

In this paper, the author presents a new methodology for measuring the gate drain capacitance of CMOS devices using an accelerated dc measurement scheme. The gate-drain capacitance was measured using a floating gate MOS transistor, i.e., an MOS transistor with an additional capacitor placed in series with the gate oxide capacitance. This was implemented within a standard p-well CMOS process using two matched transistors. The top capacitance couples charge onto the gate oxide capacitor and the gate-drain capacitor. The amount of coupling is determined by the ratio of these two capacitors     

Chemical reaction concerns of gate metal with gate dielectric in Tagate MOS devices: an effect of self-sealing barrier configurationinterposed between Ta and SiO2

Chemical reaction of gate metal with gate dielectric for Ta gate MOS devices has been experimentally investigated both by electrical and physical measurements: capacitance-voltage (C-V), current-voltage (I-V), transmission electron microscopy (TEM), energy dispersive X-ray (EDX), electron diffraction measurements. In spite of the chemical reaction of Ta with SiO₂ consuming ~1-nm-thick in gate oxide, the interface trap densities of ~2×10¹⁰ cm^-2 eV ^-1 at midgap and ideal channel mobility characteristics have been observed in the Ta gate MOS devices with 5.5-nm-thick thermal oxide gate dielectric. Considering the experimental data with theoretical calculation based on thermodynamics together, a barrier layer model has been developed for the Ta gate MOS systems. The physical mechanism involved is probably self-sealing barrier layer formation resulting from the chemical reaction kinetics in the free-energy change of Ta-Si-O system     

Effect of silicon-gate resistance on the frequency response of MOS transistors

A polycrystalline silicon gate has finite sheet resistivity, typically in the range of tens of ohms per square. The resulting gate resistance and the gate capacitance form a distributed RC network. The gate voltages appearing along this distributed network, hence, the summation drain current, is delayed from the input voltage applied to the contact pad(s). The delay of the distributed RC network is analyzed for both small and large signals. The analysis shows that when the RC time constant of the gate is comparable to the period of the signal, the frequency response is degraded. This time constant varies as the square of the gate width. For a gate width in the fractional millimeter range (typical of output MOS transistors in an integrated circuit), the time constant may be in the 100-ns range; for gate width in the 10-µ range, in the subnanosecond range.